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Full text of "National Semiconductor MOS-LSI Databook 1977"

a 



Edge Index 
by Product Family 



Clocks 

Counters/Timers 

Electronic Organ Circuits 

TV Circuits 

Analog to Digital (A/D) Converters 

Communications/CB Radio Circuits 

Watches 

Calculators 

Controller Oriented Processor Systems (COPS) 

Keyboard Encoder Circuits 

Interface Drivers 

Displays 

Clock Modules 

Custom MOS/LSI 




Table of Contents 



Edge Index by Product Family 1 

Alpha-Numerical Index 6 

CLOCKS - SECTION 1 

MM5309 Digital Clock 1-2 

MM531 1 Digital Clock 1-2 

MM5312 Digital Clock 1-2 

MM5313 Digital Clock 1-2 

MM5314 Digital Clock 1-2 

MM5315 Digital Clock 1-2 

MM5316 Digital Alarm Clock 1-9 

MM5318 TV Digital Clock 4-2 



14 
14 
21 
27 
33 
38 



MM5370 Digital Alarm Clock 1 

MM5371 Digital Alarm Clock 1 

MM5375XX Series Clocks 1 

MM5376XX Series Clocks 1 

MM5377 Auto Clock 1 

MM5378 Auto Clock 1 

MM5379 Auto Clock 1-38 

MM5382 Digital Calendar Clock Radio Circuit 1-43 

MM5383 Digital Calendar Clock Radio Circuit 1-43 

MM5384 LED Display Digital Clock Radio Circuit 1-50 

MM5385 Digital Alarm Clock 1-56 

MM5386 Digital Alarm Clock 1-56 

MM5387AA Digital Alarm Clock 1-62 

MM5396 Digital Alarm Clock 1-56 

MM5397 Digital Alarm Clock 1-56 

MM5402 Digital Alarm Clock 1-68 

MM5405 Digital Alarm Clock 1-68 

MM53108 Digital Alarm Clock 1-62 

AN-143 Using National Clock Integrated Circuits in Timer Applications 1-74 

COUNTERS/TIMERS - SECTION 2 

MM5307 Baud Rate Generator/Programmable Divider 2-2 

MM5369 17-Stage Programmable Oscillator/Divider 2-7 

MM5865 Universal Timer 2-10 

MM53107 17-Stage Oscillator/Divider 2-20 

AN-168 MM5865 Universal Timer Applications 2-23 

AN-169 A 4-Digit, 7-Function Stopwatch/Timer 2-33 

ELECTRONIC ORGAN CIRCUITS - SECTION 3 

MM5554 Frequency Divider 3-2 

MM5555 Chromatic Frequency Generator 3-4 

MM5556 Chromatic Frequency Generator 3-4 

MM5559 Serial-to-Parallel Converter 3-6 

MM5823 Frequency Divider 3-8 

MM5824 Frequency Divider 3-8 



ELECTRONIC ORGAN CIRCUITS - SECTION 3 (Continued) 

MM5832 Chromatic Frequency Generator 3_1 1 

MM5833 Chromatic Frequency Generator 3.^ 

MM5837 Digital Noise Source 3 . 14 

MM5871 Rhythm Pattern Generator 3_1 6 

MM5891 MOS Top Octane Frequency Generator 3_ig 

TV CIRCUITS - SECTION 4 

t-M 1889* TV Video Modulator 4 _ 48 

MM5318 TV Digital Clock 4 _ 2 

MM5320 TV Camera Sync Generator 4 _ 6 

MM5321 TV Camera Sync Generator 4 _1 2 

MM5322 Color Bar Generator Chip 4 _1 8 

MM5840 TV Channel Number (16 Channels) and Time Display Circuit 4-23 

MM5841 TV Channel Number and Time Readout Circuit 4-28 

MM5878 Remote Control Potentiometer 4-57 

MM53100 Programmable TV Timer/ Alarm Clock 4 -32 

MM53104* TV Game Clock Generator (NTSC) with reference to MM531 14 TV Game Clock Generator (PAL). . , . 4-50 

MM53105 Programmable TV Timer/Alarm Clock 4 _3 2 

MM57100* TV Game Circuit (NTSC) with reference to MM57105 TV Game Circuit (PAL) 4-37 

MM58106 Digital Clock and TV Display Circuit 4-53 

ANALOG TO DIGITAL (A/D) CONVERTERS - SECTION 5 

LF13300 Integrating A/D Analog Building Block 5_2 

MM5330 4 1/2-Digit Panel Meter Logic Block 5.23 

MM5863 12-Bit Binary A/D Building Block 5 . 30 

AN-155 Digital Voltmeters and the MM5330 5.35 

AN-156 Specifying A/D and D/A Converters 5 . 44 

COMMUNICATIONS/C.B. RADIO CIRCUITS - SECTION 6 

MM5303 Universal Fully Asynchronous Receiver/Transmitter 6-2 

MM5393 Push Button Telephone Dialer 6 -8 

MM5395 TOUCH-TONE® Generator .:................... 6-11 

MM55104 PLL Frequency Synthesizer g.1g 

MM55106 PLL Frequency Synthesizer 6 -16 

MM55108 PLL Frequency Synthesizer with Receive/Transmit Mode 6-20 

MM551 10 PLL Frequency Synthesizer with Receive/Transmit Mode 6-20 

MM55114 PLL Frequency Synthesizer 6-16 

MM551 16 PLL Frequency Synthesizer 6-16 

WATCHES - SECTION 7 

MM5829 LED Watch Circuit 7 . 2 

MM5860 LED Watch Circuit ........... 76 

MM5879 RC Circuit 7 1 2 

MM5880 LED Watch Circuit 7-6 

MM5885 Direct Drive LED Watch 7-13 

MM5886 Direct Drive LED Watch 7 _ 13 

MM5889 RC Circuit 7-12 

MM5890 LCD Chronograph Circuit 7 . 2 q 

MM5899 RC Circuit 7 . 12 

MM58104 Direct Drive LED Watch 7-27 

MM581 15 Digitally Tuned, Direct Drive, 6-Function LED Watch 7 _3 2 

MM581 17 LCD Watch Circuit . . . . 7-40 

MM581 18 LCD Watch Circuit 7-40 

MM581 19 LCD Watch Circuit 7-40 

*TV Game Kit #SK1 1 15 includes this circuit TOUCH-TONE® is a Registered Trademark of Bell Telephone 



3 



WATCHES - SECTION 7 (Continued) 

MM58120 LCD Watch Circuit 7-40 

MM58127 LCD Watch Circuit 7-47 

MM58128 LCD Watch Circuit 7-47 

MM58129 LCD Watch Circuit 7-47 

MM58130 LCD Watch Circuit 7-47 

MM58601 Two Time Zone LED Watch Circuit 7-6 

MM58801 Two Time Zone LED Watch Circuit 7-6 

CALCULATORS - SECTION 8 

MM5734 8-Function, Accumulating Memory Calculator 8-2 

MM5737 8 Digit, 4-Function, Floating Decimal Point Calculator 8-8 

MM5758 Scientific Calculator 8-14 

MM5760 Slide Rule Calculator 8-26 

MM5762 Financial Calculator 8-35 

MM5763 Statistical Calculator 8-46 

MM5764 Conversion Calculator 8-56 

MM5765 Calculator Programmer 8-66 

MM5766 Calculator Programmer 8-76 

MM5767 Slide Rule Calculator 8-80 

MM5777 6-Digit, 4-Function, Floating Decimal Point Calculator 8-84 

MM5780 Educational Toy Calculator 8-90 

MM5791 7-Function, Accumulating Memory Calculator 8-96 

MM5794 7-Function, Accumulating Memory, Vacuum Fluorescent Display Calculator 8-105 

MM5795 7-Function, Accumulating Memory, Vacuum Fluorescent Display Calculator 8-114 

MM57103 Scientific Calculator Circuit 8-123 

MM57104 Scientific Calculator Circuit 8-132 

MM57123 Financial Calculator 8-141 

MM57135 Scientific Calculator ROM 8-153 

MM57136 RPN Scientific Calculator Control ROM 8-157 

AN 112 Calculator Chip Makes a Counter 8-163 

AN-1 19 Calculator Learns to Keep Time 8-169 

AN-149 Handheld Calculator Battery Systems 8-177 

AN-176 Using Standard National Calculators in Industrial and Microprocessor Applications 8-181 

CONTROLLER ORIENTED PROCESSOR SYSTEMS (COPS) - SECTION 9 

National's Controller Oriented Processor Systems 9 '2 

MM5781 Controller Oriented Processor System 9"3 

MM5782 Controller Oriented Processor System 93 

MM5785 RAM Interface Chip 9 " 15 

MM5788 Printer Interface Chip 9 " 21 

MM5799 Controller Oriented Processor 9-27 

MM57109 Number Processing Unit 9 " 39 

MM57126 COPS Memory 9 " 40 

MM57140 Controller Oriented Processor 9 '46 

KEYBOARD ENCODER CIRCUITS - SECTION 10 

MM5740 90-Key Keyboard Encoder 1Q -2 

MM5745 78-Key Keyboard Encoder 10-10 

MM5746 78-Key Keyboard Encoder 10-10 

MM54C922/MM74C922 16-Key Encoder 10-16 

MM54C923/MM74C923 20-Key Encoder 10-16 

AN- 128 Microprocessor Mates with MOS/LSI Keyboard Encoder 10-21 

AN-139 MOS Encoder Plus PROM Yield Quick Turnaround Keyboard Systems 10-27 



INTERFACE DRIVERS - SECTION 1 1 

Display Driver Selection Guide 11-2 

CD45118M/CD4511BC BCD-to-7-Segment Latch/Decoder/Driver 11-4 

DS7664/DS8664 14-Digit Decoder/Driver with Low Battery Indicator 11-9 

DS8665 14-Digit Decoder/Driver (Hi-Drive) 11-12 

DS8666 14-Digit Decoder 'Driver (P.O.S.) 11-15 

DS8692 Printing Calculator Interface Set 11-18 

DS8693 Printing Calculator Interface Set 11-18 

DS8694 Printing Calculator Interface Set 11-18 

DS8867 8-Segment Driver 11-25 

DS8868 12-Digit Decoder/Driver 1 1-27 

DS8871 Saturating LED Cathode Driver 11-29 

DS8872 Saturating LED Cathode Driver 11-29 

DS8873 Saturating LED Cathode Driver 11-29 

DS8874 9-Digit Shift Input LED Driver 11-31 

DS8877 6-Digit LED Driver 11-33 

D38892 Programmable Hex LED Digit Driver 11-35 

DS8977 Saturating LED Cathode Driver 1 1-29 

DS75491 MOS-to-LED Quad Segment Driver 1 1-37 

DS75492 MOS-to-LED Hex Digit Driver 11-37 

DS75493 Quad LED Segment Driver 11-40 

MM54C48/MM74C48 BCD-to-7-Segment Decoder 11-42 

MM54C915/MM74C915 7-Segment-to-BCD Converter 11-46 

DISPLAYS -SECTION 12 

NSA 1100 Series 0.100 Inch 9-Digit LED Display 12-2 

NSA 1298 0.110 Inch 9 Digit LED Display 12-6 

NSA 5120 1/8 Inch 12-Digit LED Display 12-8 

NSA 5140 1/8 Inch 14-Digit LED Display 12-10 

NSB 5917 0.5 Inch 5-Digit Numeric Display 12-12 

NSB 5921 0.5 Inch 5-Digit Numeric Display 12-12 

NSB 5922 0.5 Inch 5-Digit Numeric Display 12-12 

Multi Digit LED Numeric Series . 12-14 

AN-170 Mounting Techniques for Multidigit LED Numeric Display 12-22 

CLOCK MODULES - SECTION 13 

MA1002 LED Display Digital Electronic Clock Module 13-2 

MA1003 12 Vqc Automotive/Instrument Clock Module 13-8 

M A1010 LED Display Digital Electronic Clock Module 13-11 

IVA1012 LED Display Digital Electronic Clock Module 13-17 

MA1013 LED Display Digital Electronic Clock Module 13-23 

CUSTOM MOS/LSI - SECTION 14 

C-istom MOS at National 14-2 

ORDERING INFORMATION/PHYSICAL DIMENSIONS 

Ordering Information A- 1 

Physical Dimensions A-2 

Definition of Terms A-8 



--- n ™' U ^; un „ dp -- n - n --„/ )r - morf °* ,h V c :v;ing U ' S stents; 3383262, 3189758, 3231797, 3303356, 3317571, 3323071, 3381071, 3408542, 3421025, 3426423, 3440498, 3518750, 3519897, 3557431, 3550765 
.1566218, 3571630, 3575609, 3579059, 3593063, 35S7540, 3607469 3617859, 3631312, 3633052, 3G38131, 3648071, 3651565, 36S3248. 

rJetionaf noes not nss-Tre any r:!i:or'=,:i/ity for jse cd any :ir:wtiy described; no crrcnrt patent licenses ere inpliee: soil Notional reserves trie rrettt, at any time without notice, to change sere crrcuitry. 




Alpha-Numerical Index 



CD4511BC BCD-to-7-Segment Latch/Decoder/Driver 11-4 

CD4511BM BCD-to-7-Segment Latch/Decoder/Driver 11-4 

DS7664 14-Digit Decoder/Driver with Low Battery Indicator 11-9 

DS8664 14-Digit Decoder/Driver with Low Battery Indicator 11-9 

DS8665 14-Digit Decoder/Driver (Hi-Drive) 11-12 

DS8666 14-Digit Decoder/Driver (P.O.S.) 11-15 

DS8692 Printing Calculator Interface Set 11-18 

DS8693 Printing Calculator Interface Set 11-18 

DS8694 Printing Calculator Interface Set 11-18 

DS8867 8-Segment Driver 11-25 

DS8868 12-Digit Decoder/Driver 11-27 

DS8871 Saturating LED Cathode Driver 11-29 

DS8872 Saturating LED Cathode Driver 11-29 

DS8873 Saturating LED Cathode Driver 1 1 29 

DS8874 9-Digit Shift Input LED Driver 11-31 

DS8877 6-Digit LED Driver 11-33 

DS8892 Programmable Hex LED Digit Driver 11-35 

DS8977 Saturating LED Cathode Driver 11-29 

DS75491 MOS-to-LED Quad Segment Driver 1 1 -37 

DS75492 MOS-to-LED Hex Digit Driver 1 1 37 

DS75493 Quad LED Segment Driver 11-40 

LF13300 Integrating A/D Analog Building Block 5-2 

LM1889 TV Video Modulator 4-48 

MA1002 LED Display Digital Electronic Clock Module 13-2 

MA1003 12 Vdc Automotive/Instrument Clock Module 13-8 

MA1010 LED Display Digital Electronic Clock Module 13-11 

MA1012 LED Display Digital Electronic Clock Module 13-17 

MA1013 LED Display Digital Electronic Clock Module 13-23 

MM5303 Universal Fully Asynchronous Receiver/Transmitter . . ■ 6-2 

MM5307 Baud Rate Generator/Programmable Divider 2-2 

MM5309 Digital Clock 1-2 

MM531 1 Digital Clock 1-2 

MM5312 Digital Clock 1-2 

MM5313 Digital Clock 1-2 

MM5314 Digital Clock 1-2 

MM5315 Digital Clock 1-2 

MM5316 Digital Alarm Clock 1-9 

MM5318 TV Digital Clock 4-2 

MM5320 TV Camera Sync Generator 4-6 

MM5321 TV Camera Sync Generator 4-12 

MM5322 Color Bar Generator Chip 4-18 

MM5330 4 1/2-Digit Panel Meter Logic Block 5-23 

MM5369 17-Stage Programmable Oscillator/Divider 2-7 

MM5370 Digital Alarm Clock 1-14 

MM5371 Digital Alarm Clock 1-14 

MM5375XX Series Clocks 1-21 

MM5376XX Series Clocks 1-27 

MM5377 Auto Clock 1-33 

MM5378 Auto Clock 1-38 

MM5379 Auto Clock 1-38 

MM5382 Digital Calendar Clock Radio Circuit 1-43 



MM5383 Digital Calendar Clock Radio Circuit 1.43 

MM5384 LED Display Digital Clock Radio Circuit 1-50 

MM5385 Digital Alarm Clock 1.56 

MM5386 Digital Alarm Clock I.56 

MM5387AA Digital Alarm Clock 1-62 

MM5393 Push Button Telephone Dialer 6-8 

MM5395 TOUCH-TONE® Generator 6 11 

MM5396 Digital Alarm Clock ^55 

MM5397 Digital Alarm Clock i- 56 

MM5402 Digital Alarm Clock -|.g8 

MM5405 Digital Alarm Clock i_68 

MM5554 Frequency Divider 3. 2 

MM5555 Chromatic Frequency Generator 3.4 

MM5556 Chromatic Frequency Generator 3.4 

MM5559 Serial-to-Parallel Converter 3.5 

MM5734 8-Function, Accumulating Memory Calculator 8-2 

MM5737 8-Digit, 4-Function, Floating Decimal Point Calculator 8-8 

MM5740 90-Key Keyboard Encoder 10-2 

MM5745 78-Key Keyboard Encoder 10-10 

MM5746 78-Key Keyboard Encoder 10-10 

MM5758 Scientific Calculator 8-14 

MM5760 Slide Rule Calculator 8-26 

MM5762 Financial Calculator 3.35 

MM5763 Statistical Calculator g.46 

MM5764 Conversion Calculator 8-56 

MM5765 Calculator Programmer 8-66 

MM5766 Calculator Programmer 8-76 

MM5767 Slide Rule Calculator g_80 

MM5777 6-Digit, 4-Function, Floating Decimal Point Calculator 8-84 

MM5780 Educational Toy Calculator 8-90 

MM5781 Controller Oriented Processor System g-3 

MM5782 Controller Oriented Processor System g.3 

MM5785 RAM Interface Chip 9.15 

MM5788 Printer Interface Chip g.21 

MM5791 7-Function, Accumulating Memory Calculator 8-96 

MM5794 7-Function, Accumulating Memory, Vacuum Fluorescent Display Calculator 8-105 

MM5795 7-Function, Accumulating Memory, Vacuum Fluorescent Display Calculator Circuit 8-114 

MM5799 Controller Oriented Processor g_27 

MM5823 Frequency Divider 3-8 

MM5824 Frequency Divider 3.8 

MM5829 LED Watch Circuit 7-2 

MM5832 Chromatic Frequency Generator 3-11 

MM5833 Chromatic Frequency Generator 3-1 1 

MM5837 Digital Noise Source 3-14 

MM5840 TV Channel Number (16 Channels) and Time Display Circuit 4-23 

MM5841 TV Channel Number and Time Readout Circuit 4-28 

MM5860 LED Watch Circuit 7-6 

MM5863 12-Bit Binary A/D Building Block 5-30 

MM5865 Universal Timer 2-10 

MM5871 Rhythm Pattern Generator 3-16 

MM5878 Remote Control Potentiometer 4-57 

MM5879 RC Circuit 7-12 

MM5880 LED Watch Circuit 7-6 

MM5885 Direct Drive LED Watch 7-13 

MM5886 Direct Drive LED Watch 7-13 

MM5889 RC Circuit 7-12 

MM5890 LCD Chronograph Circuit 7-20 

MM5891 MOS Top Octane Frequency Generator 3-ig 

MM5899 RC Circuit 7-12 

MM53100 Programmable TV Timer/Alarm Clock 4-32 

TOUCH-TONE ?) is a Registered Trademark of Bell Telephone 



MM53104* TV Game Clock Generator (NTSC) with reference to MM531 14 TV Game Clock Generator (PAL) 4-50 

MM531 05 Programmable TV Timer/Alarm Clock 4-32 

MM53107 17-Stage Oscillator/Divider 2-20 

MM53108 Digital Alarm Clock 1-62 

MM54C48 BCD-to-7-Segment Decoder 1 1-42 

MM55104 PLL Frequency Synthesizer 6-16 

MM55106 PLL Frequency Synthesizer 6-16 

MM55108 PLL Frequency Synthesizer with Receive/Transmit Mode 6-20 

MM55110 PLL Frequency Synthesizer with Receive/Transmit Mode 6 20 

MM551 14 PLL Frequency Synthesizer 6-16 

MM551 16 PLL Frequency Synthesizer 6-16 

MM57100* TV Game Circuit (NTSC) with reference to MM57105 TV Game Circuit (PAL) 4-37 

MM57103 Scientific Calculator Circuit 8-123 

MM57104 Scientific Calculator Circuit 8-132 

MM57109 Number Processing Unit 9-39 

MM57123 Financial Calculator 8-141 

MM57126 COPS Memory 9-40 

MM57135 Scientific Calculator ROM 8-153 

MM57136 RPN Scientific Calculator Control ROM 8-157 

MM57140 Controller Oriented Processor 9-46 

MM58104 Direct Drive LED Watch 7-27 

MM58106 Digital Clock and TV Display Circuit 4-53 

MM58115 Digitally Tuned, Direct Drive, 6-Function LED Watch 7-32 

MM581 17 LCD Watch Circuit 7-40 

MM581 18 LCD Watch Circuit 7-40 

MM581 19 LCD Watch Circuit 7-40 

MM58120 LCD Watch Circuit 7-40 

MM58127 LCD Watch Circuit 7-47 

MM58128 LCD Watch Circuit 7-47 

MM58129 LCD Watch Circuit 7-47 

MM58130 LCD Watch Circuit 7-47 

MM58601 Two Time Zone LED Watch Circuit 7-6 

MM58801 Two Time Zone LED Watch Circuit 7-6 

MM74C48 BCD-to-7-Segment Decoder 11-42 

MM54C915 7 Segment-to-BCD Converter 11-46 

MM54C922 16-Key Encoder 10-16 

MM54C923 20-Key Encoder 10-16 

MM74C915 7 Segment-to BCD Converter 11-46 

MM74C922 16-Key Encoder 10-16 

MM74C923 20-Key Encoder 10-16 

NSA 1100 Series 0.100 Inch 9-Digit LED Display 12-2 

NSA 1298 0.110 Inch 9-Digit LED Display 12-6 

NSA 5120 1/8 Inch 12-Digit LED Display 12-8 

NSA 5140 1/8 Inch 14-Digit LED Display 12-10 

NSB 5917 0.5 Inch 5-Digit Numeric Display 12-12 

NSB 5921 0.5 Inch 5-Digit Numeric Display 12-12 

NSB 5922 0.5 Inch 5-Digit Numeric Display 12-12 

NSN Series Multi-Digit LED Numeric Series 12-14 




SECTION 1 
CLOCKS 




Clocks 



For additional application information, 
see AN-143 at the end of this section. 



MM5309, MM5311, MM5312, MM5313, 
MM5314, MM5315 digital clocks 

general description 

These digital clocks are monolithic MOS integrated i 

circuits utilizing P-channel low-threshold, enhancement 
mode and ion implanted, depletion mode devices. The 
devices provide all the logic required to build several , 

types of clocks. Two display modes (4 or 6-digits) 
facilitate end-product designs of varied sophistication. ■ 

The circuits interface to LED and gas discharge displays 
with minimal additional components, and require only 
a single power supply. The timekeeping function a 

operates from either a 50 or 60 Hz input, and the dis- 
play format may be either 12 hours (with leading-zero 
blanking) or 24 hours. Outputs consist of multiplexed 
display drives (BCD and 7-segment) and digit enables. 
The devices operate over a power supply range of 11V 
to 19V and do not require a regulated supply. These 
clocks are packaged in dual-in-line packages. 

features 

■ 50 or 60 Hz operation 

■ 12 or 24-hour display format 



Leading-zero blanking (12-hour format) 

7-segment outputs 

Single power supply 

Fast and slow set controls 

Internal multiplex oscillator 

For features of individual clocks, see Table I 



applications 



Desk clocks 
Automobile clocks 
Industrial clocks 
Interval Timers 



TABLE I 



FEATURES 


MM5309 


MM5311 


MM5312 


MM5313 


MM5314 


MM5315 


BCD Outputs 


X 


X 


X 


X 




X 


4,'6-Digit Display Mode 


X 


X 




X 


X 


X 


Hold Count Contro 




X 




X 


X 


X 


1 Hz Output 






X 


X 






Output Enable Control 


X 


X 






X 




Reset 


X 










X 



Connection diagrams (Dual In Line Packages) 



Von— 




28 
— OUTPUT ENABLE 


f bcdb — 




27 

— 4/6DIGITSELECT 


MULTIPLEXED ,— _ 3 
BCD OUTPUTS J SC0 4 — 
(NEGATIVE 1 nrfTf-^ 
TRUE) BC ° 2 

VScrn — 






TIMING 




fa — 
7 


MMS3Q9 


i*H10 


DIGIT 

ENABLE 
OUTPUTS 








iisi 




MULTIPLEXED 

7SEGMENT ■ 

OUTPUTS 


9 

e _1D 




20 

— SID, 

— 50/6 


Hi INPUT 




,11 




— FAST SET 




l«- 




— SLOW SET 


12/24 HOUR SELECT — 




— RESET 


50/60 V>i SELE 


oii 




1 — V SS 







v 


JD — 




28 
— OUTPUT ENABLE 




r 2 
BCDB — 




— 4/6DIGITSELECT 


TIPLEXED 

1 OUTPUTS 

NEGATIVE 

TRUE) 


BC 04 — 
BCD! — 




— MUX 

iSml 

pM,0 


TIMING 




ICOl-^l 








— 
7 

6 


MM5311 


23 

ils, 


DIGIT 

ENABLE 

OUTPUTS 


MULTIPLEXED 

7SEGMENT • 

OUTPUTS 


9 




19 

— 50/60 


Hz INPUT 




11 
f — 




— FAST SET 




9 — 




— SLOW SET 


2/24 HOUR SELECT — 




— HOLD 


50/60 H; 


ELE 


CT — ' 




^v ss 





Order Number MM 5309 N 
See Package 23 



Order Number MM5311N 
See Package 23 



1-2 



absolute maximum ratings 

Voltage at Any Pin 

Operating Temperature 

S-orage Temperature 

Lead Temperature (Soldering, 10 seconds) 



Vss + 0.3to Vss~20V 
-25°Cto+70°C ( 
~65°Cto+150°C 
300°C 



electrical Characteristics Ta within operating range, Vss = 1 1 V to 19V, Vqd = 0V, unless otherwise specified. 



PARAMETER 



Power Supply Voltage 

Power Supply Current 

50/60 Hz Input Frequency 

50/60 Hz Input Voltage 
Logical High Level 
Logical Low Level 

Multiplex Frequency 

A 1 Logic Inputs 
Logical High Level 
Logical Low Level 

BCD and 7-Segment Outputs 
Logical High Level 
Logical Low Level 

Digital Enable Outputs 
Logical High Level 
Logical Low Level 



CONDITIONS 



VSS (VDD = 0V) 

VSS = 14V, (No Output Loads) 



Determined by External R & C 
Driven by External Timebase 
Internal Depletion Device to VgS 



Loaded 2 k-Q to Vqd 



Loaded 100 Q to Vss 



MIN 



dc 

vss-1 

VDD 
0.100 
dc 

vss-1 

VDD 
2.0 



5.0 



TYP 



50 or 60 

VSS 
VDD 
1.0 

VSS 
VDD 



MAX 



19 
10 
60k 

VSS 
V S S- 10 

60 

60 

VSS 
V S S- 10 

20 
0.01 

0.3 
25 



UNITS 



V 
mA 
Hz 

V 
V 

kHz 

kHz 
V 
V 

mA source 
mA source 

mA source 
mA sink 



Connection diagrams (Continued) Dual-ln-Line Packages (Top Views) 



MULTIPLEXED 

BCD OUTPUTS 

(NEGATIVE 

TRUE) 



BCD 4 — 
BCDl 



MULTIPLEXED 

7 SEGMENT 

OUTPUTS 



12/24 HP, SELECT 
50/60 Hi SELECT — 

Orde 

OUTPUT ENABLE - 



MULTIPLEXEO 

7 SEGMENT 

OUTPUTS 



12/24 HP. SELECT 
50/60 H.- SELECT — 



-BCD 8 
L »DD 
-MUX TIMING 



DIGIT 

ENABLE 

OUTPUTS 



— H10 

— I PPS OUTPUT 

16 

— 50/60 Hi INPUT 

— FAST SET 

14 

— SLOW SET 

'S „ 



r Number MM53 
Seei Package 22 



»ss 
12N 



- 4/6 DIGIT SELECT 

I 

-MUX TIMING 



DIGIT 

ENABLE 

OUTPUTS 



17 



- S10 

— 50/60 Hi INPUT 
FAST SET 

— SLOW SET 
iDLD 



er Number MM5314N 
See Package 22 



MULTIPLEXED 

BCD OUTPUTS 

(NEGATIVE 

TRUE! 



BCD 8- 
BC DE- 



MULTIPLEXED 

7 SEGMENT 

OUTPUTS 



12/24 HR SELECT — 
SO/60 Hi SELECT 



-4/6 DIGIT SELECT 
-MUX TIMING 



DIGIT 

ENABLE 

OUTPUTS 



— S10 

1 PPS OUTPUT 
50/60 Hi INPUT 

— FAST SET 
SLOW SET 
HOLD 

— Vss 



Order Number MM5313N 
See Package 23 



MULTIPLEXED 

BCD OUTPUTS 

(NEGATIVE 

TRUE) 



BCD4 

BCD2 

BCD 1 — 



ULTIPLEXED 

JSEGMENr 

OUTPUTS 



12/24 HR SELECT 
SO/60 Hz SELECT — 



28 . 



GIT SELECT 

— MUX TIMING 
1 " 

(£m,0 

DIGIT 

ENABLE 

OUTPUTS 

-S10 

— 50/60 Hz INPUT 
FAST SET 

— SLOW SET 
H0LO 
RESET 
VSS 



Order Number MM5315N 
See Package 23 



1-3 



functional description 



A block diagram of the MM5309 digital clock is shown 
in Figure 1. MM5311, MM5312, MM5313, MM5314 
and MM5315 clocks are bonding options of MM5309 
clock. Table I shows the pin-outs for these clocks. 

50 or 60 Hz Input: This input is applied to a Schmitt 
Trigger shaping circuit which provides approximately 
5V of hysteresis and allows using a filtered sinewave 
input. A simple RC filter such as shown in Figure 10 
should be used to remove possible line voltage transients 
that could either cause the clock to gain time or damage 
the device. The shaper output drives a counter chain 
which performs the timekeeping function. 

50 or 60 Hz Select Input: This input programs the 
prescale counter to divide by either 50 or 60 to obtain a 
1 Hz timebase. The counter is programmed for 60 Hz 
operation by connecting this input to Vrjr). An internal 
depletion device is common to this pin; simply leaving 
this input unconnected programs the clock for 50 Hz 
operation. As shown in Figure 7, the prescale counter 
provides both 1 Hz and 10 Hz signals, which can be 
brought out as bonding options. 

Time Setting Inputs: Both fast and slow setting inputs, 
as well as a hold input, are provided. Internal depletion 
devices provide the normal timekeeping function. 
Switching any of these inputs (one at a time) to Vqd 
results in the desired time setting function. 



which is driven by a multiplex oscillator. The oscillator 
and external timing components set the frequency of 
the multiplexing function and, as controlled by the 4 or 
6-digit select input, the divider determines whether data 
will be output for 4 or 6 digits. A zero-blanking circuit 
suppresses the zero that would otherwise sometimes 
appear in the tens-of-hours display; blanking is effective 
only in the 12-hour format. The multiplexer addresses 
also become the display digit-enable outputs. The multi- 
plexer outputs are applied to a decoder which is used 
to address a programmable (code converting) R OM . 
This ROM generates the final output codes, i.e., BCD 
and 7-segment. The sequential output order is from 
digit 6 (unit seconds) through digit 1 (tens of hours). 

Multiplex Timing Input: The multiplex oscillator is 
shown in Figure 2. Adding an external resistor and 
capacitor to this circuit via the multiplex timing input 
(as shown in Figure 4a) produces a relaxation oscillator. 
The waveform at this input is a quasi-sawtooth that is 
squared by the shaping action of the Schmitt Trigger in 
Figure 2. Figure 3 provides guidelines for selecting the 
external components relative to desired multiplex 
frequency. 

Figure 4 also illustrates two methods of synchronizing 
the multiplex oscillator to an external timebase. The 
external RC timing components may be omitted and 
this input may be driven by an external timebase; the 
required logic levels are the same as 50 or 60 Hz input. 



The three gates in the counter chain (Figure 1} are 
used for setting time. During normal operation, gate A 
connects the shaper output to a prescale counter (+50 
or +60); gates B and C cascade the remaining counters. 
Gate A is used to inhibit the input to the counters for 
the duration of slow, fast or hold time-setting input 
activity. Gate B is used to connect the shaper output 
directly to a seconds counter (+60), the condition for 
slow advance. Likewise, gate C connects the shaper 
output directly to a minutes counter (+60) for fast 
advance. 

Fast set then, advances hours information at one hour 
per second and slow set advances minutes information 
at one minute per second. 

12 or 24-Hour Select Input: This input is used to pro- 
gram the hours counter to divide by either 12 or 24, 
thereby providing the desired display format. The 
12-hour display format is selected by connecting this 
input to Vqq; leaving the input unconnected (internal 
depletion device) selects the 24-hour format. 

Output Multiplexer Operation: The seconds, minutes, 
and hours counters continuously reflect the time of day. 
Outputs from each counter (indicative of both units 
and tens of seconds, minutes, and hours) are time- 
division multiplexed to provide digit-sequential access 
to the time data. Thus, instead of requiring 42 leads to 
interconnect a 6-digit clock and its display (7 segments 
per digit), only 13 output leads are required. The multi- 
plexer is addressed by a multiplex divider decoder, 



Reset: Applying Vrjp to this input resets the counters 
to 0:00:00.00 in 12-hour format and 00:00:00.00 in 
24-hour formats leaving the input unconnected (internal 
depletion pull-up) selects normal operation. 

4 or 6 Digit Select Input: Like the other control inputs, 
this input is provided with an internal depletion pull-up 
device. With no input connection the clock outputs data 
for a 4-digit display. Applying VpD to this input pro- 
vides a 6-digit display. 

Outp ut Enable Input: With this pin unconnected the 
BCD and 7-segment outputs are enabled (via an internal 
depletion pull-up). Switching Vrjrj to this input inhibits 
these outputs. (Not applicable to MM5312, MM5313, 
and MM5315 clocks.) 

Output Circuits: Figure 5a illustrates the circuit used 
for the BCD and 7-segment outputs. Figure 5b shows 
the digit enable output circuit. Figure 6 illustrates 
interfacing these outputs to standard and low power 
TTL. Figures 7 and 8 illustrate methods of interfacing 
these outputs to common anode and common cathode 
LED displays, respectively. A method of interfacing 
these clocks to gas discharge display tubes is shown in 
Figure 9. When driving gas discharge displays which 
enclose more than one digit in a common gas envelope, 
it is necessary to inhibit the segment drive voltage(s) 
during inter-digit transitions. Figure 9 also illustrates a 
method of generating a voltage for application to the 
output enable input to accomplish the required inter- 
digit blanking. 



functional description (Continued) 



SELECT "-"^ 
HOLDO— 



SO/60 Hz . 
INPUT 1 



SLOW SET ID- 



FAST SET O- 
RESETO- 



«DD 



MULTIPLEX 
TIMING 
OUTPUT 



MULTIPLEX 
OSCILLATOR 



SHAPING 
CIRCUIT 



SECONDS 
COUNTER 

I-: 601 



PRESCALE COUNTER 



1Z* 



MINUTES 
COUNTER 



iz 



HOURS 
COUNTER 

(- 12 OR 24} 



ZERO 
BLANKING 



lZ lz 



SECONDS, MINUTES, S HOURS MULTIPLEXER 



z> 



MULTIPLEX 
DIVIOER' 
DECODER 



^ DECDD 



^ 



PROGRAM 
MABLE 
ROM 



S. MULTI 

^/bCTJO 

Km 

=Vo 

>di 
° 



LTIPLEXED 
UTPUTS 



MULTIPLEXED 
SEGMENT 
UTPUTS 



□(GIT ENABLE 
UTPUTS 



FIGURE 1. MM5309 Digital Clock Block Diagram 




50/60 PPS 
OUTPUT OR 

>• MULTIPLEX 
OSCILLATOR 
OUTPUT 



Dotted components added to shaping 
circuit to form multiplex oscillator 



Effectively 
FIGURE 2. 50/60 H;e Shaping Circuit/Multiplex Oscillator 



§fe 


























































xJL- 
















m 


^RC 




S^ 
































■*— r+- 


















ill ^ 














pjjj 


































-Vss ASSHOWN- 
"Vqd^OV 




























R = 2 


20k 










1 







0.0001 0.001 0.01 0.1 

C - CAPACITANCE I/jF) WITH R = 220k 



FIGURE 3. Multiplex Timing Component Selection Guide 



1-5 



functional description (Continued) 



FIGURE 4a. Relaxation Oscillator 



EXTERNAL 
TIME 
BASE 



(INPUT OR OUTPUT) 



<H 



MULTIPLEX 
TIMING INPUT 



VSS 



. . EXTERNAL 

I CLOCK O VW 

1 ' SIGNAL 10k 



MULTIPLEX 
TIMING INPUT 



«SS 



FIGURE 4b. External Time Base 



FIGURE 4c. External Clock 



Note. Free running frequency should be set to run slightly lower than system frequency 
over temperature. External time base may be input or output. 
* R=100k. 

FIGURE 4. Synchronizing or Triggering Multiplex Oscillators 



V S S 

—DM 



"ss 

J 



1— 



SEGMENT BCD OH 1 PPS 
OUTPUT 



«ss 



4>H 




DIGIT ENABLE 
OUTPUT 



FIGURE 5. Output Circuits 



1-6 



functional description (continued) 



MOS to Low Power TTL Interface 

vss 



ANY TTL GATE 

"cc-sv 




For V S s = 5, Vqd = 12, R = 10k 

For V ss = 10 to 17V, V DD = Gnd, R = 3k 



MOS to TTL Interlace 

V™ = 5V 




O 

U Dn .-12V 

For V ss = 5, V DD = -12, R = 7.5k 

Note. Digit select wilt drive TTL directly when 

5, —12 supplies are used. 



22 
22 

(Jl ui 
WW 



w 

2 

2 
w 
w 



(O 



UI 

w 



OTU1 
WW 



FIGURE 6. Interfacing TTL 




2N44D3 

OR EQUIV. (X4 0R X6| 



1 


"^ TYPICAL LED 


1 


SEGMENTS 




(COMMON-ANODE) 




SUCH AS 




NSN71L, OR 




EQUIV. 


;!N3904 




OR EQUIV. (X7) 



-#-? 



TYPICAL 
SEGMENT 
OUTPUT 



Hh^ 



TYPICAL 

DIGIT 

ENABLE 

.OUTPUT 



*2N39(M 
OR EQUIV. (X7) 



'it \ 



TYPICAL LEO 
SEGMENTS 
/' I 1 (COMMON-CATHODE) 
^ ^J SUCH AS NSN74R, 
▼ OR EQUIV. 

II A— 



2NM03 

OR EQUIV. (X4 0RX6) 



v S s- 



M(I F ) 

Where R|_ a!; in kl_l 
And Vp = forward drop of LED 
0.6V ^ voltage drop of transistors 
N = number of digits in display 
lp = required average LED current 



<V SS V DD )/2 V F 1.5V 



^ L = 



N(lp} 

Where R L is in kft 
And V F = forward drop of LED 
0.9V = voltage drop of transistors 
N = number of digits in display 
lp = required average LED current 



^Transistors may be replaced by DM75491, DM75492, 
DM8861 , DM8863 or equivalent segment/digit drivers. 



FIGURE 7. Interfacing Common Anode LED Displays 



FIGURE 8. Interfacing Common Cathode LED Displays 



1-7 



functional description (Continued) 



JL. 



\< TYPICAL 

DIGIT 

ENABLE 

OUTPUT 



TYPICAL 

SEGMENT 

OUTPUT 

MULTIPLEX 

TIMING 

INPUT 



V 0D 
(-15V) - 



DIGIT 

COMMON-ANODE 

TERMINAL 



TYPICAL 
SEGMENT 



SEGMENT 
CATHODE 

TERMINAL 



X 



2N3904J i > 



4 



<X6) 
?70k 



Hh 



-35V- 
-125V- 



F1GURE 9. Interface Panaplex II* Neon Display Tube 



TM of Burroughs Corp. 



t — f 



100k 
AC IN— ^^\~ 



-35V- 
-105V- 



15 27 

V SS 4/6 



01 25 
D2 24 

03 23 

04 22 



SEG 
a b c d e I g 
6 7 8 9 1Q 11 12 



\J 



>- 



H 



INTER-DIGIT BLANKING CIRCUIT 



$ 



< 



2N5086 

(X4) 



TYPICAL 
ANODE 
DRIVER 



ONLY 1M 

T V\Ar- 



* 270k I 

► 1X4) I 



/ o i 



u u 
LhLh 



AM 



?N5Q86 
(X7) 



0.1 P200V 

!X7> 



ne- 



220k S 22k < 47k 

(X7) > (X7| > (X7> 



PM 



TYPICAL 

CATHODE | 

DRIVER I 



' 1N914 
. <X7) 



^ 



1N914 <47k >22k 



FIGURE 10. MM5309 Driving Gas Discharge Display, Typical Applications 




Clocks 



2 
w 



MM5316 digital alarm clock 
general description 

The MM5316 digital alarm clock is a monolithic MOS 
integrated circuit utilizing P-channel low-threshold, 
enhancement mode and ion-implanted depletion mode 
devices. It provides all the logic required to build several 
types of clocks and timers. Four display modes (time, 
seconds, alarm and sleep) are provided to optimize 
circuit utility. The circuit interfaces directly with 7- 
segment fluorescent tubes, and requires only a single 
power supply. The timekeeping function operates 
from either a 50 or 60 Hz input, and the display for- 
mat may be either 12 hours (with leading-zero blank- 
ing and AM/PM indication) or 24 hours. Outputs 
consist of display drives, sleep (e.g., timed radio turn 
off), and alarm enable. Power failure indication is 
provided to inform the user that incorrect time is 
being displayed. Setting the time cancels this indi- 
cation. The device operates over a power supply range 
of 8— 29V and does not require a regulated supply. 
The MM5316 is packaged in a 40-lead dual-in-line 
package. 



features 

■ 50 or 60 Hz operation 

■ Single power supply 

■ Low power dissipation (36 mW at 9V) 

■ 12 or 24-hour display format 



► 12-hour format 



■ AM/PM outputs 

■ Leading-zero blanking) 

■ 24-hour alarm setting 

■ All counters are resettable 

■ Fast and slow set controls 

■ Power failure indication 

■ Blanking/brightness control capability 

■ Elimination of illegal time display at turn on 

■ Direct interface to fluorescent tubes 

* 9-minute snooze alarm 

■ Presettable 59-minute sleep timer 

applications 

■ Alarm clocks 

■ Desk clocks 

■ Clock radios 

■ Automobile clocks 

■ Stopwatches 

■ Industrial clocks 

■ Portable clocks 

* Photography timers 

■ Industrial timers 

■ Appliance timers 

■ Sequential controllers 



block and connection diagrams 



PM | TO ID'S 
OFHRS 
AM I DIGIT 




Dual-ln-Line Package 



AM OUTPUT - 

10HRS -b&c- 

HRS-f- 



HRS - p. 

10 WINS - f 

10MINS g 

0MINS-3& d 

10 MINS -b 

10MJNS-e 

lOMINS-c 

MINS-f 

WINS t| 

MINS - a 

MINS - b 

MINS-c 



-PM0UT 
-1 Hz OUT 

- 12,74 HR SELECT 

- (RANKING IN 

- 50/60 Hz SELECT 

- 60/60 Hz IN 

I 

- fast set in 

- slow set in 
-seconds display in 

- alarm oisplav in 
-sleep display in 
-vdd 

-vss 

-SLEEP0UT 

- ALARM OFF IN 

- ALARM OUT 
-SNOOZE IN 

- OUT COMMON SOURCE 
-MINS-c 



Order Number MM5316N 
See Package 24 



absolute maximum ratings 

Voltage at Any Pin 

Operating Temperature 

Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 



Vss + 0.3 to Vss~30V 

-25°Cto+70°C 

-65° C to +150°C 

300° C 



electrical characteristics 

Ta within operating range, Vgs = 21 V to +29V, Vrjrj = 0V, unless otherwise specified. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Power Supply Voltage 


VSS< V DD : =0V) 


21 




29 


V 


Power Supply Current 


No Output Loads 












V S S = 8V 






4 


mA 




V S S = 29V 






5 


mA 


Counter Operation Voltage 




8 




29 


V 


50/60 Hz Input Frequency Voltage 




dc 


50 or 60 


10k 


Hz 


Logical High Level 




vss-i 


vss 


VSS 


V 


Logical Low Level 




VDD 


VDD 


VDD+1 


V 


Blanking Input Voltage 












Logical High Level 




VSS- 1.5 


VSS 


VSS 


V 


Logical Low Level 




VDD 


VDD 


VsS-4 


V 


All Other Input Voltages 












Logical High Level 




vss-1 


VSS 


VSS 


V 


Logical Low Level 


Internal Depletion Device to Vqq 


VDD 


VDD 


VDD+2 


V 


Power Failure Detect Voltage 


(V$S Voltage) 


10 




20 


V 


Output Currents, 1 Hz Display 


Vss = 21V to 29V, 
Output Common = Vss 










Logical High Level 


VOH = V SS - 2V 


1500 






MA 


Logical Low Level, Leakage 


v OL = V DD 






1 


MA 


10's of Hours (b & c), 10's of Minutes 












(a&d) 












Logical High Level 


VOH = V S S - 2V 


1000 






ma 


Logical Low Level, Leakage 


v OL= VDD 






1 


ma 


All Other Display, Alarm and Sleep Outputs 












Logical High Level 


VOH = V S S ~ 2V 


500 






ma 


Logical Low Level, Leakage 


v OL = V DD 






1 


uA 



functional description 

A block diagram of the MM5316 digital alarm clock is 
shown in Figure 7. The various display modes provided 
by this clock are listed in Table I. The functions of the 
setting controls are listed in Table II. Figure 2 is a 
connection diagram. The following discussions are based 
on Figure 1 . 

50 or 60 Hz Input (pin 35): A shaping circuit /Figure 3) 
is provided to square the 50 or 60 Hz input. This circuit 
allows use of a filtered sinewave input. The circuit is a 
Schmitt Trigger that is designed to provide about 6V of 
hysteresis. A simple RC filter, such as shown in Figure 6, 
should be used to remove possible line-voltage transients 
that could either cause the clock to gain time or damage 
the device. The shaper output drives a counter chain 
which performs the timekeeping function. 

50 or 60 Hz Select Input (pin 36): A programmable 
prescale counter divides the input line frequency by 
either 50 or 60 to obtain a 1 Hz time base. This counter 
is programmed to divide by 60 simply by leaving pin 36 
unconnected; pull-down to Vpo is provided by an 
internal depletion device. Operation at 50 Hz is pro- 
grammed by connecting pin 36 to V$S. 

Display Mode Select Inputs (pins 30-32): In the 

absence of any of these three inputs, the display drivers 
present time-of-day information to the appropriate 
display digits. Internal pull-down depletion devices allow 
use of simple SPST switches to select the display mode. 
If more than one mode is selected, the priorities are as 
noted in Table I. Alternate display modes are selected 
by applying Vss to the appropriate pin. As shown in 
Figure 1 the code converters receive time, seconds, alarm 
and sleep information from appropriate points in the 
clock circuitry. The display mode select inputs control 
the gating of the desired data to the code converter 
inputs and ultimately (via output drivers) to the display 
digits. 

Time Setting Inputs (pins 33 and 34): Both fast and 
slow setting inputs are provided. These inputs are 
applied either singly or in combination to obtain the 
control functions listed in Table II. Again, internal 
pull-down depletion devices are provided; application of 
V SS to these pins effects the control functions. Note 
that the control functions proper are dependent on the 
selected display mode. For example, a hold-time control 
function is obtained by selecting seconds display and 
actuating the slow set input. As another example, the 
clock time may be reset to 12:00:00 AM, in the 12-hour 
format (00:00:00 in the 24-hour format), by selecting 
seconds display and actuating both slow and fast set 
inputs. 

Blanking Control Input (pin 37): Connecting this 
Schmitt Trigger input to S/QD Places all display drivers 
in a non-conducting, high-impedance state, thereby 
inhibiting the display, (see Figures 3 and 4). Conversely, 
Vss applied to this input enables the display. 

Output Common Source Connection (pin 23): All 

display output drivers are open drain devices with all 
sources common to pin 23 (Figure 4). When using 



fluorescent tube displays, Vss or a display brightness 
control voltage is permanently connected to this pin. 
Since the brightness of a fluorescent tube display is 
dependent on the anode (segment) voltage, applying a 
variable voltage to pin 23 results in a display brightness 
control. This control is shown in Figure 6. 

12 or 24-Hour Select Input (pin 38): By leaving this pin 
unconnected, the outputs for the most-significant 
display digit (10's of hours) are programmed to provide 
a 12-hour display format. An internal depletion pull 
down device is again provided. Connecting this pin 
to Vss programs the 24-hour display format. Seg- 
ment connections for 10's of hours in 24-hour mode 
are shown in Figure 5b. 

Power Fail Indication: If the power to the integrated 
circuit drops indicating a momentary ac power failure 
and possible loss of clock, the power fail latch is set. 
The power failure indication consists of a flashing of the 
AM or PM indicator at a 1 Hz rate. A fast or slow set 
input resets an internal power failure latch and returns 
the display to normal. In the 24-hour format, the power 
failure indication consists of flashing segments "c" and 
"f" for times less than 10 hours, and of a flashing 
segment "c" for times equal to or greater than 10 hours 
but less than 20 hours; and a flashing segment "g" for 
times equal to or greater than 20 hours. 

Alarm Operation and Output (pin 25): The alarm 
comparator (Figure 1) senses coincidence between the 
alarm counters (the alarm setting) and the time counters 
(real time). The comparator output is used to set a latch 
in the alarm and sleep circuits. The latch output enables 
the alarm output driver (Figure 4), the MM5316 output 
that is used to control the external alarm sound gener- 
ator. The alarm latch remains set for 59 minutes, during 
which the alarm will therefore sound if the latch output 
is not temporarily inhibited by another latch set by the 
snooze alarm input (pin 24) or reset by the alarm "OFF" 
input (pin 26). If power fail occurs and power comes 
back up, the alarm output will be in high impedance 
state. 

Snooze Alarm Input (pin 24): Momentarily connecting 
pin 24 to Vss inhibits the alarm output for between 8 
and 9 minutes, after which the alarm will again be 
sounded. This input is pulled-down to Vqd by an 
internal depletion device. The snooze alarm feature may 
be repeatedly used during the 59 minutes in which the 
alarm latch remains set. 

Alarm "OFF" Input (pin 26): Momentarily connecting 
pin 26 to VgS resets the alarm latch and thereby silences 
the alarm. This input is also returned to Vprj by an 
internal depletion device. The momentary alarm "OFF" 
input also readies the alarm latch for the next compara- 
tor output, and the alarm will automatically sound again 
in 24 hours (or at a new alarm setting). If it is desired 
to silence the alarm for a day or more, the alarm "OFF" 
input should remain at VsS- 

Sleep Timer and Output (pin 27): The sleep output 
at pin 27 can be used to turn off a radio after a 



1-11 



(0 
CO 

2 



functional description (continued) 

desired time interval of up to 59 minutes. The time 
interval is chosen by selecting the sleep display mode 
(Table I) and setting the desired time interval (Table II). 
This automatically results in a current-source output 
via pin 27, which can be used to turn on a radio 
(or other appliance). When the sleep counter, which 
counts downwards, reaches 00 minutes, a latch is reset 



and the sleep output current drive is removed, thereby 
turning off the radio. The turn off may also be 
manually controlled (at any time in the countdown) by 
a momentary Vgs connection to the snooze input 
(pin 24). The output circuitry is the same as the other 
outputs (Figure 4). 




'Effectively 



FIGURE 3. 50/60 Hz or Blanking Input Shaping Circuit 



♦OUTPUT COMMON SOURCE BUS (PIN 23) 



O(DATA)- 



vss 



BLANKING 

(FROM II O— — ►OUTPUT 

SHAPER) I | (OPEN DRAIN) 



O ► ou 



Alarm and sleep output sources are connected to Vgs : 
blanking is not applied to these outputs. 

FIGURE 4. Output Circuit 



PIN 39 PIN1 
1 Hz AM 



PIN 40 PIN1 
PM AM NC 




PIN 40 PIN 2 
PM b&c 



< b 
9 



e c 
d 



TT 



(a) 12-Hour Display Format (bl 24-Hour Display Format 

FIGURE 5. Wiring Ten's-of-Hours Digit 



1-12 



functional description (Continued) 



TABLE I. MM5316 Display Modes 



2 
01 

CO 

0) 



"SELECTED 
DISPLAY MODE 


DIGIT NO. 1 


DIGIT NO. 2 


DIGIT NO. 3 


DIGIT NO. 4 


Time Display 


10's of Hours & AM/PM 


Hours 


10's of Minutes 


Minutes 


Seconds Display 


Blanked 


Minutes 


10's of Seconds 


Seconds 


Alarm Display 


10's of Hours & AM/PM 


Hours 


10's of Minutes 


Minutes 


Sleep Display 


Blanked 


Blanked 


10's of Minutes 


Minutes 



If more than one display mode input is applied, the display priorities are in the order of Sleep (overrides all others) Alarm 
Seconds, Time (no other mode selected). 



TABLE II. MM5316 Setting Control Functions 



SELECTED 


CONTROL 


DISPLAY MODE 


INPUT 


*Time 


Slow 




Fast 




Both 


Alarm 


Slow 




Fast 




Both 




Both 


Seconds 


Slow 




Fast 




Both 




Both 


Sleep 


Slow 




Fast 




Both 



CONTROL FUNCTION 



Minutes Advance at 2 Hz Rate 
Minutes Advance at 60 Hz Rate 
Minutes Advance at 60 Hz Rate 

Alarm Minutes Advance at 2 Hz Rate 
Alarm Minutes Advance at 60 Hz Rate 
Alarm Resets to 12:00 AM (12-hour format) 
Alarm Resets to 00:00 (24-hour format) 

Input to Entire Time Counter is Inhibited (Hold) 
Seconds and 10's of Seconds Reset to Zero Without 

a Carry to Minutes 
Time Resets to 12:00:00 AM (12-hour format) 
Time Resets to 00:00.00 (24-hour format) 

Substracts Count at 2 Hz 
Substracts Count at 60 Hz 
Substracts Count at 60 Hz 



When setting time sleep minutes will decrement at rate of time counter, until the sleep counter reaches 00 minutes 
(sleep counter will not recycle). 



typical application 

Figure 6 is a schematic diagram of a general purpose alarm clock using the MM5316and a fluorescent tube display. 




FIGURE 6. Schematic 




MM5370, MM5371 digital alarm clocks 



Clocks 



general description 



The MM5370 and MM5371 digital alarm clocks are 
monolithic MOS integrated circuits utilizing P-channel 
low-threshold, enhancement mode and ion-implanted 
depletion mode devices. They provide all the logic 
required to build several types of clocks and timers. 
Three display modes (time, alarm and sleep) are pro- 
vided to optimize circuit utility. The circuits interface 
simply with 7-segment gas discharge displays. The 
timekeeping function operates from either a 60 Hz 
(MM5370) or 50 Hz (MM5371) input, and the display 
format may be either 12 hours (with leading-zero 
blanking and AM/PM indication) or 24 hours. Outputs 
consist of display drives, alarm enable and sleep (e.g., 
timed radio turn off). Power failure indication is 
provided to inform the user that incorrect time is being 
displayed. Setting the time cancels this indication. 
These clocks are packaged in 28-pin dual-in-line packages. 



AM/PM drive output in 12-hour format 

Leading-zero blanking in 12-hour format 

24-hour alarm setting 

All counters are resettable 

Fast and slow set controls 

Power fail indication 

Blinking colon — 12-hour or 24-hour mode 
Blinking AM/PM indicators-12-hour only 

Brightness control capability 

Simple interface to gas discharge display 

Presettable 59-minute sleep timer 

9-minute snooze timer 



applications 



features 

■ Single power supply 

■ Low power dissipation 

■ 12 or 24-hour display format 

■ Colon drive output 



Alarm clocks 
Desk clocks 
Clock/radios 
Automobile clocks 
Industrial clocks 
Appliance timers 



connection diagram 



Order Number MM5370N 
or MM5371N 
See Package 23 



Duat-ln-Line Package 



SNOOZE I 

INPUT 




— HOURS 




ALARM z 
OUTPUT 




— 10 HOURS 


DIGIT 


ALARM 3 
Of F INPUT 




— 10 MINUTES 


OUTPU 


SLEEP 4 
OUTPUT 




— MINUTES . 




5 

vss — 




«.*' 




6 




23 




V D0 








SLEEP 7 
DISPLAY 


MM5370 


iLi 


MULTIPLEXED 


ALARM 8 
DISPLAY 


MM537I 


21 

_— a 


. 7-SEGMENT 
OUTPUTS 


9 
RESET 




£lb 




SLOW ,0 
SET 




19 




FAST " 
SET 




18 




LINE '2 
FREQUENCY INPUT 




17 COLON 
OUTPUT 


12/24-HUUR 13 
SELECT 




16 AM/PM 
OUTPUT 


MULTIPLEX 14 
TIMING INPUT 




' 5 BRIC 

CON 


HTNESS 
TROL m 


PUT 



1-14 



absolute maximum ratings 

Voltage at Any Pin 

Voltage at Any Display Output Pin 

Operating Temperature 

Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 



V SS + 0.3V to Vss - 29V 

Vss + 0.3Vto VsS~55V 

-25°C to +70°C 

-65°Cto+150°C 

300°C 



electrical Characteristics Ta within operating range, Vss = ov , Vqd = -21V to -29V unless otherwise specified. 



PARAMETER 



Power Supply Voltage 
Functioning Clock 
Outputs Driving Display 

F'ower Supply Current 

60 Hz (or 50 Hz) Input Frequency 
MM5370 
MM5371 

60 Hz (or 50 Hz) Input Voltage 
Logical High Level 
Logical Low Level 

Brightness Control Voltage 
Logical High Level 
Logical Low Level 

All Other Input Voltages 
Logical High Level 
Logical Low Level 

Multiplex Frequency 

Power Failure Detect Voltage 

Output Currents 

Digit Anode Outputs 

Logica High Level, ("ON") 
Logical Low Level, ("OFF") 

Segment Cathode Outouts 
Logical High Level, ("OFF") 
Logical Low Level, ("ON") 

Alarm and Sleep Outpjts 
Logical High Level, ("ON") 
Logical Low Level, ("OFF") 



CONDITIONS 



No Output Loads 

No Output Loads, (See "Power 
Supply" Section) 



Internal Depletion Load to Vrjo 

Determined by Ext. RC 
Driven by Ext. Time Base 

(Vdd Voltage) 

Vqd = -21 V to -29V, Vss = 0V 

VOH = V SS - 5V 
VOL = V S S-45V 

VOH = V S S - 5V 

vol = v ss -45v 

VOH = V S S - 2V 
v OL = V DD + 2V 



functional description 

A block diagram of the MM5370 and MM5371 clocks is 
shown in Figure 1 . The various display modes provided 
by these clocks are listed in Table I. The functions of the 
controls are listed in Table II. A connection diagram for 
these devices is shown on page 1 . Unless indicated other- 
wise, the following discussions are based on Figure 1. 

Power Supply: Even though these clocks do not require 
a regulated supply, and operate over a wide voltage 
range, certain factors should be remembered. Power 
supply voltages between -8V and -21V will provide all 



MIN 



-8.0 
-21 



dc 
dc 

Vss -i.o 
vdd 

Vss-2.0 

vdd 

Vss- 1-0 
vdd 

500 

dc 

-3.0 



TYP 



8.0 



2.0 



1.5 
-10 



-25 



VSS 

vdd 

vss 
vdd 

Vss 
vdd 



MAX 



-29 

-29 

5.0 



30k 
30k 



VSS 
VDD+1 

VSS 
Vss-4.0 

VSS 
VDD+2.0 

60k 
60k 

-8.0 



40 



10 



UNITS 



V 
V 

mA 



Hz 
Hz 

V 
V 

V 
V 

V 
V 

Hz 
Hz 

V 



mA 

,uA 

mA 
HA 

mA 
KA 



functions of the clocks (proper counting, etc.) except 
output drive capabilities. In order to ensure proper 
output levels and breakdown voltages it is necessary to 
provide supply voltages between —21V and —29V. At 
some point between — 7V and — 3V, the power fail 
latch becomes "set". All counters will then hold their 
count at least 0.5V below this point. This ensures power 
failure indication before any count is lost. For proper 
power failure indication, power supply rise time should 
not exceed 10 V/ms, since faster rise times may be 
faster than propagation delays within the latch circuitry. 



1-15 



functional description (Continued) 



Line Frequency Input (pin 12): A shaping circuit is 
provided to square the 60 Hz (MM5370) or 50 Hz 
(MM5371) input. This circuit allows use of a sinewave 
input. The Schmitt Trigger shaper (Figure 21 is designed 
to provide approximately 6V of hysteresis. A simple RC 
filter, such as shown in Figure 8, should be used to 
remove possible line-voltage transients that could cause 
the clock to gain time or damage the device. The shaper 
output drives a counter chain which performs the time- 
keeping function. A prescale counter divides the line 
input frequency to obtain a 1 pps timebase. 

Display Mode Select Inputs (pins 7 and 8): In the 

absence of either of these inputs, the display drivers 
output time-of-day information to the display. Internal 
pull-down (to Vqd) depletion loads allow use of simple 
SPST switches for connecting these inputs to Vss* 
thereby selecting alternate display modes. If more than 
one mode is simultaneously selected, the priorities are 
are noted in Table I. As shown in Figure 1 the multi- 
plexed code converter receives time, alarm and sleep 
information from appropriate points in the clock 
circuitry. The display mode select inputs control the 
gating of the desired data to the multiplexed code 
converter inputs and ultimately (via output drivers) 
to the display. 

Time Setting Inputs (pins 10 and 11): Both fast and 
slow setting inputs are provided. These inputs are 
applied either singly or in combination to obtain the 
control functions listed in Table II. Again, internal 
pull-down depletion loads are provided; application of 
VSS f° these Pins effects the control functions. Note 
that the control functions proper are determined by the 
selected display mode. An optional hold-time control 
function can be obtained as shown in Figure 8. 

Reset Input (pin 9): Applying Vss to this input results 
in resetting the timekeeping function of the clock; 
a pull-down depletion load is provided at this input. 
Time is reset to 12:00 AM in the 12-hour format, 
or 00:00 in the 24-hour format. See Table II. 

12 or 24-Hour Select Input (pin 13): By leaving this 
pin unconnected, the clock is programmed to provide 
a 12-hour display format. This format provides for 
zero-blanking the most significant display digit (ten's of 
hours). An internal pull-down depletion load is again 
provided; connecting this pin to V$S programs the 
24-hour display format. (See Figure 8). 

Output Multiplexer Operation: Depending upon the 
selected display mode (see Table I), outputs from the 
appropriate internal counter are time division multi- 
plexed to provide digit-sequential access to the data. 
Thus, instead of requiring 28 leads to interconnect a 
4-digit clock and its display (7-segments per digit), 
only 11 output leads are required. Note that the 
MM5370 and MM5371 actually provide 13 outputs 
(4-digit anode drive outputs plus 9 "segment" cathode 
drive outputs). The two additional "segment" drives 
are provided to accommodate displays which feature a 
colon and/or AM/PM indication. (See sections on 
pin 16 and pin 17). The multiplexed code converter and 
output drivers are controlled by a multiplex oscillator. 
The oscillator and external timing components set the 



frequency of the multiplexing function. Each digit 
anode is sequentially enabled for a time equal to the 
period of one cycle of the multiplex oscillator frequency. 

When driving gas discharge displays which enclose more 
than one digit in a common gas envelope, it is necessary 
to either (1) inhibit the segment drive voltage(s) for a 
short time during inter-digit transitions, or (2) avoid 
physically adjacent inter-digit transitions. The MM5370 
and MM5371 clocks utilize an interlaced output sequence 
to eliminate the need for inter-digit blanking circuitry 
and to prevent display arcing problems. The digit 
sequence is: (1) digit no. 1 (ten's of hours), (2) digit 
no. 3 (ten's of minutes), (3) blank for one digit time, 
(4) digit no. 2 (unit hours), (5) digit no. 4 (unit min- 
utes), (6) blank for one digit time, etc. The two blanking 
intervals are provided to recharge level-translating 
capacitors located in the display segment drive lines 
(see Figure 8). Both segment data and digit enables are 
blanked. Figure 3 is a timing diagram which illustrates 
output timing. 

Multiplex Timing Input (pin 14): The multiplex oscil- 
lator is shown in Figure 4. Adding an external resistor 
and capacitor to this circuit via the multiplex timing 
input produces a relaxation oscillator. The waveform at 
this input is a quasi-sawtooth that is squared by the 
shaping action of the Schmitt Trigger in Figure 4. Figure 
5 provides guidelines for selecting the external com- 
ponents relative to the desired multiplex frequency. 
Figure 6 illustrates a method of synchronizing or driving 
the multiplex oscillator with an external timebase. The 
external RC timing components may be omitted and 
this input driven by an external timebase; the required 
logic levels are the same as the 60 Hz or 50 Hz input. 

Output Circuits: All display output drivers are open- 
drain devices with sources common to Vss (P' n 5), 
see Figure 7. Figure 8 illustrates interfacing the clock 
outputs and a gas discharge display. 

Brightness Control Input (pin 15): Since display bright- 
ness is a function of cathode segment current, a capa- 
bility of interrupting this current for a variable per- 
centage of the digit interval results in a brightness 
control. Connecting this Schmitt Trigger input (see 
Figure 2) to VpD places all cathode segment drive 
voltages at the high level, thereby inhibiting the display. 
Conversely, V55 applied to this input enables the 
cathode segment drives. The Schmitt Trigger shaper 
provides approximately 1V of hysteresis, which facili- 
tates using a waveform such as a sawtooth with a variable 
slope (or variable dc component) to effect the shaper 
output duty cycle and, therefore, the display brightness. 
The control waveform should be derived from the multi- 
plex frequency; a circuit is included in Figure 8. 

Alarm Operation and Output (pin 2): An alarm com- 
parator (see Figure 1) senses coincidence between the 
alarm counters (the alarm setting) and the time counters 
(real time). The comparator output is used to set a latch 
in the alarm and sleep circuits. This latch enables the 
alarm output driver (see Figure 7), the output of which 
is used to control the external alarm sound generator. 
The alarm latch remains set for 59 minutes, during 
which the alarm will sound if the latch output is not 



1-16 



functional description (Continued) 

temporarily inhibited by another latch set by the snooze 
input (pin 1) or reset by the alarm "OFF" input (pin 3). 
Alarm time setting and resetting are outlined in Table II. 
When initially powered, alarm is in "OFF" state. 



Alarm "OFF" Input (pin 3): Momentarily connecting 
this pin to Vss resets the alarm latch and thereby 
silences the alarm. This input is also returned to Vqd 
by an internal depletion load. The momentary alarm 
"OFF" input also readies the alarm latch for the next 
alarm comparator output; the alarm will sound again in 
24 hours (or at a new alarm settingl. If it is desired to 
silence the alarm for a day or more, the alarm input 
should remain at Vss. 

Snooze Timer Input (pin 1): Momentarily connecting 
this pin to Vss inhibits the alarm output for between 
8 and 9 minutes, after which the alarm will again be 
sounded. This input is pulled to Vqq by an internal 
depletion load. The snooze feature may be repeatedly 
used during the 59 minutes in which the alarm latch 
remains set. 



Sleep Timer and Output (pin 4): The sleep output at 
pin 4 can be used to turn off a radio (or other 
appliance) after a desired time interval of up to 59 
minutes. The time interval is chosen by selecting the 



sleep display mode (see Table I) and setting the desired 
time interval (see Table II). This automatically results 
in a current-source output via pin 4 which can be used 
to turn on a radio. When the sleep counter, which 
counts downwards, reaches 00 minutes a latch is reset 
and the sleep output drive current is removed, thereby 
turning off the radio. This turn off also may be manually 
controlled (at any time in the count-down) by a momen- 
tary Vss connection to the snooze input (pin 1). This 
input is also returned to Vrjo by a depletion load. The 
output circuitry is the same as the alarm output (see 
Figure 7). 

AM/PM Cathode Output (pin 16): Current with this 
writing, gas-discharge clock displays are available with 
two types of AM/PM indications, (1) AM and PM 
indicators common to digits 3 and 4 respectively; and 
(2) a PM only indication common to digit 1. Figure 3 
illustrates an AM/PM cathode drive output that is com- 
patible with both display types. Note that this same 
output also provides a non-blinking (steady) colon drive 
common to digit two. Power failure is shown by turning 
off this output at a 1 Hz rate. 

Colon Cathode Output (pin 17): As an optional indica- 
tion of clock operation, some users may prefer to 
display a 1 Hz activity. As shown in Figure 3, a cathode 
drive output is provided to facilitate a blinking colon. 



1 
W 

vl 
o 



1 

Ul 

w 




AM/PM 
COLO 



M I AUXILIARY 

> CATHODE DRIVE 
N J OUTPUTS 



MULTIPLEXED 
7SEGMENT 
CATHODE ORIVE 
OUTPUTS 



FIGURE 1. MM5370and MM5371 Digital Alarm Clock, Block Diagram 



CO 

in 

5 



functional description (Continued) 



O 

CO 

in 

1 



TABLE I. MM5370 and MM5371 Display Modes 



•SELECTED 
DISPLAY MODE 



Time 

Alarm 

Sleep 



DIGIT NO. 1 



10's of Hours 
10's of Hours 
Blanked** 



DIGIT NO. 2 



Unit Hours 
Unit Hours 
Blanked 



DIGIT NO. 3 



10's of Minutes 
10's of Minutes 
10's of Minutes 



DIGIT NO. 4 



Unit Minutes 
Unit Minutes 
Unit Minutes 



*lf more than one display mode input is applied, the display priorities are in the order of Sleep (overrides all others), Alarm, 

Seconds, Time (no other mode selected). 
*F segment is lit in 12-hour display mode. This may be eliminated by using circuit shown in Figure 9. 



Table II. MM5370 and MM5371 Setting Control Functions 



SELECTED 
DISPLAY MODE 



Time* 



Alarm 



Sleep 



CONTROL 
INPUT 



Slow 

Fast 

Both 

Reset 

Reset 

Slow 
Fast 
Both 
Both 

Slow 
Fast 
Both 



CONTROL FUNCTION 



Minutes Advance at 2 Hz Rate 

Minutes Advance at 60 Hz Rate 

Minutes Advance at 60 Hz Rate 

Time Resets to 12:00 AM (12-hour format) 

Time Resets to 00:00 (24-hour format) 

Alarm Minutes Advance at 2 Hz Rate 
Alarm Minutes Advance at 60 Hz Rate 
Alarm Resets to 12:00 AM (12-hour format) 
Alarm Resets to 00:00 (24-hour format) 

Subtracts Count at 2 Hz Rate 
Subtracts Count at 60 Hz Rate 
Subtracts Count at 60 Hz Rate 



*When setting time sleep minutes will decrement at rate of time counter, until the sleep counter reaches 
00 minutes (sleep counter will not recycle). 



LINE 
FREQUENCY 

INPUT OR _ 
BRIGHTNESS U " 
CONTROL 
INPUT 




SHAPED LINE 
FREQUENCY 
OR BRIGHTNESS 
CONTROL SIGIML 



FIGURE 2. 60 Hz lor 50 Hzl Input (or Brightness Control Input) Shaping Circuit 



functional description (Continued) 



MULTIPLEX 
TIMING 
INPUT 



DIGIT NO. 1 
10'SDF HOURS 



J J 



1 I 



1 

r 



COLON | PM 
I 



r 



{ COLON 
1 _ 



MULTIPLEX 
Vss TIMING INPUT 



FIGURE 3. Output Timing Diagram 



EXTERNAL 

TIMING 

COMPONENTS 




FIGURE 4. Multiplex Oscillator Circuit 



< + 



EXTERNAL | 



I" 



















££fc 




-Lj* 


! 






1 


= rp 




i,l'w ' "onw ' ' 1 












P 


;v D0 --2ivs 














]| [_ 










~lp 


I =S = 














ilili i 




1-™ 




iFt 






] V 0D « 










J H 




P = = 


















, 


II ■ III 






1 








1 


1 1 J II 




ll 


ml i illll 





10 pF 100 pF 1000 pF 0.01 ^F 01«F 
CAPACITANCE C (WITH R=100k) 



FIGURE 5. Multiplex Timing Component 
Selection Guide (Typical Only) 



Note 1: For synchronizing, free running period 
should be set to run slightly longer than exter- 
nal timebase over temperature. 
Note 2: For driving, timing capacitor should 
be deleted. 



FIGURE 6. Synchronizing or Driving Multiplex Oscillator 



1-19 



functional description (Continued) 



« 



W 




(OPEN DRAIN) 



TYPICAL DIGIT 
OR SEGMENT 
OUTPUT 



FIGURE 7. Output Circuits 



CONTROLS TO 
ALARM AND/OR 
RADIO CIRCUITS 




FIGURE 8. Recommended Application 



1 20 




Clocks 



MM5375XX series clocks 



general description 

MM5375XX series clock is a monolithic MOS integrated 
circuit utilizing P-channel low threshold enhancement- 
mode and ion-implanted depletion-mode devices. It 
provides all the logic required to give a 4 or 6-digit 
12-hour or 24-hour display from a 50 or 60 Hz input. 
An auxiliary counter allows various options. Available 
options have been listed under features. Power failure 
indication is provided to inform the user that incorrect 
time is being displayed. Setting time cancels this indica- 
tion. MM5375XX is available in a 24-lead dual-in-line 
epoxy package. 

features 

■ Single power supply 

■ Low power dissipation 

■ All counters resettable 

■ Fast and slow set controls 

■ Power failure indication 



2 
£ 

(71 
W 
*J 
(J1 

X 
X 

c/> 

5' 



■ Brightness control capability 

■ No illegal time display at turn-on 

■ Simple interface to gas discharge displays and LED's 

■ Internal digit multiplex oscillator 

■ Leading zero blanking 

■ Activity indicator 

■ 4 to 6-digit operation 

■ Available options^ 

application 

■ Alarm clocks 

■ Desk clocks 

■ Automobile clocks 

■ Industrial clocks 

■ Date clocks 

■ Minute timer clocks 
" Seconds timer clocks 



connection diagram 



Duai-ln-Line Package 



available options table 1 





i 

" 1 MIN — 

I 
10 MIN — 

3 
1 HR — 




21 
23 

n_ 


10 SEC 


DIGIT 
OUTPUTS 


























FEATURE 


FUNCTION 


OPTION NAME 




AA 


AB 


AC 


AD 


AE 


AG 


AH 


Al 




DIGIT 
OUTPUTS 


8THSEG OUT 


Input Frequency 
Time Display 


60 H; 
50 Hz 
12-Hour 






• 


• 
• 


• 




• 


• 






4 
.10HRS 




l\ 


BRIGHTNESS CON 


Auxiliary Counter 


24-Hour 
Alarm Counter 






• 




• 










5 




20 


MUX DSC 




Date Counter 
Minute Timer 
Second Timer 






* 


• 


• 




• 






AUX COUNTER DlS 






B 




Alarm Signal 


DC Level 






N/A 
N/A 


N/A 
N/A 


N/A 

N/A 




N/A 
N/A 






ALARM "OFF" 






C 




Alarm Output 


Modulated at 2 Hz 
Not Modulated 






N/A 
N/A 


N/A 
N/A 


N/A 

N/A 




N/A 

N/A 






ALARM OUTPUT 




1/ 


A 




A.arm at Power Failure 


"ON" 
"OFF" 






N/A 

N/A 


N/A 
N/A 


N/A 
N/A 




N/A 
N/A 






SLOW SET 




lb 


D 


SEGMENT 
OUTPUTS 


Segment Output Polarity 


V SS for Display 
Vqp for Display 






• 


• 


• 




• 






FAST SET — 




IS 


E 




AM or PM Indication 


"OFF" During Time Display 
Displayed at All Times 






N/A 
N/A 


• 


N/A 

N/A 




• 


N/A 
N/A 


N/A 
N/A 


60 Hz INPUT 




14 
13 


F 
G 




8th Segment Blanked 
During Alarm Display 


No 


• 




N/A 


N/A 
N/A 


N/A 
N/A 




N/A 
N/A 


• 


• 


v ss 1L 


Tone is 1/6 multif 


)lex frequency 





















Order Number MM5375XXN 
See Package 22 



1-21 



absolute maximum ratings 

Voltage at Any Pin 

Voltage at Any Display Output Pin 

Operating Temperature 

Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 

electrical characteristics 

Ta within operating range, Vss = 0V, Vqd 



VSS + 0-3V to VsS~30V 

VSS + 0-3V to Vss ~ 55V 

-25°C to +70°C 

-65°Cto+150°C 

300° C 



= -21 V to ~29V unless otherwise specified. 



PARAMETER 



Power Supply Voltage (Vdd> 

Power Supply Current 

60 Hz Input 
Frequency 
Logical High 
Logical Low 

Brightness Control Range 
% of Digit Time 

Multiplex Oscillator Frequency Input 

All Other Input Voltages 
Logical High Level 
Logical Low Level 

Power Failure Detect Voltage 

Output Current 

Digit Select Outputs 
Logical High, Source 
Logical Low, Leakage 

Segment Outputs 

Logical High, Source 
Logical Low, Leakage 

Alarm Output 

Logical High, Source 
Logical Low, Sink 



CONDITIONS 



Excluding Outputs 
Outputs Driving Displays 

Excluding Outputs 



Determined by External R and C, 
(Figure 2) 

Determined by External R and C, 
(Figure 2) 



(VqD Voltage) 

V D D = ~21V to -29V 

V S S = ov 

VQH = VsS"5V 

vol = v S s -45v 

VOH = V S S-5V 

vol = vss -45V 

VOH = Vss-2V 
VQL = VDD + 2V 



MIN 



-8.0 
-21 



DC 

vss-1-o 

V D D 


DC 



vss-i.o 

VDD 
-1.0 



8.0 



2.0 



1.5 

1 



TYP 



50/60 
VSS 
VDD 



VSS 
VDD 



MAX 



-29 
-29 



30k 

VSS 
V D D+'I.O 

95 
30 



VSS 
VDD+2.0 

-8.0 



40 



10 



UNITS 



V 
V 

mA 



Hz 
V 
V 



kHz 



V 
V 



mA 
uA 

mA 
uA 

mA 
uA 



functional description 

A block diagram of the MM5375XX series of clocks 
is shown in Figure 1. The display modes are listed in 
Table I. The functions of the setting controls are listed 
in Table II. The following discussions are based on 
Figure 1. 

60 Hz Input (Pin 11): A shaping circuit is provided to 
square the 60 Hz input (50 Hz optional). This circuit 
allows use of a filtered sinewave input. The circuit is a 
Schmitt trigger that is designed to provide about 3V of 
hysteresis. The shaper output drives a counter chain 
which performs the timekeeping function. 

Time Setting Inputs (Pins 9 and 10): The time setting 
control functions are affected by the application of VsS 
to these 2 pins, which are internally pulled to the power 



supply. Activating Fast Set (pin 10) causes the minutes 
counter to advance at a 60 Hz rate, thus clocking the 
hours counter at a rate of 1 hour per second. Slow Set 
(pin 9) advances the minutes counter at a rate of 2 min- 
utes per second. Activating either Fast Set or Slow Set 
resets the seconds counter to zero. When Fast Set and 
Slow Set are activated simultaneously, all counters are 
reset to 12:00 p.m. and remain in that count until Slow 
Set is deactivated. The 2 time setting inputs affect only 
the counters that are displayed (either the timekeeping 
counters or the alarm counters). 



8-Segment Test (Pin 24): For testing purposes, all 
8-segment output lines may be activated by connecting 
pin 24 (S10 digit output) to Vss- 



1-22 



functional description (Continued) 

Brightness Control (Pin 21): In LED applications, 
brightness of the Display may be varied by use of an 
external time constant. This time constant is used in the 
integrated circuit to control the pulse width or duty 
cycle of the 6-digit enable outputs, (Figure 2). In gas 
discharge applications, connect as shown in Figure 3. 

Activity Indication (Pin 23): When all 6 digits are being 
used, it is not necessary to blink the colon to indicate 
operation of the clock, because the seconds digits pro- 
vide this information. When only 4 digits are in use, the 
S1 digit (pin 23) may be connected to Vgg. In this case, 
the colon flashes at a 1 Hz rate. 

Multiplex Frequency (Pin 20): Applying an external 
time constant to this pin allows the multiplex frequency 
to be adjusted, (Figure 2). 

Power Failure Indication: If the power to the integrated 
circuit drops, indicating a momentary ac power failure 
and possible loss of clock, the AM or PM and colon indi- 
cator will flash at a 2 Hz rate. If power drops completely, 
the clock will reset itself (on resumption of power) to a 
legal state, and the AM or PM and colon indicators will 
flash at a 2 Hz rate. In addition to the flashing AM or 
PM and colon indicator, if a power failure occurs when 
alarm "OFF" (pin 7) is at Vqd (logical "0"), the alarm 
output will be activated (non-activated optional). A 
logical "1" (Vss) on pin 7 will deactivate the alarm 
signal. 

8-Segment Outputs (Pins 13-19 and 22): These outputs 
contain multiplexed information for the display of 
7-segment numerical readouts. The 8th segment is for 
the activation of AM/PM and colon(s) as included in the 
gas discharge displays for which these outputs are 
designed. 

4-Digit Operation: Connect pin 23 to Vgg. 

Digit Enable Outputs (Pin 1-4, 23 and 24): These 
outputs are used to select the 6 digits and are syn- 
chronized with the segment outputs. If pin 23 is 
grounded, segment outputs will be blanked during the 
scanning of the seconds digits. 

Auxiliary Counter: Alarm Counter Option: In this 
option, the auxiliary counter is programmed and used as 
an alarm counter. Pin 6 serves as both alarm display and 
snooze input pin. Ala-m counter is displayed when pin 6 
is held at VgS- Alarm setting (Table II) is done using 
alarm display. Fast Set (pin 10) and Slow Set (pin 9). 
If the alarm "OFF" input (pin 7) is open and whenever 



the real time matches with the alarm time, the alarm 
comparator sets the alarm latch. This latch activates the 
alarm output (pin 8). The alarm will remain activated 
until the alarm "OFF" input is connected to Vss 
temporarily. This readies the alarm latch for next com- 
parison. To deactivate the alarm output for more than 
24 hours, the alarm "OFF" input is held at Vgs for 
that long. When the alarm output is active, connecting 
pin 6 to Vgg will interrupt the alarm signal for 6 to 8 
minutes (snooze function). 

Auxiliary Counter: Date Counter Option: In this option, 
the auxiliary counter is programmed and used as a 
month and day counter. The day counter counts up to 
31 days and increments the month counter. The day 
counter rolls over from 31 to 1. The month counter 
counts up to 12 and rolls over to 1. The date counter 
can be displayed by connecting date display (pin 6) to 
Vss. Tne effects of Fast and Slow Set controls are 
shown in Table II. In this option, do not use the alarm 
output (pin 8). 

Auxiliary Counter: Timer Option: In this option, the 
auxiliary counter is programmed and used as a timer 
counter. When the display pin 6 is connected to Vgg, 
the elapsed time from the previous setting is displayed. 
The following sequence describes the use of the product 
as a minute (or seconds) timer. 

1 . Hold display pin 6 at Vss. 

2. Hold both Fast and Slow Set controls at Vgg. 

Note: This will reset the timer counter to 12:00 in 
12-hour mode and 00:00 in 24 hour mode. 

3. Release both the Fast and Slow Set controls simul- 
taneously. 

Note: The timer counter starts counting minutes 
(or seconds). 

4. If it is required to monitor elapsed time continuously, 
retain the display pin 6 at Vgg. Otherwise, release 
pin 6. 

5. Elapsed time can be displayed any time by holding 
pin 6 at Vgg. 

In this option, the clock can be used for up to 12 hours 
(12 minutes in seconds timer) of elapsed time in 12-hour 
mode and 24 hours (24 minutes in seconds timer) of 
elapsed time in 24 hour mode. The effect of Fast and 
Slow Set controls are listed in Table II. In these options, 
do not use the alarm output (pin 8). 

Accuracy of Hlapsed Time: Elapsed time = displayed 
time ± 1 minute (or second). 



2 
2 

CJ1 

w 

(J1 
X 
X 

CO 

CD 

5' 
(/i 



TABLE I. Display Modes 



SELECTED 
DISPLAY MODE 


DIGIT NO. 1 


DIGIT NO. 2 


DIGIT NO. 3 


DIGIT NO. 4 


DIGIT NO. 5 


DIGIT NO. 6 


Time Display 


10's of Hours 


Units Hours 


10's of Minutes 


Units Minutes 


10's of Seconds 


Units Seconds 


Alarm Display 


10's of Hours 


Units Hours 


10's of Minutes 


Units Minutes 








Date Display 


Month 


Month 


Date 


Date 








Minute Timer Display 


10's of Hours 


Units Hours 


10's of Minutes 


Units Minutes 


<P 





Second Timer Display 


10's of Minutes 


Units Minutes 


10's of Seconds 


Units Seconds 









1-23 



(fl 

.32 
*w 

C/i 

X 
X 

w 
p* 

CO 

in 

2 



functional description (Continued) 

TABLE II. Setting Control Functions 



SELECTED DISPLAY 
MODE 



Time Display 



Alarm Display 



Date Display 



Minute Timer Display 



Second Timer Display 



CONTROL 
INPUT 



Slow 

Fast 

Both 

Slow 
Fast 
Both 

Slow 
Fast 
Both 
Slow 

Fast 

Both 

Slow 

Fast 

Both 



CONTROL FUNCTION 



Minutes advance at 2.0 Hz rate and seconds are 

held at a reset (00) condition 

Minutes advance at 60 Hz rate and seconds are 

held at a reset (00) condition 

Time resets to 12:00:00 p.m. (12-hour mode) 

or 00:00:00 (24-hour mode) 

Alarm minutes advance at a 2.0 Hz rate 
Alarm minutes advance at a 60 Hz rate 
Alarm resets to 12.00 p.m. (12-hour mode) 
or 00:00 (24-hour mode) 

Date advances at a 2.0 Hz rate 
Date advances at a 60 Hz rate 
Date counter resets to 12:00 

Minutes (auxiliary counter) advance at a 

2.0 Hz rate 

Minutes (auxiliary counter) advance at a 

60 Hz rate 

Timer counter resets to 12:00 (12-Hour mode) 

or 00:00 (24-hour mode) 

Seconds (auxiliary counter) advance at a 

2.0 Hz rate 

Seconds (auxiliary counter) advance at a 

60 Hz rate 

Timer counter resets to 12:00 (12-hour mode) 

or 00:00 (24-hour mode) 




TIMING 
INPUT 










MULTIPLEX 




















5D/B0 Hz 




OSCILLATOR 








SELECT 






50/ bO H/ 
INPUT 


I 




SHAPING 
CIRCUIT 


PRESCALE 
COUNTER 


OpiK 
























t 


MULTIPLEXED 

CODE 

CONVERTER 

AND 

OUTPUT 

ORIVERS 
















o ► 






I.Opprn 












FAST SET 




SECONDS 
COUNTER 


TIME 
MINUTES 
COUNTER 


1.D pph 


TIME 
HOURS 
COUNTER 




TIME 


o * 








MINUTES / 
























i 








^ 








INPUT 


CONTROL 
CIRCUITS 


ftLARM 
COMPARATOR 


















, 


L 


i 
















> 




I 








AUXILIARY 
COUNTER 
DISPLAY 


AUXILIAHV COUNTER 


— 


















. 


L 


L 


BRIGHTNESS 












INPUT 


PULSEWIDTH 














M00U 


LAT0RC1R 


UIT 





















• HHS 

• 10'sMlNS. 
► MINS 
. JO'j SECONDS 
» SECONDS 



DIGIT 
ANODE 
DRIVE 
OUTPUTS 



MULTIPLEXED 
7-SEGMENT 
CATHOOE 
DRIVE OUTPUTS 



FIGURE 1. Block Diagram 



1-24 



functional description {Com 



inued) 



BRIGHTNESS CONTROL 

INPUT OR MULTIPLEX 

FREQUENCY INPUT 



FIGURE 2 




1 

01 
w 
■«j 

Ul 

X 
X 

w 

(D 

5' 

(A 



«ss>- 



Vdd>- 



50/BDmiN^ — Wv- 
100k 



1 00k 
-V</V- 



a 



v S s ™ UA - 

SLOW SET 



RESET 



FAST SET 

ALARM SET (AND DROWSE) 
ALARM DFF 



AMfPM 
COLON 



v S s = ov 

Vqd = -21V to -29V 



ALARM 
OUT 



-4BV TO O— 
-50V 



Note. LED interface - common cathode LED's (IMSN74R) can 
be interfaced with MM5375AB by using two DM75491 segment 
drivers, one DM7549:? digit driver, eight 150 J2, LOW resistors 
and a 10V power supply. 




GAS DISCHARGE DISPLAY 



0.05nF 

'150V (XB] 



vsso- 
FIGURE 3. Typical Application 



AM/PM 
COLON 



1.0MX7 



— ^^ 1 ^— > 
-vw- 



■AVH > 
-WV-ii 



10M 





xLOWEH 
V DD TRIP POINT 



SHAPED 

LINE 

FREQUENCY 



FIGURE 4. 50 or 60 Hz Shaping Circuit 



1-25 



functional description (Continued) 




MULTIPLEX 
TIMING INPUT 

BRIGHTNESS 

CONTROL 

INPUT 



DIGIT NO. 4 
UNITM1NS. 



DIGIT NO. 2 
UNIT HOURS 



DIGIT NO. 6 
10'S OF SECS. 



DIGIT NO. 3 
ID'S OF NUNS 



DIGIT NO. 1 
10'S OF HOURS 



ANY 
SEGMENT 



8TH | 
SEGMENT 



J L 



J L 



J L 



~[ PM | |coLQigf 



FIGURE 5. Output Timing Diagram 



1-26 




Clocks 



MM5376XX series clocks 



general description 

MM5376XX series clock is a monolithic MOS integrated 
circuit utilizing P-channel, low threshold, enhancement- 
mode and ion implanted depletion-mode devices. It 
provides all the logic required to give a 4 or 6-digit 
12-hour or 24-hour display from a 50 or 60 Hz input. 
An auxiliary counter allows various options. Available 
options have been listed under features. Power failure 
indication is provided to inform the user that incorrect 
time is being displayed. Setting time cancels this indica- 
tion. MM5376XX is available in a 24-lead dual-in-line 
epoxy package. 



features 

■ 50 or 60 Hz operation 

■ Single power supply 

■ Low power dissipation 

■ All counters resettable 

■ Fast and slow set controls 

■ Power failure indication 



2 
w 

00 

o> 
X 
X 

00 

CD 

5' 



■ Brightness control capability 

■ No illegal time display at turn-on 

■ Simple interface to gas discharge displays and LED's 

■ Internal digit multiplex oscillator 

■ Leading zero blanking 

■ Activity indicator 

■ 4 to 6-digit operation 

■ Available options' 

application 

■ Alarm clocks 

■ Desk clocks 

■ Automobile clocks 

■ Industrial clocks 

■ Two time zone clocks 

■ Date clocks 

■ Minute timer clocks 

■ Seconds timer clocks 



connection diagram 



available options table' 



Dual-ln-Lme Package 



1 WIN 

tOMIN 

,„R-i 

a 

NC 

10 MRS — - 
Vcd — 
AUX COUNTER DISP — 

ALARM "OFF" 

ALARM OUT — 

SLOW SET — 

FASTSFT — 

50/60 Hi in — 

50/60 Hi SEL — 



- 1 SEC J 

- BTHSEG OUT 



- BIRGHTNESSCON 

- MUX 0SC 



Note 1 : 50 Hz input at pin 12 connect pin 13 to Vr^Q. 
Note 2: 60 Hz nput at pin 12 connect pin 13 to Vgs- 

Order Number MM5376XXN 
See Package 23 



FEATURE 


FUNCTION 


OPTION NAME 


AA 


AB 


AD 


AE 


AG 


AH 


Input Frequency 


60 Hz 
50 Hz 














Time Display 


12-Hour 
24-Hour 


• 


• 


• 


• 


* 


• 


Auxiliary Counter 


Alarm Counter 
Date Counter 
Minute Timer 


• 


• 


• 


• 


• 


• 


Alarm Signal 


Tone* 


• 


• 


N/A 


N/A 


• 


N/A 




DC Level 






N/A 


N/A 




N/A 


Alarm Output 


Modulated at 2 Hz 


• 


• 


N/A 


N/A 


• 


N/A 




Not Modulated 






N/A 


N/A 




N/A 


Alarm at Power Faiiure 


"ON" 


• 


• 


N/A 


N/A 


• 


N/A 




"OFF" 






N/A 


N/A 




N/A 


Segment Output Prjlanty 


V S S for Display 
V DD for Display 


• 


• 


• 


• 


• 


• 


AM ov PM indication 


"OFF" During 
Time Display 


* 


* 




N/A 








Displayed at 






• 


N/A 


• 


• 




All Times 














8th Segment Blanked 


Y fc5 






N/A 


N/A 




N/A 


During Alarm D. splay 


No 


• 


• 


N/A 


N/A 


• 


N/A 



Tone is '16 multiplex frequency 



1-27 



absolute maximum ratings 




Voltage at Any Pin Vss + 0.3V to V$S " 30V 




Voltage at Any Display Output Pin V$S + 0.3V to VsS - 55V 




Operating Temperature —25 C to +70 C 




Storage Temperature -65° C to +150°C 




Lead Temperature (Soldering, 10 seconds) 300°C 




electrical characteristics 




Ta within operating range, Vss = 0V, S/QD = ~ 8V to ~ 29v un!ess otherwise specified. 




PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Power Supply Current 


Excluding Outputs 






8.0 


mA 


50/60 Hz Input Frequency 




DC 


60/50 


10k 


Hz 


Logic High 




v ss -io 




vss 


V 


Logic Low 






VDD 


Vss-15.0 


V 


Brightness Control Range % of 


Determined by External R and C 







95 


% 


Digit Time 


(Figure 2) 










Multiplex Oscillator Frequency Input 


Determined by External R and C 
(Figure 21 


DC 




10 


kHz 


All Other Input Voltages 












Logic High Level 




vss-i -0 


vss 


VSS 


V 


Logic Low Level 






VDD 


Vss-15.0 


V 


Power Failure Detect Voltage 


(VqD Voltage) 


-1.0 




-8.0 


V 


Output Current Levels 


VdD = ~21V to -29V 










Digit Select Outputs 


v S s = ov 










Logic High, Source 


VOH = V S S -5.0V 


8.0 






mA 


Logic Low, Leakage 


vol = v ss -45v 






40 


«A 


Segment Outputs 












Logic High, Source 


VOH = VSS - 5.0V 


2.0 






mA 


Logic Low, Leakage 


vol = v S s -45V 






10 


MA 


Alarm Output 












Logic High, Source 


VOH = VSS - 2.0V 


1.5 






mA 


Logic Low, Sink 


vol = v dd + 2.ov 


1.0 






MA 


functional description 




A block diagram of the MM5376XX series of alarm allows use of a filtered sinewave input. The circuit is a 


clocks is shown in Figure 1 . The two display modes are Schmitt trigger that is designed to provide about 3.0V 


listed in Table I. The functions of the setting controls of hysteresis. The shaper output drives a countt 


r chain 


are listed in Table II. The following discussions are which performs the timekeeping function. 




based on Figure 1 . 




50 or 60 Hz Select (Pin 13): 50 or 60 Hz inpu 


t at pin 


12 is selected by pin 13. 50 Hz operation is selected by 


50 or 60 Hz Input (Pin 12): A shaping circuit is pro- connecting pin 13 to Vqd <P in 6) and 60 Hz operation 


vided to square the 50 or 60 Hz input. This circuit is selected by connecting pin 13 to Vss (P in 1 4). 





1-28 



functional description (continued) 



Time Setting Inputs (Pins 10 and 11): The time setting 
control functions are affected by the application of Vss 
to these two pins, which are internally pulled to the 
power supply. Activating Fast Set (pin 11) causes the 
minutes counter to advance at 50 or 60 Hz rate, thus 
clocking the hours counter at a rate of one hour per 
second. Slow Set (pin 10) advances the minutes counter 
at a rate of 2 minutes per second. Activating either Fast 
Set or Slow Set resets the seconds counter to zero. When 
Fast Set and Slow Set are activated simultaneously, all 
counters are reset to 12:00 p.m. and remain in that 
count until Slow Set is deactivated. The two time setting 
inputs affect only the counters that are displayed (either 
the timekeeping counters or the alarm counters). 

8- Segment Test (Pin .28): For testing purposes, all 8- 
segment output lines may be activated by connecting 
pin 24 (S10 digit output) to V$S 

Brightness Control (Pin 24): In LED applications, 
brightness of the display may be varied by use of an 
external time constant. This time constant is used in the 
integrated circuit to control the pulse width or duty 
cycle of the 6-digit enable outputs (Figure 2). In 
gas discharge applications, connect as shown in Figure 3. 

Activity Indication (Pin 27): When all 6 digits are being 
used, it is not necessary to blink the colon to indicate 
operation of the clock, because the seconds digits 
provide this information. When only 4 digits are in use, 
the S1 digit (pin 27I may be connected to VgS- In this 
case, the colon flashes at a 1 .0 Hz rate. 

Multiplex Frequency (Pin 23): Applying an external 
time constant to this pin allows the multiplex frequency 
to be adjusted. See Figure 2. 

Power Failure Indication: If the power to the integrated 
circuit drops, indicating a momentary ac power failure 
and possible loss of clock, the AM or PM and colon 
indicator will flash at a 2.0 Hz rate. If power drops 



completely, the clock will reset itself (on resumption of 
power) to a legal state, and the AM or PM and colon 
indicators will flash at a 2.0 Hz rate. In addition to the 
flashing AM or PM and colon indicator, if a power 
failure occurs when alarm "OFF" (pin 8) is at Vqd 
(logic "0"), the alarm output will be activated (non- 
activated optional). A logic "1" (Vss) on P in 8 will 
deactivate the alarm signal. 

8-Segment Outputs (Pins 15-17, 19-22 and 26): These 
outputs contain multiplexed information for the display 
of 7-segment numerical readouts. The eighth segment 
is for the activation of AM/PM and colon(s) as included 
in the gas discharge displays for which these outputs are 
designed. 

4-Digit Operation: Connect pin 23 to VSS- 

Digit Enable Outputs (Pins 1-3, 5, 27 and 28): These 
outputs are used to select the 6 digits and are synchron- 
ized with the segment outputs. If pin 27 is grounded, 
segment outputs will be blanked during the scanning of 
the seconds digits. 

Auxiliary Counter, Alarm Counter Option: In this 
option, the auxiliary counter is programmed and used as 
an alarm counter. Pin 7 serves as both alarm display and 
snooze input pin. Alarm counter is displayed when 
pin 7 is held at Vss- Alarm setting (Table II) is 
done using Alarm Display, Fast Set (pin 11) and Slow 
Set (pin 10). If the alarm "OFF" input (pin 8) is open 
and whenever the real time matches with the alarm time, 
the alarm comparator sets the alarm latch. This latch 
activates the alarm output (pin 9). The alarm will 
remain activated until the alarm "OFF" input is con- 
nected to Vgs temporarily. This readies the alarm 
latch for next comparison. To deactivate the alarm 
output for more than 24 hours, the alarm "OFF" input 
is held at Vss for that long. When the alarm output is 
active, connecting pin 7 to Vss W 'H interrupt the alarm 
signal for 6 to 8 minutes (snooze function). 



TABLE I. Display Modes 



SELECTED 
DISPLAY MODE 


DIGIT NO. 1 


DIGIT NO. 2 


DIGIT NO. 3 


DIGIT NO. 4 


DfGITNO. 5 


DIGIT NO. 6 


Time Display 


10's of Hours 


Units Hours 


10's of Minutes 


Units Minutes 


10's of Seconds 


Units Seconds 


Alarm Display 


10's of Hours 


Units Hours 


10's of Minutes 


Units Minutes 








Date Display 


Month 


Month 


Date 


Date 








Minute Timer Display 


10's of Hours 


Units Hours 


1 O's of Minutes 


Units Minutes 








Second Timer Display 


10's of Minutes 


Units Minutes 


10's of Seconds 


Units Seconds 









1-29 



functional description (Continued) 

TABLE It. Setting Control Functions 



SELECTED DISPLAY 
MODE 


CONTROL 
INPUT 


CONTROL FUNCTION 


Time Display 


Slow 


Minutes advance at 2.0 Hz rate and seconds are 
held at a reset (00) condition 




Fast 


Minutes advance at 60 Hz rate and seconds are 
held at a reset (00) condition 




Both 


Time resets to 12:00:00 p.m. (12-hour mode) 
or 00:00:00 (24-hour mode) 


Alarm Display 


Slow 


Alarm minutes advance at a 2.0 Hz rate 




Fast 


Alarm minutes advance at a 60 Hz rate 




Both 


Alarm resets to 12:00 p.m. (12-hour mode) 
or 00:00 (24-hour mode) 


Date Display 


Slow 


Date advances at a 2.0 Hz rate 




Fast 


Date advances at a 60 Hz rate 




Both 


Date counter resets to 12:00 


Minute Timer Display 


Slow 


Minutes (auxiliary counter) advance at a 
2.0 Hz rate 




Fast 


Minutes (auxiliary counter) advance at a 
60 Hz rate 




Both 


Timer counter resets to 12:00 (12-Hour mode) 
or 00:00 (24-hour mode) 


Second Timer Display 


Slow 


Seconds (auxiliary counter) advance at a 
2.0 Hz rate 




Fast 


Seconds (auxiliary counter) advance at a 
60 Hz rate 




Both 


Timer counter resets to 12:00 (12-hour mode) 
or 00:00 (24-hour mode) 




MULTIPLEXED 

CODE 

CONVERTER 

AND 

OUTPUT 

□RIVERS 



• HRS 

• ID'sMINS. 
► WINS. 

• 10's SECONDS 

• SECONDS J 



DIGIT 
ANODE 
DRIVE 
OUTPUTS 



MULTIPLEXED 

7SEGMENT 

CATHODE 

DRIVE OUTPUTS 



FIGURE 1. Block Diagram 



1-30 



functional description (Continued) 



BRIGHTNESS CONTROL 

INPUT OR MULTIPLEX 

FREQUENCY INPUT 




ui 

w 

X 
X 

CD 

5' 



Vdd>- 



50/60HzlN^— WV- 



0/GOHzV 
IELECT/ 



SLOW SET 



RESET 



FAST SET 

ALARM SET (AND DROWSE) 

ALARM OFF 

*D0 



LINE 
FREQ. 



VdD" " 21V to -29V 



ALARM 
OUT 



-40V TO O— 
-50V 



ai50V<X8) 




H H 10M M 10S 
GAS DISCHARGE OISPLAV 



20k 1X8) 



Note. LED interface - common cathode LED's (ISISN74R) can 
be interfaced with MM5376AB by using two DM75491 segment 
drivers, one DM75492 digit driver, eight 150fi, LOW resistors 
and a 10V power supply. 



AM/PM 
g COLON 



1.0M X 7 
-VA-— i 






-Wv— " 

IBM 




FIGURE 3. Typical Application 



FREQUENCY ( 

INPUT 



V S S 

LINE 1*4^' 

ENCY O f >f> 

NPUT \Sf 




SHAPED 

LINE 

FREQUENCY 



FIGURE 4. 50 or 60 Hz Shaping Circuit 



-31 



functional description (Continued) 




DIGIT NO. 4 

UNITMINS. 



DIGIT NO. 2 
UNIT HOURS 



DIGIT NO. 5 
10'SOFSECS. 



DIGIT NO. 3 
10'SOFMINS. 



DIGIT NO. 1 
10'S OF HOURS 



ANY 
SEGMENT 



8TH 

SEGMENT 



J L 



J L 



i r 



J Irtl 



FIGURE 5. Output Timing Diagram 



32 



a 



Clocks 



2 

CJl 

w 



MM 5377 auto clock 



general description 

The MM5377 Auto Clock is a monolithic MOS integrated 
circuit utilizing P-channel low-threshold, enhancement 
mode and ion-implanted depletion mode devices. The 
circuit interfaces directly with liquid crystal 4 digit 
displays and fluorescent tubes. The display format is 
12 hours with leading-zero blanking and colon indication. 
A voltage sensitive output is provided that drives an 
energy storage network which perforins as a voltage 
doubler/regulator. The circuit uses a 2 MHz crystal 
oscillator as the reference time base and is packaged in 
a 40 lead dual-in-line package. 

features 

■ Crystal controlled oscillator (2.097152 MHz) 

■ 12 hour display format 

■ Colon output 



Leading zero blanking 

Hours and minutes set controls 

Crystal tuner output 

Voltage doubler control output 

Elimination of illegal time display at turn-on 

Direct interface to liquid crystal display 

Direct interface to fluorescent tubes 

Low standby power dissipation 



applications 



Automobile clocks 
Desk clocks 
Portable clocks 
High accuracy clocks 



block and connection diagrams 



OSC I 

oscz 



m r^ 



SET MINUTES C 
SET HOURS C 



I 


J 


I 


O 








VOLTAGE 
C0NVERT0R 




SUFFER 





Dual-ln-Line Package 



MODE 

AND TEST 

OUIC 



& 



■ c 



TT 



I 



D 



OUTPUT BUFFEflS 



.ANEO 1 

HON O 1 



II 



U" 



LX BACKPLANE 

10HDURS 

HOURS Al 

HOURS Fl 

HOURS Gl 

HOURS El 

HOURS 01 

HOURS CI 

HOURS Bl 

COLON 

1D MINUTES A2 

tO MINUTES FZ 

10MINUTESG2 

10 MINUTES U 

10 MINUTES D2 

1BMINUTESC2 

JO MINUTES 02 

MINUTES F3 

MINUTES 03 

MINUTES E3 



IGNITION INPUT 
SET HOURS 



SET MINUTES 
MODE SELECT 
TtME TEST INPUT 




CONVERTER DRIVE 



VOLTAGE MONITOR 



Order Number 5377N 
See Package 24 



■33 



absolute maximum ratings 

Voltage at V GG Pin 

Voltage at Any Pin 

Operating Temperature 

Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 



V ss + 0.3V to V ss - 30V 

V ss + 0.3V to V ss - 24V 

-40°C to +85°C 

-65°Cto+150°C 

300°C 



electrical characteristics 

T A within operating range, V ss = +9V to +20V, V DD = 0V, V GG = -10V, unless otherwise specified. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Power Supply Voltage (V ss ) 


Outputs and OSC Operational 


8 


18 


20 


V 


Power Supply Voltage (V GG ) 


Outputs and OSC Operational 


-6 


-8 


-10 


V 


Power Supply Voltage (V ss ) 


No Loss of Time Memory 


5 


18 


20 


V 


Power Supply Voltage (V ss ) 


Ignition Open 


7 


9 


20 


V 


Power Supply Voltage (V GG ) 


Ignition Open 









V 


Power Supply Current (l ss ) 


Ignition Open 


1 


3 


5 


mA 


Input Frequency 


OSC 1 


DC 


2.097152 


2.1 


MHz 


Frequency of Outputs 


Liquid Crystal Display 
f IN = 2.097152 MHz 




32 




Hz 



OUTPUT CURRENTS 



Display Segments 


V ss =+18V 










Source Current 


Vout = V SS -1V 


200 






(JA 


Sink Current 


Vqut =V SS -17V 


200 






M 


Display Colon and 10's Hours 


V ss = +18V 










Source Cunent 


Vout = V ss -1V 


400 






/J A 


Sink Current 


Vqut =V SS - 17V 


400 






M 


Display Backplane 


V ss =+18V 










Source Current 


Vout = V ss - 1 .2V 


4 






mA 


Sink Current 


Vout = V ss - 16.8V 


4 






mA 


Convertor Drive Output 


V ss = +10V 










Source Current 


Vout=V ss - 6V 


500 






IjA 


Sink Current 


Vout = V ss -8V 


100 






mA 


FOSC/2 Source Current 


V ss = +18V 












Vout = V ss - 2V 


200 






ma 


Voltage Monitor 


Zener ~ 16V 










Source Current 






100 




ma 


Trip Point 




17 


18 


19 


V 



1-34 



functional description 



A block diagram of the MM5377 auto clock is shown in 
Figure 1. A connection diagram is shown in Figure 2. 
Unless otherwise indicated, the following discussions are 
based on Figure 1. 



Oscillator 1 (Pin 34) and Oscillator 2 (Pin 33) 

A quartz crystal, resonant at 2.019752 MHz, two 
capacitors and one resistor, together with the internal 
MOS circuits form a crystal controlled oscillator as 
shown in Figure 3. Varying one of the capacitors 
allows precise frequency setting. For test purposes, OSC 
1 is the input and OSC 2 is the output of an inverting 
amplifier. 



FOSC/2 (Pin 32) 

FOSC/2 is the output of the first divide-by-two stage. 
This output allows frequency tuning of the crystal 
oscillator without adding any additional capacitance to 
the oscillator circuit. 



Ignition Input (Pin 40) 

The Ignition Input enables setting of the clock using the 
set hour or set minute inputs, and enables the drive to 
the display and the voltage doubler. When the input is 
at a voltage greater than 50 percent of the V ss supply 
the time set, display and voltage doubler are enabled. 
When the input is open circuited or at V D d . the time set, 
display and voltage doubler are disabled. The display 
outputs and backplane drive are held to V DD when the 
display is disabled. This input does not affect the accu- 
racy of the time keeping logic in any manner. 



Voltage Converter Control (Pin 31) 

The Voltage Converter Control input enables the voltage 
doubler to operate regardless of the state of the ignition 
input when it is at V DD . When the input is open 
circuited or at Vss, the voltage doubler is controlled by 
the ignition input. 



Set Hours (Pin 39) and Set Minutes (Pin 37) 

Set Hours will advance the hours at a 1 Hz rate when 
the input is held at V DD . While setting hours, the minute's 
counter may also advance the hours count. Set Minutes 
will advance the minutes at a 1 Hz rate, hold the internal 
seconds counter reset and cause the colon to blink at 
1 Hz rate when the input is held at V OD . Depressing 
both switches at the same time shall cause the clock to 
initiate a hold and not advance until the switches are 
released. 



Output Circuits 

The Converter Drive output and all display outputs are 
push-pull stages with sources common to V ss (Pin 27) 
and drains common to V DD (Pin 38) as shown in 
Figure 5. FOSC/2 output is a open-drain stage with the 
source common to V ss as shown in Figure 6. Figure 8 
illustrates the interfacing between the clock and a liquid 
crystal display and the clock and fluorescent tubes. 
When driving fluorescent tubes, V GG can be connected 
to Vnn- 



Mode Select (Pin 36) 

Mode Select determines the shape of the output wave 
form as shown in Figure 4. With the input open or at 
V OD , the output wave form is a 32 Hz square wave. 
Segments to be energized have the 32 Hz square wave 
180° out of phase with respect to the backplane 32 Hz 
square wave. Segments not to be energized have their 
outputs in phase with the backplane output. With the 
mode select input at V ss , the outputs are at a constant 
level. Segments to be energized are at V ss , and segments 
not to be energized are at V DD . 



Time Test Input (Pin 35) 



Converter Drive (Pin 29) and Voltage Monitor (Pin 26) 

The Converter Drive output oscillates at 65.636 kHz. 
The duty cycle of the wave depends on the state of the 
Voltage Monitor input pin as shown in Figure 7. With 
V S s on the input pin, the duty cycle of the output wave 
is 50%, which enables the voltage doubler. Once the 
input pin is a few volts above the zener breakdown 
voltage of its' zener diode (Figure 8) , the duty cycle of 
the output is 0% or held at V DD , which disables the 
voltage doubler. Therefore, the duty cycle of the output 
wave form varies from 50% to 0% as the voltage at the 
voltage monitor input pin varies. Therefore, the voltage 
to the chip is regulated about 2V above the zener break- 
down voltage. 



Time Test Input causes the circuit to cycle through a 
12 hour period using an internal clock of 65536 Hz 
instead of 1 Hz to increment the seconds counter when 
the input is at V S s- The input also causes the mode of 
the outputs to change from 32 Hz square wave to 
constant levels. 



Colon Output (Pin 10) 

The colon output indicates the clock is counting by 
blinking at a 1/2 Hz rate. When setting minutes, the 
colon blinks at 1 Hz rate. 



typical applications 



•-4- 



-L * 




FIGURE 3. Crystal Oscillator 



MODE SELECT 



ONSEGMENr 




FIGURE 4. Output Timing Diagram 



— i* — t it 



fix*" 



H R 



FIGURE 5. Push-Pull Output Circuit 






FIGURE 6. Open Drain Output Circuit 



1-36 



typical applications (con't) 



Jirui_ji_rL_ji 



FIGURE 7. Operation of Converter Drive 



LIQUID CRYSTAL DISPLAY 

on 

FLUORESCENT TUBES 



v — 



z/ 



SET, C 

minJ 



^LJ -01 



il SET 

Ihouf 



-w 



X 



;p 



SI OPEN LC DISPLAY 
SI CLOSED FT DISPLAY 



FIGURE 8. Typical Application 



1-37 




Clocks 



MM5378, MM5379 auto clocks 



general description 



The MM5378 and the MM5379 auto clocks are 
monolithic MOS integrated circuits utilizing P -channel 
low-threshold, enhancement mode and ion-implanted 
depletion mode devices. The MM5378 circuit interfaces 
with vacuum fluorescent 4-digit displays. The MM5379 
circuit interfaces with gas-discharge 4-digit displays. 
The display format is 12 hours with leading-zero 
blanking and colon indication. The time keeping 
function operates from a 2 MHz crystal controlled or 
externally applied source. 

features 

■ Crystal-controlled oscillator (2.097152 MHz) 

■ 12-hour display format 

■ Blinking colon output 



■ Leading-zero blanking 

■ Hours and minutes set controls 

■ Brightness control capability 

■ No illegal time display at turn-on 

■ Simple interface to vacuum fluorescent and gas 
discharge displays 

■ Low standby power dissipation 

applications 

■ Automobile clocks 

■ Desk clocks 

■ Portable clocks 

■ High accuracy clocks 



connection diagram 



Dual-tn-Line Package 





1 


U 


MULTIPLEXED 2 




SEGMENT < c — 




OUTPUTS t 

l'- 






COLON — 




5 
03C2 — 


MM537B0R 
MM 53 79 


OSC ! — 




BRIGHTNESS 7 




INPUT 




IGIT ENABLE 


m — 




OUTPUTS 


9 

mo — 





MULT1PI.EXF0 

SEGMENT 

OUTPUTS 



block diagram 



:;s=(ZH 



Order Number MM5378N 
or MM5379N 
See Package 20 



<= 



|— •— M 60SEC I — M 6QMIN I — ►[ 12 H 



JIT mr 

J MULTIPLEXER ^ 



V 



38 



absolute maximum ratings 

Voltage at Any Pin 

Voltage at Any Display Output or 

Switch Input Pin (MM 53 79 Only) 
Operating Temperature 
Storage Temperature 
Lead Temperature (Soldering, 10 seconds) 



V S S + 0.3V to Vss - 25V 
V S S + 0.3V to Vss~55V 

-40°C to +85°C 

-65°Cto+150°C 

300° C 



electrical Characteristics T/\ within operating range, Vgg = 9V to 20V, Vqq = 0V, unless otherwise specified. 



PARAMETER 



Power Supply Voltage (Vgs) 

Power Supply Voltage (Vgs) 

Power Supply Current (Igs) 

Input Frequency (Osc. 1 or Osc. 2) 

Oscillator Input Voltage 
Logical High Level 
Logical Low Level 

Switch In Voltage (MM5378) 
Logical High Level 
Logical Low Level 

Switch In Voltage (MM5379) 
Logical High Level 
Logical Low Level 

Output Currents (MM5378) 
Digit Outputs 

Logical High Level 

Logical Low Level 
Segment Outputs 

Logical High Level 

Logical Low Level 

Output Currents (MM5379) 
Digit Anode Outputs 
Logical High Level 
Logical Low Level 
Segment Cathode Outputs 
Logical High Level 
Logical Low Level 



CONDITIONS 



Outputs and Osc. Operational 
No Loss ot Time Memory 
No Output Loads 

(Note 1) 



Internal Depletion Device to 

vss 

Internal Depletion Device to 

v S s 



MIN 



VOH = Vss - 
VOL = V DD 



1V 



VOH = Vss- IV 
VOL = V D D 



VOH = V S S - 5V 

vol = vss -45v 

VOH = V S S-5V 

vol = vss -45v 



9 
5 

1 

dc 
VSS 1-5 

Vss-1.5 

VSS-5 



TYP 



MAX 



2.097152 



2.0 



8.0 



2.0 



VSS 
VDD 

VSS 



20 
25 
5 
2.1 

V S S 
VSS-5.5 

VSS 
VSS-5 



Vss-25 



UNITS 



40 



10 



40 



10 



V 
V 

mA 
MHz 

V 
V 

V 
V 

V 
V 



mA 
MA 

mA 
HA 



mA 
MA 

mA 
UA 



Note 1: These are the input levels required if an external oscillator input is preferred, using Osc. 2 (pin 51 as the input while holding Osc, 1 (pin 6) 
to V SS . 



functional description 

A block diagram of the MM5378 and the MM5379 
auto clocks is shown in Figure 1 . Connection diagrams 
for these devices are shown on the front page. Unless 
otherwise indicated, the following discussions are based 
on Figure 7 . 

Crystal Oscillator: A quartz crystal, resonant at 
2.097152 MHz, two capacitors and one resistor, together 
with the internal MOS circuits form a crystal-controlled 
oscillator as shown in Figure 2. Varying one of the 
capacitors allows precise frequency setting. For test 
purposes, Osc. 1 is the input and Osc. 2 is the output 
of an inverting amplifier. 



Time Setting: Time setting is accomplished via the 

switch input pin. If this input is a logic high during the 
M1 digit time, the minutes counter will advance at a 
2 Hz rate wtth no carry to hours counter and will also 
cause seconds counter to reset. If the switch input is a 
logic high during the M10 digit time, the hours counter 
will advance at a 2 Hz rate, minutes and seconds counter 
will continue in real time. If the switch input is a logic 
high during H1 digit time, seconds, minutes, and hours 
counters will reset to 12:00:00. If this input is a logic 
high during H10 digit time, a test mode will exist in 
which the minutes counter will advance at a 65.536 kHz 
rate with carry to hours counter {see Figure 3). An 



-39 



functional description (Continued) 




FIGURE 2. Crystal Oscillator 

internal pull-up resistor to Vgs provides normal time- 
keeping. 

Output Multiplex Operation: Outputs from the appro- 
priate internal counter are time division multiplexed at 
a 2048 Hz rate. The MM5378 and MM5379 provide 
12 outputs (4 digit-anode drive outputs plus 8 segment- 
cathode drive outputs). The additional "segment" drive 
is provided to accommodate displays which feature a 
colon. The colon output is switched at a 1/2 Hz rate to 
provide a blinking colon as a short-time indication that 
the clock is operating. 

When driving vacuum fluorescent displays which enclose 
more than one digit in a common gas envelope, it is 
necessary to either (1) inhibit the segment drive 



voltage(s) for a short time during inter-digit transitions, 
or (2) avoid physical adjacent inter-digit transitions. 
The MM5379 auto clock utilizes an interlaced output 
sequence and inter-digit blanking circuitry to prevent 
display arcing problems. The digit sequence is: (1) digit 
no. 4 (unitminutes), (2) digit no. 2 (unit hours), (3) digit 
no. 3 (ten's of minutes), (4) digit no. 1 (ten's of hours), 
etc. Blanking intervals are provided to recharge level- 
translating capacitors located in the display segment 
drive lines {Figure 6). Both segment data and digit 
enables are blanked. Figure 4 is a timing diagram which 
illustrates output timing for the MM5379. Figure 5 is a 
timing diagram which illustrates output timing for 
the MM5378. 

Brightness Control: Since display brightness is a func- 
tion of cathode segment current, a capability of inter- 
rupting this current for a variable percentage of the 
digit interval results in a brightness control. Depending 
on the magnitude of the voltage applied, the digit 
"ON" time will vary from 0% to 100% of its possible 
period in 8 1/3% increments. This is illustrated in 
Figures 4 and 5. 

Output Circuits: All display output drivers, both digit 
and segment outputs, are open-drain enhancement 
devices [Figure 6). Thus, all outputs are capable of 
sourcing currents while external pull-downs are required 
to sink currents. Figure 7 illustrates method of inter- 
facing these outputs to gas discharge displays. 



DIGIT ENABLE 
UNITMiNS 


M 


















DIGIT ENABLE 
UNIT HOURS 


HI 




DIGIT ENABLE 
TEN'S MINS 




1 M10 1 

1 




DIGIT ENABLE 
TEN'S HOURS 


mo J 



SELECTED MODE 



SWITCH IN v 
WAVEFORM v. 



SWITCH IN " 
WAVEFORM v L 



SWITCH IN Vh 
WAVEFORM v. 



SWITCH I 
WAVEFORM 



















-^488^ 










1 








- 366ns 


















^12Z, 







SWITCH III 
WAVEFORM 



n ¥ «— r 
M v, — I 



MORE THAN ONE 




HELD AT V H 



MINUTES COUNTER ADVANCES AT 2 Hz RATE. 
HOURS COUNTER UNAFFECTED. COLON HELD "ON " 



TIME SET AND HELD AT 12:00.00, 
COLON HELD "ON ". 



HOURS COUNTER ADVANCES AT 2 Hz RATE. 
MINUTES COUNTER UNAFFECTED. COLON BLINKING. 



MINUTES COUNTER ADVANCES AT 65,536 kHz RATE WITH COMPLETE 
CARRY. COLON HELD "ON" AT 65.536 kHz RATE. 



NORMAL TIME KEEPING. 
COLON BLINKING, 



NORMAL TIME KEEPING, 
COLON BLINKING. 



SWITCH IN 
WAVEFORM 



TIME SET AND HELD AT 12:00:00. 
COLON HELD "ON". 



FIGURE 3. MM5378, MM5379 Setting Control Functions 



1-40 



functional description (Continued) 



v S s- 

V - - 

v S s- 
v-- 

v S s- 
v~- 

v S s- 



■— 488ns 

an 



- 36644s 



— 122ns 



vss 



33.3% 
BRIGHT 



:~~u~ -nnnr 

ON ON ON ON 

v ss ""i""o"""n"°" n"°"* | "n " o '""i T'°" 1 



DIGIT NO. 1 
UNITMINS 



DIGIT NO. 2 
DNITHODRS 



DIGITN0.3 
TEN'S MINS 



DIGIT NO. 4 
TEN'S HOURS 



ANY 
SEGMENT 



00% 
BRIGHT 





M1 


I 




-—488ns 




H. 1 






• — 366ns 




f M10 ] 




— 


— — 122 w s 




I H10 | 








BRIGHT 


ON 


OFf JT ON |[ ON 1 1 ON 



33.3% 
BRIGHT 



_JL 



jujljl: 



.G^JznEEOJXuzioii: 
ji_EL_[LJLjr: 



33.3% 

BRIGHT 



VSS 
V" 

vss 

V - 

Vss 

V - 

v S s 

V" 

«ss 

V" 

v S s 

V - 

vss 
v- 

v S s 



FIGURE 4. MM5379 Output Timing Diagram 



FIGURE 5. MM5378 Output Timing Diagram 



Q(DATA) — 




P 

' 1 TYPICAL DIGIT 

O » OR SEGMENT 

(OPEN DRAIN) OUTPUT 



VSS 



QIDATA) 



-D>o — il 



TYPICAL DIGIT 
■♦OR SEGMENT 



(OPEN DRAIN) OUTPUT 



FIGURE 6. Output Circuits 



functional description (Continued) 



100k 



BRIGHTNESS 7 



i k 35V —I — 

. 1 ' 






^ 



IGNITION 

+ 



6- 25 pF 26 pF 



> MIN HOURS 

4JSW1TCH in Iq I 

t I 



►I Wr| 1> 




FIGURE 7. Typical Application for MM5379 



1-42 




Clocks 



MM5382, MM5383 digital calendar clock radio circuits 



general description 



2 
w 

00 
M 

2 
w 
w 

00 
CO 



The MM5382 and MM5383 digital calendar clock 
circuits provide the timing, control, and interface 
minimum-cost, solid state, digital clock 



circuitry for 
radio. 



The timekeeping function operates in either a 12-hour 
or a 24-hour mode. The MM5382 is the 12-hour version, 
and has a morith<Jateformat;the MM5383 is the 24-hour 
version, and has a date-month format. 

Outputs consist of a presettable 59-minute sleep timer 
(e.g., a timed radio turn-off) and an alarm tone. A power 
failure indication warns the user that the time displayed 
may be in error. 

Other features include: alarm display; brightness control; 
24-hour alarm set; PM indication; fast and slow set 
controls; and a 9-minute snooze alarm. (The MM5383 
has an alarm "ON" indicator.) Both circuits provide 
open drain outputs for the direct drive of LED displays 
to 15 mA. 



features 

■ 50 or 60 Hz operation 

■ 12 hour, month-date (MIV15382) or 24 hour, date- 
month (MM5383) display 

■ PM indication (MM5382) 



■ Leading zero blanking 

■ 24-hour alarm setting 

■ Power failure indication (the word "OFF" is displayed 
in MM5382 and all "ON" digits blink in MM5383 

■ Brightness control 

■ Date display (4 year calendar) 

■ Presettable 59-minute sleep timer 

■ Alarm display 

■ Fast and slow set sleep and alarm 

■ 9 minute snooze alarm 

■ Blinking colon 

■ Alarm "ON" indication (MM5382 only) 

■ Alarm tone output 

■ No illegal time or date display at turn-on 

applications 

■ Alarm clock 

■ Desk clock 

■ Clock radios 

■ Stop watch 

■ Industrial clock 

■ Portable clock 

■ Timer 

■ Sequential controllers 



Q 



connection diagrams 

Dualln-Ltne Package 



Dual-ln-Line Package 



1 




40 
—10 HRS -b 


10 HRS -e — 




40 
—10 HRS -d 


I'M — 




39 
—10 HRS - c 


2 

10HRS -g — h 




39 

— 10 HRS -c 


:MC — 




36 
— HR -e 


3 
10 HRS -j— J 




3fl 
— HR -e 


BRIGHTNESS REF. OUTPUT 




37 
— HR -d 

36 
— HR -c 


4 
10 HRS-b^— 




37 
HR - d 


ALARM OUTPUT — 




BRIGHTNESS REF. OUTPUT—— 




36 


6 
SLEEP OUTPUT — 




35 
HR-g 

31 
HR -b 


6 
ALARM OUTPUT —h 




35 
HR-g 


50/60 Hz DRIVE — 




SLEEP OUTPUT 




34 
— HR - h 


8 
5D/60 Hz SELECT — 




33 

— HR -a 


B 
50/60 Hz DRIVE — 




33 

— HR -a 


9 

vss — 




32 
— HR -1 


9 
50/60 Hz SELECT 




32 
— HR -f 


10 

voo — 
11 

DATE DISPLAY'ADVANCE— 


MM5382 


31 
COLON 

30 
10MINS -b 


10 

v ss — 
Vdd — 


MM5383 


31 
COLON 

30 
— lOMINS-h 


12 
ALAHM ON/OFF— 




29 
— 10MINS -a 


52 
DATE DISPLAY/ADVANCE 




29 
— 10MINS-a 


13 
ALARM DISPLAY, SET/SNOOZE— 




28 
10MINS -f 


13 
ALARM 0N70FF — 




28 
— 10MINS -f 


SEQUENCE/SLEEP DISPLAY- 




27 
1DMINS-9 

26 

1DMINS -e 

25 
— 10 WINS- d 


14 
ALARM DISPLAY, SET/SNOOZE— 




27 

— tOMINS-g 


BRIGHTNESS REF INPUT- 




15 
SEQUENCE/SLEEP DISPLAY 




26 

— IQMINS-e 


ALARM "ON INDICATOR 




BRIGHTNESS REF. INPUT — 




25 

—10 MIMS - d 


17 
.WIN - f — 




21 

10MINS- c 


17 
MIN -f 




24 

— lOMINS-c 


MIN -a — 




23 

— MIN - e 


18 
MIN -a — 




23 
■^MIN -e 


19 




22 


19 




22 


MIN b — 




— MIN - d 


MIN - b — 




— MIN -d 


20 




21 


20 




21 


MiN g 




— MIN ~c 


MIN -g — 




— MIN -c 




TOP VIEW 




TOP VIEW 







rder Number MM5382N 


o 


rder Number MM5383N 




See Package 24 






See Package 24 





1-43 



absolute maximum ratings 










Voltage at Any Pin except Segment, 


Vgs +0-3V to Vss -28V 










Colon, and PM 












Voltage at Segment, Colon, and PM 


Vss+0.3Vto Vss -10V 










Operating Temperature 


-25°C to +70°C 










Storage Temperature 


-65°C to+150°C 










Lead Temperature (Soldering, 10 seconds) 300"C 










Maximum Power Dissipation 


1 Watt 










Electrical Characteristics 












Ta within Operating Range Vgs = +18V to +26V, Vqo = ov . 












with specified output drive 












unless otherwise specified 










Functional Clock Voltage 


Vss = +8V to +26V ' V DD = 
(No output drive spec) 










electrical characteristics 












PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Power Supply Current 


No output levels 












VSS = 8V 






4 


mA 




VSS = 26V 






5 


mA 


50/60 Hz Input 












Frequency 




DC 


50 or 60 


30k 


Hz 


Voltage 


V S S = 18V 










Logical High Level 




vss-1 


VSS 


vss 




Logical Low Level 




VDD 


VDD 


VDD+1 




Switch Input Voltages 












(Date, Sequence, Alarm 












Enable, Alarm Display) 












Logical High Level 




vss-1 


VSS 


vss 




Logical Low Level (1) 


Nominal Floating Level 


VsS-3 


Float 


VSS-6 


V 


Logical Low Level (2) 




VDD 


VDD 


Vqd+2 


V 


All Other Input Voltages 












Logical High Level 




vss-1 


VSS 


VSS 




Logical Low Level 


Internal Depletion Load 
to VqD 






VsS-15 




Power Failure Detect Voltages 


(Vss Voltage) 


1.0 




8.0 


V 


Output Currents: 


Vss = 18V to 26V, VQD = 0V 










All Segments and Colon 












Logical High Level, Source 


VOH = V S S-2V 


15 






mA 


Logical Low Level, Leakage 


vol = v S s -iov 






10 


MA 


PM Indicator and Alarm Indicator 












Logical High Level, Source 


VOH = Vss -2V 


15 






mA 


Logical Low Level, Leakage 


VOH = V S S -10V 






10 


PA 


Alarm and Sleep Outputs 












Logical High Level, Source 


VOH = V S S-2V 


2 






mA 


Logical Low Level, Sink 


V H = V SS -15V 


500 






MA 


Alarm Output Tone 


Vss= 18V to 26V 


400 




2000 


Hz 


Frequency Modulated with 2 Hz 












Total Power Dissipation 


V S S = 26V, V DD = 0V 
'OUT (25 Segments) = 15 mA 
T = 70°C 
V0UT = V SS -2V 






830 


mW 



1-44 



block diagram 



VooC 



1 




i 


SHAPING 
CIRCUIT 




50 OR 60 





c 



YIMC 

SECONDS 
COUNTER 



ALARM AND 

SLEEP 

CIRCUIT 

r — 



TIME 
MINUTES 
COUNTER 



fiME 
HOURS 
COUNTER 



iLARM COMPARATOR 



ALARM 
MINUTES 
COUNTER 



ALARM 
HOURS 
COUNTER 






CODE 

CONVERTER 

ANO 

OUTPUT 

DRIVER 



► OIGIT4 

► DIGIT 3 

► COLON 

► DIGIT 2 

► DIGIT 1 



5 
w 

00 
ISJ 



Display Tir 
Set Time 



Display Alarm 



Set Alarm: 
2 Hz Rate 



60 Hz Rate 
Display Sleep 



Set Sleep: 
2 Hz Rate 



60 Hz Rate 



FIGURE 2. 
TABLE I. Display Modes and Setting Control Functions 



DATE DISPLAY/ 
ADVANCE 



Float 
Float 



VDD 
Float 



VDD 



Vqd (Advances at 60 Hz Rate) 



functional description 

Connection diagrams for the MM5382 and the MM5383 
Digital Clock Radio Circuits are shown in Figure J. 
A block diagram of these devices is shown in Figure 2. 
Unless otherwise indicated, the following discussions 
are based on Figure 2. Figure 3 shows the general 
purpose alarm clock and procedure to set the time, 
month, day, alarm and sleep counters. Table I shows 
the display modes and setting control functions. 



ALARM DISPLAY - 
SET/SNOOZE 



Float 
Float 



SEQUENCE/SLEEP 
DISPLAY 



Float 

Momentary connect to Vqq 
for each step of setting time 
and calendar 
Float 



Connect to Vrjrj 


Float 


for < 2 seconds 




Connect to Vqq 


Float 


for > 2 seconds 




VDD 


Float 


Float 


Connect to Vss for < 2 




seconds 



Hold Vgs for > 2 seconds 
{Advances at 2 Hz Rate) 

VSS 



50 or 60 Hz Select Input: A programmable prescale 
counter divides the input line frequency by either 50 or 
60 to obtain a 1 Hz base. This counter is programmed 
to divide by 60 simply by leaving the pin unconnected; a 
pull-down to Vdq is provided by an internal resistor. 
Operation at 50 Hz is programmed by connecting this 
input to Vss. 



50 or 60 Hz Drive: A shaping circuit is provided to 
square the 50 or 60 Hz input. This circuit allows use of a 
filtered sinewave input. The circuit is a Schmitt trigger 
that is designed to provide about 4V of hysteresis. A 
simple RC filter should be used to remove possible line- 
voltage transients that could either cause the clock to 
gain time or damage the device. The input should swing 
between Vss a™ 1 Vrj[). The shaper output drives a 
counter chain which performs the timekeeping function. 



Alarm Operation: The internal alarm comparator senses 
coincidence between the alarm counters (the alarm 
setting) and the time counters (real time). The comparator 
output is used to set a latch in the alarm and sleep cir- 
cuits. The alarm latch remains set for 59 minutes during 
which time the alarm or radio will sound if the latch 
outputs are not temporarily inhibited by another latch 
set by the snooze input or reset by the alarm "OFF" 
input. 



1 45 



functional description (Continued) 

Alarm ON/OFF/RADIO Input: Momentarily leaving this 
input unconnected resets the alarm latch and thereby 
silences the alarm. This input is also used to determine 
if the alarm or the sleep output will be enabled when the 
alarm latch is set. By connecting the input pin to Vrjrj, 
both the alarm output and the sleep output (radio) are 
enabled when the alarm latch is set. If the input pin is 
connected to Vgs. on ' v tne sleep output (radio) is 
enabled when the alarm latch is set. Momentarily leaving 
this pin unconnected also readies the alarm latch for the 
next comparator output, hence, the alarm will auto- 
matically sound again in 24 hours (or at a new alarm 
setting). If it is desired to silence the alarm for a day or 
more, the Alarm ON/OFF Radio input pin should re- 
main unconnected. 

Alarm Output: The alarm output signal is a tone of from 
400 Hz to 2000 Hz, which is gated on and off at a 
2 Hz rate. 

Alarm Display, Set/Snooze: Momentarily connecting this 
pin to V(3D when the alarm and sleep outputs are dis- 
abled displays the alarm setting for 1 .5 to 2 seconds. The 
display shows the hours and minutes of the alarm setting, 
a constant colon and a PM indication if the clock is in 
the 12 hour mode. If the input pin is held to VrjD for 
longer than 2 seconds, the minutes of the alarm counter 
start to advance at a 2 Hz rate. To increase the rate that 
the alarm counter is set at, also connect the Date/ 
Advance input pin to Vpo- The minutes of the alarm 
counter will now advance at a 60 Hz rate. By momen- 
tarily connecting the input pin to Vqd vvhen the alarm 
or sleep output is enabled, snooze is enabled for 8 or 9 
minutes. Snooze inhibits the alarm output for between 
8 and 9 minutes, after which the alarm output is enabled 
again. Snooze has no effect on the sleep output. The 
snooze feature may be repeatedly used duringthe 59 
minutes in which the alarm latch remains set. Momen- 
tarily connecting this input pin to Vqd when the clock 
is in the power failure mode stops all power failure 
indications and displays alarm. If this pin is connected to 
Vss and date advance pin is connected to V$s, the clock 
is in a test mode. All outputs are enabled and time and 
alarm are set to 12:00 AM, the date is set to the 12th 
month and the 1st day, and the sleep counter is set to 
00 minutes. If the Alarm Display, Set/Snooze is at Vss. 
all outputs and inputs are disabled except 50/60 Hz 
Select and 50/60 Hz Drive. 

Sleep Timer and Output: The sleep output can be used 
to turn off a radio after a desired interval of up to 59 
minutes. The time interval is chosen by selecting the 
sleep display mode and setting the desired time interval. 
This automatically results in a current-source output, 
which can be used to turn on a radio (or other appliance). 
When the sleep counter, which counts downwards, reaches 
00 minutes, a latch is reset and the sleep output current 
drive is removed, thereby turning off the radio. This 
turn-off may also be manually controlled (at any time in 
the countdown) by a momentary Vqd connection to 
the Alarm Display, Set/Snooze input. 

Sequence/Sleep Display and Set: If left open, time or 
the counter to be set is displayed. Momentarily con- 
necting this pin to Vss displays the sleep counter for 
1.5 to 2 seconds. If after 2 seconds the pin is still at VgS- 
the sleep counter will decrement at a 2 Hz rate. To 



increase the rate at which the sleep counter is decre- 
mented, also connect the Date/Advance pin to VDD. 
The sleep counter will now decrement at a 60 Hz rate. 
Momentarily connecting the Sequence pin to Vqq steps 
the clock through its set modes. There are 6 states; they 
are real time, set hours, set minutes, set month (12 hour 
mode), set day (12 hour mode), and the holding state. 
When real time is displayed, a momentary connection 
to VqD advances the clock to the set hours state. In this 
state, hours are displayed, minutes are blanked, the colon 
is constant, and an A or P is displayed in the unit minutes 
position if the clock is in the 12 hour mode. To set 
hours, the Date/Advance pin is connected to Vqq. The 
next time the Sequence pin is connected to Vrjp, the 
clock is advanced to the set minutes state. In this state, 
the minutes are displayed, the hours are blank, the colon 
is constant and the PM indication is displayed if the 
clock is in the 12 hour mode and set for PM. The next 
state the clock advances to is the set left state. In the 
12 hour mode, this is a month set state. For the 24 hour 
mode, this is a day set state. In this state, the left two 
digits of the display are shown, the colon and the right 
two digits of the display are blank. The next state the 
clock advances to is the set right state. In this state, 
the day in the 12 hour mode or month in the 24 hour 
mode is displayed in the right two digits of the display. 



T, P a n o 
o 

COLON 



n rr 



n 



:iJ 



r nc-i: 

H F P 

L lJc__jJ 



o 
o 



U---J 



o 

o 



L In 



P P 
lI Lie 



o 



o 



'1 



SET MINUTES 



Time and Date Display Format in 'Set' Mode 



1-46 



functional description (Continued) 

The left two digits and colon are blank. The next transi- 
tion on the Sequence input displays real time if the 
minutes were not set. If the minutes counter was set, 
the next state the clock advances to is the holding state. 
In this state the time and the colon are blinking at a 
2 Hz rate and held to the set time. To leave the holding 
state, the Sequence Input is connected to Vqd momen- 
tarily. If the clock remains in any state except the 
holding state for more than 10 seconds without being 
set, the clock will automatically advance to real time or 
the holding state if minutes were set. 

Note: Time set mode should not be initiated while in 
alarm or sleep display 2 second time out. Time set mode 
should be sequenced only when the clock displays real 
time. 



Date/Advance Input: If left open, this input has no 
effect on the clock. Momentarily connecting this pin to 
Vqd displays the date for 1.5 to 2 seconds if the clock 
was not in a set state. If after 2 seconds the input pin is 
still at Vqd, the date remains displayed until the input 
pin is released. If the Date/Advance pin is connected to 
Vprj when the clock is in a set mode, the counter dis- 
played will advance at a 2 Hz rate until the pin is released. 
Connecting this input pin to VDD w hen the sleep counter 
or the alarm counter is displayed advances the displayed 
counter at a 60 Hz rate. If the Date/Advance pin is con- 
nected to V$S. the seconds counter is bypassed and 
minutes counter advances at a 1 Hz rate. 

Colon: The colon output blinks at a 1 Hz rate in the run 
mode. It is constant during set hours and minutes, and 
alarm display. The colon is blank for date display. The 
colon blinks at a 2 Hz rate in the holding state. 



Alarm Indication Output: Whenever the alarm is enabled, 
the Alarm Indicator output is turned on. It is used to 
indicate to the user that the alarm has been set. 

PM Output: The PM Output is available only in the 
WIM5382. This output is enabled only when time or 
alarm are displayed. 

Power Failure Indication: If the power to the integrated 
circuit drops, indicating a momentary ac power failure 
and possible loss of the correct time, in the MM5382 
the word 'OFF' is displayed blinking at a 2 Hz rate, in 
the MM5383 all the 'ON' segments blink at 2 Hz rate 
and the colon is blank. Momentarily connecting the 
Alarm Display Set/Snooze input to Vqd displays first 
the alarm for 1.5 to 2 seconds and then real time. In 
addition, if the alarm was "ON" the Alarm "ON/OFF" 
input should also be momentarily connected to Vprj. 

LED CURRENT CONTROL INPUT AND 
REFERENCE OUTPUT 

Pin (15) MM5382, pin (16) MM5383 controls the gate 
voltage at all the display outputs and the reference device. 
The output drives can be disabled by connecting pin 15 
MM5382, 16 MM5383 to V S S- This wire-OR capability 
allows the display to be used for other functions (e.g., 
temperature). The output current can be controlled two 
ways: 1) driving the output in saturated mode; 2) driving 
the output in linear mode. (Refer to Figures 4 and 5. ) 

1. The reference device pins (4, 15) MM5382 (5, 16) 
MM5383 are connected as diodes and an external 
resistor is used to set the desired current in these 
diodes (see Figure 4). The segment drivers of all 
digits are connected as current mirrors. The drain 



2 

oi 
w 

00 



2 

CJl 

w 

00 

w 







REAL TIME AND 
DATE SETTINGS 


1 

CE 


10SECONDS 
(ADVANCE FLOATING) 


X SEQUEN 


HOUR DISPLAY 

IE 1 : « 

OR 
III- P 












^ SEQIiEN 


CE 






10 SECONDS 
(ADVANCE FLOATING) 


MINUTE DISPLAY 

•C CI 
• -1 _l 












10SECONDS 
(ADVANCE FLOATING) 








"ADVANCE 1 ' 
ATV DD 
SETS AT 

2 M RATE 


XSEQUEM 


E 




LEFT DISPLAY 
MONTH MM5382 








10SECGNDS 
(ADVANCE FLOATING) 










X SEQUEN 


E 




RIGHT DISPLAY 
MM 5382 DAY 






















REAL TIME AND 
DATE SETTINGS 




I0SECONDS 
[ADVANCE FLOATING) 




1 SEQUEN 


CE 


HOUR DISPLAY 

1 3 * 

1 1 • 

OR 

i n * 

1 l_ • 












X SEQUEN 


CE 






10SECONQS 
(ADVANCE FLOATING) 


MINUTE DISPLAY 

■C CI 
• _l _l 










i 
i 


1GSEC0N0S 
{ADVANCE FLOATING) 








"ADVANCE' 

*TV D0 

SETS AT 

2 Hi RATE 


XsEQUEN 






E 




LEFT DISPLAY 
DAY MM5383 








10 SECONDS 
(ADVANCE FLOATING) 










X SEQUEN 


E 




RIGHT DISPLAY 
MM53B3 MONTH 














E 










Time and Date Set Flow Chart 
MM5382, 12-Hour Mode 



Time and Date Set Flow Chart 
MMS383, 24-Hour Mode 



1-47 



CO 
00 
CO 

in 

S 

cm" 

CO 
CO 

in 

2 



functional description (Continued) 

voltage V1 of the segment drivers is selected such 
that these devices operate in saturation mode. 
Since the drain current variation in saturation 
mode operation of the MOS device is relatively 
constant, the segment drive current does not vary 
significantly, even though V1 is increased con- 
siderably. However, as the voltage across the output 
buffers increases, average power dissipation also 
increases linearly. This technique of current control 
is recommended to be used only with low current 
LEDs (1-7 mA). 



The high current drive requirement of large LED 
displays can be accomplished by operating the 
segment drivers in the linear mode. The circuit 
for high current LED drivers is shown in Figure 5. 
The reference output device is used in series with 
a reference LED, diode and current setting resistor. 
A high beta PNP transistor provides the current 
drive for all the segments. A reference voltage V3 
is developed which compensates for variations in 
MOS process parameters and the variations in the 
voltage drop across the LED. The resistor sets the 
current in the reference LED which sets the 
reference voltage V3 which in turn sets the current 
in the LEDs equal to resistor current minus the 
base current of the transistor. Variation in second 
supply voltage does not vary the LED currents so 
long as the PNP transistor is kept operating in the 
linear mode. Full wave rectified power supply 
without any filtering can be used as a second 
supply voltage V2. The LED brightness can be 
varied by using a variable resistor. 



Figure 6 shows a LED drive circuit which uses a single 
resistor. The resistor controls the total current flowing 
through all the segments. Brightness shall vary depending 
on number of segments that are "ON" at that time. 



Radio Frequency Interference: All display outputs in- 
clude circuitry to slow up the switching transition time 
to minimize radio frequency interference. 



Clock Set Up Procedure: (MM5382) 

1. Connect 110V supply. 

2. Blinking 'OFF' displayed. 

3. Momentarily connect alarm display set/snooze pin 
(13) to Vqd which removes "OFF" and displays 
first the alarm for 1.5 to 2 seconds, then real time. 

4. Momentarily connect alarm "ON/OFF" to VsS- 

5. Wait till the colon starts blinking. (Approximately 
2 seconds.) 

6. Time setting 

a. Momentarily connect sequence pin (14) to Vqd 
display shows hour and AM or PM. Connect 
advance pin (11) to Vqd to advance hour. 

b. Connect pin (14) momentarily to Vqd display 
shows minutes, connect pin (11) to Vqd an d 
set minutes. 

c. Connect pin (14) momentarily to Vqd display 
shows month, connect pin (11) to Vqd and 
set month. 

d. Connect pin (14) momentarily to Vqd display 
shows date, connect pin (11) to Vqd ar| d set 
date. 

e. Connect pin (14) momentarily to Vqd ar >d *h e 
real time is displayed at 2 Hz rate. 

f. Connect pin (14) momentarily to Vqd again 
and real time is displayed continuously. 

7. Alarm setting 

a. Connect alarm display pin (13) to Vrjo and 
hold it for more than 2 seconds. Alarm minutes 
will advance at slow rate. 

b. Connecting pin (11) and pin (13) to Vqd 
simultaneously will advance the alarm time at a 
fast rate. 

c. Set the desired alarm time. 

8. Sleep time setting 

a. Connect, sleep display, pin (14) to Vss ar| d 
hold it for more than 2 seconds. Sleep time will 
decrement at slow rate. 

b. Connecting pin (11) and pin (14) to Vqd 
simultaneously will decrement the sleep time at 
a fast rate. 

c. Set the desired sleep time. 

9. Connect pin 12 to Vqd t0 activate alarm. 

Note: Time and date setting must be done only in the 
real time display mode. 




H ALARM 6 / DISPLAY" I 
off/ and t" 
FMIknTt T 



~> fSLI 



SB/60 H; 
SELECT 
ALARM OUTPUT 



LED REFERENCE OUTPUT 



^— ■ COLON -^-" ■ "*— ■ 

J I I I I— 

' BRIGHTNESS CONTROL " """ 10'S Of HOUR UNIT HOUR tO'SOFMINUTE UNIT MINUTES 

FIGURE 3. Calendar Alarm Clock Using the MM5382 and a LED Display 




1 48 



functional description (Continued) 



BRIGHTNESS V LE0 SUPPLY 
/CONTROL 0C0R-OOC7- 

RESISTOR Q 



l R' l lED ■ 



®U- 



z¥5 

CONTROL 
LOGIC 




FIGURE 4(a). Low Current LED Drive Control Circuit (1-7 mA) 















i 


(t 








t 






-,1> ! i-- 








d 


~1 

t" 






I i 






I , - 








fUa.n^ 




^ss 













-7 -9 -11 



FIGURE 4(b). Segment Current vs V| 

(V DD at -18V) (Typical Output Characteristics) 



BRIGHTNESS CONTROL RESISTOR 



'REFERENCE 
LED.| R - l bQ , 



/ V lED SUPPLY 

1/' "I0»cccr 




4 r4 rt 

v$s v ss 



OUTPUT 

DRIVER 

OPERATING 

REGION 

















*\ 


0-7 mA 
J12.5 

H 










1 








£~ 


~T 


SEGMENT T^>*, ->| 






:.^i, 












i 















-5 -iQ _ib _20 -25 -30 
Vrj D <V) (REFERENCEDTOV SS ) 



FIGURE 5(a). High Current LED Drive Current Circuits (7-15 mA) 



FIGURE 5(b). R ON vsV DD (V DS at--1V) 
(Typical Output Characteristics) 



V LED SUPPLY 



CURRENT 

R LIMITING 

RESISTOR 



O CONTROL 6 O 



V SS LOGIC 



FIGURE 6. Simple LED Drive Circuit 



— 




























Ill I 






""" 


I! '" 













V| N IV) 

FIGURE 7. I|imvsV| N (Typical 
Input Depletion Load Characteristics) 



1-49 




Clocks 



MM 5384 LED display digital clock radio circuit 



general description 

The MM5384 digital clock radio circuit is a monolithic 
MOS integrated circuit utilizing P-channel low-threshold, 
enhancement mode and ion-implanted depletion mode 
devices. It provides all the logic required to build several 
types of clocks and timers. Four display modes (time, 
seconds, alarm and sleep) are provided to optimize 
circuit utility. The circuit interfaces directly with 3 1/2 
digit 7-segment LED displays. The timekeeping function 
operates from either a 50 or 60 Hz input, and the 
display format is 12 hours (with leading-zero blanking 
and AM/PM indication) or 24 hours. Outputs consist of 
display drivers, sleep (e.g., timed radio turn-off), and 
alarm enable. Power failure indication is provided to 
inform the user that incorrect time is being displayed. 
Setting the time cancels this indication. The device 
operates over a power supply range of 8— 26V and does 
not require a regulated supply. The MM5384 is packaged 
in a 40 lead dual-in-line package. 



features 

■ 50 or 60 Hz operation 

■ Single power supply 

■ 12 or 24 hour display format 

■ AM/PM outputs 

■ Leading-zero blanking 



1 12-h 



our format 



24-hour alarm setting 
All counters are resettable 
Fast and slow set controls 
Power failure indication 
Blanking/brightness control capability 
Elimination of illegal time display at turn-on 
Direct interface to 0.5" LED displays 
9-minute snooze alarm 
Presettable 59-minute sleep timer 



applications 

■ Alarm clocks 

■ Desk clocks 

■ Clock radios 

■ Automobile docks 

■ Stopwatches 

■ Industrial clocks 

■ Portable clocks 

" Photography timers 

■ Industrial timers 

■ Appliance timers 

■ Sequential controllers 



block and connection diagrams 



OUTPUT , 
COMMON O— 
SOURCE 



G 


SHAPING 
CIRCUIT 




■:■ 50 OR GO 












5 




t 


1PPS 




° 











ALARM 

OUT * 
ALARM , 



SLEEP 0IS O— 
ALARM 1 



SECONDS qJ 



SLOW SET C 
FAST SET C 

vssc 

VqoC 



1, 


TIME 




IP 


*M 


TIME 
MINUTES 
COUNTER 


IPPH 


TIME 
HOURS 
COUNTER 




COUNTER 






* 


1G 








' 










15 








' 







+ 




h 


' 


17 


ALARMS 

SLEEP 
CIRCUITS 


ALARM COMPARATOR 


- 1* 


| . 


L 


■ 


i, 




















SLEEP 




ALARM 




ALARM 




C0IJ 


m 


R 




cou 


TER 




COU 


UEfl 



} 



art, urn us 

^> 

ALARM 
SLEEP 



L 



CODE 
CON- 
VERTERS 

AND 
OUTPUT 
DRIVERS 



10 | OS 

\ QFHRS 

OfGIT 



-*\ TO MRS 
— j/ DIGIT 



26-31 K TO 10'S 

\ Of MINS 

V DIGIT 



Duat-ln-Line Package 



PM OUT 

COLON (1 Hil 

12/24 Hit SELECT 

BUNKINtJIN 

50/60 Hr SELECT 

50/60 H; IN 

FAST SET IN 

SLOW SET IN 1 

SEC5 DISPLAY IN- 

ALARM DISPLAY IN' 

SLEEP DfSPLAY IN' 

V DD ■ 

Vss 1 

SLEEP OUT' 

ALARM Of F IN' 

ALARM OUT' 

SNOOZE IN 

UT COMMON SOURCE 

WINS -c 

MINS - d' 




umber MM5384N 
i Package 24 



FIGURE 1. 



1-50 



absolute maximum ratings 

Voltage at Any Pin Except Segment Outputs Vss + 0.3 to Vss - 30V 

Voltage at Segment Outputs Vss + 0.3 to Vss ~ 1 5V 

Operating Temperature -25°C to +70°C 

Storage Temperature ~65°C to +150°C 

Lead Temperature (Soldering, 10 seconds) 300°C 

electrical characteristics 

Ta within operating range, Vss = 24V to 26V, Vqd = 0V, unless otherwise specified. 



PARAMETER 



Power Supply Voltage 
Power Supply Current 



50/60 Hz Input Frequency Voltage 
Logical High Level 
Logical Low Level 

50/60 Hz Input Leakage 

Blanking Input Voltage 
Logical High Level 
Logical Low Level 

Blanking Input Leakage 

All Other Input Voltages 
Logical High Level 
Logical Low Level 

Power Failure Detect Voltage 

Count Operating Voltage 

Hold Count Voltage 

Output Current Levels 

10's of Hours (b&c), 10's of 

Minutes (a & d) 

Logical High Level, Source 
Logical Low Level, Leakage 

1 Hz Display 

Logical High Level, Source 
Logical Low Level, Leakage 

All Other Displays 

Logical High Level, Source 
Logical Low Level, Leakage 

Alarm and Sleep Outputs 
Logical High, Source 
Logical Low, Sink 



CONDITIONS 



Output Driving Display 
Functional Clock 

No Output Loads 
VSS = 8V 
VSS = 26V 
Vss= 8V to 26V 



Internal Depletion Device to Vrjp 
(Vss Voltage), (Note 2) 

(Note 2) 

VSS = 24V to 26V, 
Output Common = Vss 



VOH = V S S " ?V 

vol = v S s- 14V 

VOH = Vss -~> 
VOL = V SS - 14 

VOH = V SS - 7V 

vol = v S s- i4V 

V S S = 24V 
VOH = V S s - 2 
VQL= V DD +2 



MIN 



24 



dc 

vss-1 

VDD 



vss-1 

VDD 



vss-i 

VDD 

1 



10 



15 



500 

1 



TYP 



50 or 60 
V S S 
VDD 



VSS 
VDD 



VSS 
VDD 



MAX 



26 
26 



10k 

VSS 

VDD+2 

10 

VSS 
VSS-5 

10 

vss 

VSS-6 
8 

26 
26 



10 



10 



10 



UNITS 



V 
V 

mA 

mA 

Hz 

V 

V 

yA 

V 
V 

/lA 

V 
V 

V 

V 

V 



mA 
MA 

mA 

AlA 

mA 
MA 

MA 
MA 



Note 1: Segment Output Current must be [im 

at25°C. 

Note 2: Power fail detect voltage is 0.25V or 

above the voltage at which data stored in the ti 



ted to 6 mA maximum by user; power dissipation must be limited to 900 mW at 70° C and 1 .2W 

more above the hold count voltage. The power fail latch trips into power fail mode at least 0.25V 
ne latch is lost. 



Ol 
00 
00 



1-51 



functional description 



A block diagram of the MM5384 digital clock radio 
circuit is shown in Figure 1. The various display modes 
provided by this clock are listed in Table I. The 
functions of the setting controls are listed in Table II. 
Figure 2 is a connection diagram. The following dis- 
cussions are based on Figure 7. 

50 or 60 Hz Input: A shaping circuit (Figure 3) is pro- 
vided to square the 50 or 60 Hz input. This circuit 
allows use of a filtered sinewave input. The circuit is a 
Schmitt trigger that is designed to provide about 6V of 
hysteresis. A simple RC filter such as shown in Figure 5, 
is recommended in order to remove possible line-voltage 
transients that could either cause the clock to gain time 
or damage the device. The shaper output drives a counter 
chain which performs the timekeeping function. 

50 or 60 Hz Select Inputs: A programmable prescale 
counter divides the input line frequency by either 
50 or 60 to obtain a 1 Hz time base. This counter is 
programmed to divide by 60 simply by leaving 50/60 Hz 
select unconnected; pull-down to Vqd is provided by an 
internal depletion device. Operation at 50 Hz is pro- 
grammed by connecting 50/60 Hz select to Vgs- 

Display Mode Select Inputs: In the absence of any of 
these three inputs, the display drivers present time-of- 
day information to the appropriate display digits. Inter- 
nal pull-down depletion devices allow use of simple 
SPST switches to select the display mode. If more than 
one mode is selected, the priorities are as noted in 
Table I. Alternate display modes are selected by applying 
Vgs to the appropriate pin. As shown in Figure 1 the 
code converters receive time, seconds, alarm and sleep 
information from appropriate points in the clock 
circuitry. The display mode select inputs control the 
gating of the desired data to the code converter inputs 
and ultimately (via output drivers) to the display digits. 

Time Setting Inputs: Both fast and slow setting inputs 
are provided. These inputs are applied either singly or in 
combination to obtain the control functions listed in 
Table II Again, internal pull-down depletion devices are 
provided; application of Vgs to these pins affects the 
control functions. Note that the control functions pro- 
per are dependent on the selected display mode. For 
example, a hold-time control function is obtained by 
selecting seconds display and actuating the slow set 
input. As another example, the clock time may be reset 
to 12:00:00 AM, by selecting seconds display and actua- 
ting both slow and fast set inputs. 

Blanking Control Inputs: Connecting this Schmitt 
Trigger input to Vqd Places all display drivers in a non- 
conducting, high-impedance state, thereby inhibiting the 
display. See Figures 3 and 4. Conversely Vgg applied to 
this input enables the display. This input does not have 
internal pull-down device. 

Output Common Source Connection: All display output 
drivers are open-drain devices with all sources common 



(Figure 4). Common source pin should be connected 
to Vss- 

12 or 24-Hour Select Input: By leaving this pin uncon- 
nected, the outputs for the most-significant display digit 
(10's of hours) are programmed to provide a 12-hour 
display format. An internal pull-down depletion device 
is again provided. Connecting this pin to VgS programs 
the 24-hour display format. See Figure 6 for 24-hour 
application. 

Power Fail Indication: If the power to the integrated 
circuit drops, indicating a momentary ac power failure 
and possible loss of clock, the AM or PM indicator will 
flash at 1 Hz rate. A fast or slow set input resets an inter- 
nal power failure latch and returns the display to nor- 
mal. 

Alarm Operation and Output: The alarm comparator 
(Figure V senses coincidence between the alarm count- 
ers (the alarm setting) and the time counters (real 
time). The comparator output is used to set a latch in 
the alarm and sleep circuits. The latch output enables 
the alarm output driver (Figure 4), the MM5384 output 
that is used to control the external alarm sound genera- 
tor. The alarm latch remains set for 59 minutes, during 
which the alarm will therefore sound if the latch output 
is not temporarily inhibited by another latch set by the 
snooze alarm input or reset by the alarm off input. 

Sno -,' e Alarm Input: Momentarily connecting snooze to 
Vgs inhibits the alarm output for between 8 and 9 
minutes, after which the alarm will again be sounded. 
This input is pulled-down to VQD D y an internal deple- 
tion device. The snooze alarm feature may be repeatedly 
used during the 59 minutes in which the alarm latch 
remains set. 

Alarm Off Input : Momentarily connecting alarm off to 
Vgs resets the alarm latch and thereby silences the 
alarm. This input is also returned to SlQD bv an i nternal 
depletion device. The momentary alarm off input also 
readies the alarm latch for the next comparator output, 
and the alarm will automatically sound again in 24 hours 
(or at a new alarm setting). If it is desired to silence the 
alarm for a day or more, the alarm off input should 
remain at VsS- 

Sleep Timer and Output: The sleep output at pin 14 can 
be used to turn off a radio after a desired time interval 
of up to 59 minutes. The time interval is chosen by 
selecting the sleep display mode. (Table I) and setting 
the desired time interval (Table II). This automatically 
results in a current-source output via pin 14, which can 
be used to turn on a radio (or other appliance). When 
the sleep counter, which counts downwards, reaches 00 
minutes, a latch is reset and the sleep output current 
drive is removed, thereby turning off the radio. This 
turn-off may also be manually controlled (at any time in 
the countdown) by a momentary Vss connection to the 
Snooze input. The output circuitry is the same as the 
other outputs (Figure 4). 



1-52 



functional description (Continu 



ed) 



2 

2 
w 

00 



d 



50/60 HZ 
INPUT OR 
BLANKING " 
INPUT 



L0WV TH 




50/60 Hz 

_ output or 
"blanking 

SIGNAL 



HIGHV TH * 



FIGURE 3. 50/60 or Blanking Input Shaping Circuits 



•OUTPUT COMMON SOURCE BUS (PIN 18 



Q (DATA) 




OUTPUT 
(OPEN DRAIN) 



FROMALARM/SLEI 
COMPARATORS 



«SS 

Ep — in 

RS I J 



S 



1 



FIGURE 4a. Segment Outputs 



FIGURE 4b. Alarm and Sleep Outputs 



TABLE I. MM5384 Display Modes 



•SELECTED 
DISPLAY MODE 


DIGIT NO. 1 


DIGIT NO. 2 


DIGIT NO. 3 


DIGIT NO. 4 


Time Display 


10's of Hours & AM/PM 


Hours 


10's of Minutes 


Minutes 


Seconds Display 


Blanked 


Minutes 


10's of Seconds 


Seconds 


Alarm Display 


10'sof Hours & AM/PM 


Hours 


10's of Minutes 


Minutes 


Sleep Display 


Blanked 


Blanked 


10's of Minutes 


Minutes 



*lf more than one display mode input is applied, the display priorities are in the order of Sleep (over- 
rides all others). Alarm, Seconds, Time (no other mode selected). 



1-53 



00 
CO 

in 

5 



functional description (Continued) 



TABLE II. MM5384 Setting Control Functions 



SELECTED 
DISPLAY MODE 


CONTROL 
INPUT 


CONTROL FUNCTION 


"Time 


Slow 


Minutes Advance at 2 Hz Rate 




Fast 


Minutes Advance at 60 Hz Rate 




Both 


Minutes Advance at 60 Hz Rate 


Alarm 


Slow 


Alarm Minutes Advance at 2 Hz Rate 




Fast 


Alarm Minutes Advance at 60 Hz Rate 




Both 


Alarm Resets to 12:00 AM (12-hour format) 




Both 


Alarm Resets to 00:00 (24-hour format) 


Seconds 


Slow 


Input to Entire Time Counter is Inhibited (Ho.d) 




Fast 


Seconds and 10's of Seconds Reset to Zero Without 
a Carry to Minutes 




Both 


Time Resets to 12:00:00 AM (12-hour format) 




Both 


Time Resets to 00.00:00 (24-hour format) 


Sleep 


Slow 


Substracts Count at 2 Hz 




Fast 


Substracts Count at 60 Hz 




Both 


Substracts Count at 60 Hz 



*When setting time sleep minutes will decrement at rate of time counter, until the 
sleep counter reaches 00 minutes (sleep counter will not recycle). 



T 



— w— 



L_ l_ L_ L L_ L_ L 

o\ ol o\ ol a\ ol a\ 



50/60 Hz 12/24 HR SLOW FAST ALARM SECONDS SLEEP ALARM SNOOZE 



SELECT SELECT 

V S S 
OUTPUT COMMON SOURCE 



tQ'SOFHOUFIS 



SET DISPLAY DISPLAY DISPLAY OFF 



10'S OF MINUTES 




3 



-M- 



1 



-K- 



i i i 



i i n i r 

Wk 



f a&d h g e d a f a b u 
I I I I I I I I I I I 



l 



n<=v, n^ 






COMMON CATHODE 





6 

»00 



LFD DISPLAY 



__220»F 

i i j 



FIGURE 5. A Schematic Diagram of a General Purpose Alarm Clock 
(12-Hour Model using the MM5384 and a 3 1/2-Digit LED Display 



1-54 



functional description (Cominu 



ed) 



M 



-i h 




2 
w 

00 



v Switch A must be ganged with 

Sleep display switch as shown. 



lOHRb&c SLEEP 

DISPLAY 



FIGURE 6. 24-Hour Operation: 10's of Hours Digit Connections 



1-55 



in <o 

00 0) 
CO CO 

in in 
22 
22 




Clocks 



MM5385. MM5386. MM5396, MM5397 digital alarm clocks 



general description 

The MM5385, MM5386, MM5396 and MM5397 digital 
alarm clocks are monolithic MOS integrated circuits 
utilizing P-channel low-threshold, enhancement mode 
and ion-implanted depletion mode devices. MM5385 or 
MM5396 and MWI5386 or MM5397 have display formats 
of 12 hours and 24 hours respectively, with 24-hour 
alarm display capability. They provide all the logic 
required to build several types of clocks and timers. 
Four display modes (time, seconds, alarm and sleep) 
are provided to optimize circuit utility. The circuit 
interfaces directly with 7-segment light emitting diodes 
and requires two power supplies. The timekeeping 
function operates from either a 50 or 60 Hz input. 
MM5385 or MM5396 displays 12 hours with colon 
flashing at a one second rate and a PM indication. 
MM5386 or MM5397 displays 24 hours with leading 
zero blanking. Outputs consist of display drives, sleep 
(e.g., timed radio turn off), and alarm enable. Power 
failure indication is provided to inform the user that 
incorrect time is being displayed. The power failure 
indication consists of flashing of all the "ON" digits at 
a 1 Hz rate. Setting the time cancels this indication. 
The device operates over a power supply range of 
18-26V and LED supply voltage of 4-7 V. 



The MM5396 and MM5397 are reverse lead-bend versions 
(mirror image) of the MM5385, MM5386 (respectively) 
ideally suited to facilitate PC board layouts when 
designing an "L" shaped clock "module" (vertical 
display, horizontal component board); the MM5385, 
MM5386 are better suited for applications where the 
display and IC are mounted on a PC board in the same 
plane. All four versions are supplied in a 40-lead dual-in- 
line package. 



features 

■ 50 or 60 Hz operation 

■ Low power dissipation 

■ PM outputs in 12-hour format with a colon flashing 
at a one second rate ((MM5385 and MM5396 only) 

■ Leading zero blanking 

■ 24-hour alarm setting 

■ All counters are resettable 

■ Fast and slow set controls 

■ Power failure indication 

■ Blanking/brightness control capability 

■ Direct interface to light emitting diode (LED) with 
forward current of 3—15 mA 

■ Individual drivers for each segment of each digit 

■ 9-minute snooze alarm 

■ Presettable 59-minute sleep timer 

■ Radio frequency interference eliminating slow up 
circuitry at the outputs 

■ Available in standard (MM5385, MM5386) or reverse 
lead-bend version (MM5396, MM5397) 

applications 

■ Alarm clocks 

■ Desk clocks 

■ Clock radios 

■ Stopwatches 

■ Industrial clocks 

■ Portable clocks 

■ Photography timers 

■ Industrial timers 

■ Appliance timers 

■ Sequential controllers 



block diagram 



u 



TIME 
SECONDS 
COUNTER 



ALARM OFF O— 



ALARM & 

SLEEP 
CIRCUITS 



SLEEP 

DOWN 

COUNTER 



TIME 
MINUTES 
COUNTER 



TIME 
HOURS 
COUNTER 



LiL) 

| SECONDS ^) 



ALARM COMPARATOR 



ALARM 
MINUTES 
COUNTER 



O 



ALARM 
HOURS 
COUNTER 



rsj^ ) 



C00E 

CON- . 

VERTERS 

AN0 
OUTPUT 
DRIVERS 



3138) 
H4D) 
Z(39) 
3(37) 
5( 36 ) 
6(35L 



TOIO'S 
0FMINS 
DIGIT 



(15—21) *^ 



Note. MM5396, MM5397 pin connections shown in parenthesis (xx). 



FIGURE 1 



1-56 



absolute maximum ratings 

Voltage at Any Pin 

Voltage at Any Output Pin 

Operating Temperature 

Storage Temperature 

Power Dissipation 

Lead Temperature (Soldering, 10 seconds) 



V S S + 0.3to V S S-28V 

V S s + 0.3to V SS -7.5V 

-25°C to +70°C 

-65°Cto+150°C 

1W 

300° C 



electrical characteristics 

Ta within operating range, Vss = 18V to 26V, Vqq = 0V, unless otherwise specified. 



PARAMETER 



Power Supply Voltage (Vss) 

Power Supply Current 

50/60 Hz Input Frequency Voltage 
Logical High Level 
Logical Low Level 

All Other Input Voltages 
Except Sleep/Seconds Display 

Logical High Level 

Logical Low Level 

Power Failure Detect Voltage 
Output Currents 



All Segment Drivers 
Logical High Level 
Logical Low Level 

Alarm and Sleep Outputs 
Logical High Level 
Logical Low Level 

LED Reference Output 



Logical High Level 
Logical Low Level 



CONDITIONS 



Output Driving Display 
Functional Clock 

No Output Loads, VgS = 26V 



(Note 2) 



Internal Depletion 

Device to Vqd 

(Vss Voltage) (Note 1) 

Vss" 18V to 26V, 
VDD = 0V. Current Measured 
in Individual Segment Driver 
with Current in Remaining 
Segment Driver. LED Current 
Control Connected to Vqd 

VOH = V S S - 2 

vol = v S s -6 

VOH = V S S-2V 
VOL= Vdd+2 
LED Current Control 
Connected to Vqq, 
VSS= 18V, All Segment 
Driver Current 
VOH = VSS - 2 

vol = v ss - 6 



MIN 



dc 

vss-1 

VDD 



vss-1 

VDD 



15 



500 



15 



TYP 



50 or 60 



MAX 



26 
26 

5 

10k 

VSS 

VDD + 1 



VSS 
VDD+7 

7.5 



10 



10 



UNITS 



V 
V 

mA 

Hz 
V 
V 



mA 
uA 

"A 
uA 



mA 
MA 



Note 1: The power-fail detect voltage is 0.5V or more above the hold count voltage. The power-fail latch trips into the power-fail mode at least 
0.5V above the voltage at which data stored in the time latch is lost. 

Note 2: Sleep/seconds display (pin 11 on MM5385 and MM5386, pin 30 on MM5396 and MM5397I. Connect pin to V ss for Sleep display. 
Connect pin to Vqd for Seconds display. Leave pin open for normal time display. 



1-57 



functional description 

A block diagram of the MM5385, MM5386, MM5396 
and MM5397 digital alarm clock is shown in Figure 1 . 
The various display/setting modes are listed in Table I 
and Table II shows the setting control functions. The 
following description is based on Figure 1 ; for simplifi- 
cation, pin numbers in the text are shown only for 
the MM5385 and MM5386, but pin connections for the 
MM5396 and MM5397 may be cross-referenced from the 
diagrams in Figure 2. 

50 or 60 Hz Input (pin 8): A shaping circuit (Figure 3) 
is provided to square the 50 or 60 Hz input. This circuit 
allows use of a filtered sinewave input. The circuit is a 
Schmitt Trigger that is designed to provide about 6V of 
hysteresis. A simple RC filter, such as shown in Figure 7 , 
should be used to remove possible line-voltage tran- 
sients that could either cause the clock to gain time or 
damage the device. The input should swing between 
Vss and V DD- The shaper output drives a counter 
chain which performs the timekeeping function. 

50 or 60 Hz Select Input (pin 7): A programmable 
prescale counter divides the input line frequency by 
either 50 or 60 to obtain a 1 pps time base. This counter 
is programmed to divide by 60 simply by leaving pin 7 
unconnected; pull-down to Vqq is provided by an 
internal depletion load. Operation at 50 Hz is pro- 
grammed by connecting pin 7 to VsS- 

Display Mode Select Inputs (pins 11 and 17): In the 

absence of any of these two inputs (i.e., pin open), 
the display drivers present time-of-day information to 
the appropriate display digits. Snooze/alarm display 
input has an internal pull-down depletion load to Vqd- 
Sleep/seconds display input has an internal voltage 
control which allows this input to assume three input 
states. The sleep time can be displayed by connecting 
pin 1 1 to Vss and seconds can be displayed by con- 
necting pin 11 to Vqd. and if Pin 11 is left open, 
normal time is displayed. If more than one mode is 
selected, the priorities are as noted in Table I. As shown 



in Figure 1 the code converters receive time, alarm and 
sleep information from appropriate points in the clock 
circuitry. The display mode select inputs control the 
gating of the desired data to the code converter inputs 
and ultimately (via output drivers) to the display digits. 

Time Setting Inputs (pins 9 and 10): Both fast and slow 
setting inputs are provided. These inputs are applied either 
singly or in combination to obtain the control functions 
listed in Table II. Again, internal depletion loads to VrjD 
are provided, application of Vss to these pins affects 
the control functions. Note that the control functions 
proper are dependent on the selected display mode. 
For example, a hold-time control function is obtained 
by selecting seconds display and actuating the slow set 
input. As another example, the clock time may be reset 
to 12:00:00 AM (midnight), in the 12-hour format 
(0:00:00 in the 24-hour format), by selecting seconds 
display and actuating both slow and fast set inputs. 

Alarm Operation and Output (pin 16); The alarm com- 
parator (Figure 1) senses coincidence between the alarm 
counters (the alarm setting) and the time counters 
(real time). The comparator output is used to set a latch 
in the alarm and sleep circuits. The latch output enables 
the open drain alarm output driver to control the 
external alarm sound generator. The alarm latch remains 
set for 59 minutes, during which the alarm will therefore 
sound if the latch output is not temporarily inhibited 
by another latch set by the snooze alarm input (pin 17) 
or reset by the alarm "OFF" input (pin 15). 

Snooze/Alarm Display (pin 17): Momentarily connecting 
pin 17 to Vss inhibits the alarm output for between 
8 and 9 minutes after which the alarm will again be 
sounded and display alarm time. This input is pulled- 
down to Vdd by an internal depletion load. The snooze 
alarm feature may be repeatedly used during the 59 
minutes in which the alarm latch remains are set; con- 
necting pin 1 7 to Vss displays alarm time. 



10s HR 


10:; HR b4 


10s HR 


10:; HR rt 


10sHRa4 


- PM 


10s HR d4 


COLON 


10sHRe4 


— COLON 


10sHRg4 


1 Hz 




50/60 Hz SELECT 




50/50 Hz INPUT 




FAST SET 




SLOW SET 


SL 


EP/SEC DISPLAY 



SLEEP OUTPUT - 

ALARM "0FF"- 
ALARM OUTPUT- 
SNOOZE AND ALARM DISPLAY- 
LEO CUR CONTROL- 
LED REF OUTPUT - 
MINd- 



MM53B5 - 12 HOUR 
MM5386 -24 HOUR 



- HR 13 

- HRg3 

- HRa3 

- HRb3 

- HRrJ3 
-HRc3 
-HRe3 
-lOMINSfZ 
-1QMINSg2 
-1DMINSa2 
-IQMINSdZ 
-10MINSb2 
-10MINSe2 
-10MINSc2 
-MIN11 
-MINgl 

- MINal 

- MINbl 

- MINe! 
-MINdl 



TOP VIEW 

Order Number MM5385N or MM5386N 
See Package 24 



HR 13- 
HR g3— 
HF 83- 
HR b3— 
HR d3— 
HR 03- 
HR e3— 
DMINS12— 
0MINSg2- 
DMINSa2— 
QMINSd2- 
0MINSb2- 
DMINSe2- 
0MINSc2- 
MIN11- 
mn gl- 
MINal- 
MINbl- 
MIMel- 
VUNdl- 



MM5396 - 
MM5397 - 



12HR 


24 HR 


10s HR 


IOsHR 


10s HR 


10s HR 


^ 


10sHRa4 


— 


10s HR d4 


-^ 


10sHRe4 


* 


10s Hfl g4 



-PM 

-COLON 

-COLON 

'-} Hz 

-50/60 Hz SELECT 

-50/60 Hz INPUT 

-FAST SET 

-SLOW SET 

-SLEEP/SEC DISPLAY 
I 

-Vdd 
-vss 

-SLEEP OUTPUT 

|-ALARM"0FF" 

-ALARM OUTPUT 

—SNOOZE AND ALARM DISPLAY 

—LED CUR CONTROL 

-LED REF OUTPUT 

I 

— MINcI 



TOP VIEW 

Order Number MM5396N or MM5397N 



See Package 24 



1-58 



functional description (continued) 

Alarm "OFF" Input (pin 15): Momentarily connecting 
pin 15 to Vss resets the alarm latch and thereby silences 
the alarm. This input is also returned to Vqd d Y a n 
internal depletion load. The momentary alarm "OFF" 
input also readies the alarm latch for the next comparator 
output, and the alarm will automatically sound again in 
24 hours (or at a new alarm setting). If it is desired to 
silence the alarm for a day or more, the alarm "OFF" 
input should remain at VsS- 




FIGURE 3. 50/60 Hz Input Shaping Circuits 

Sleep Timer and Output (pin 14): The sleep output at 
pin 14 can be used to turn off a radio after a desired 
time interval of up to 59 minutes. The time interval is 
chosen by selecting the sle;ep display mode (Table I) 
and setting the desired time interval (Table II). This 
automatically results in a current-source output via pin 



14, which can be used to turn on a radio (or other 
appliance). When the sleep counter, which counts down- 
wards, reaches 00 minutes, a latch is reset and the sleep 
output drive is removed, thereby turning off the radio. 
This turn off may also be manually controlled (at any 
time in the countdown) by a momentary Vgs connec- 
tion to the snooze input (pin 17). 

Segment Outputs (pins 1-6 and 20-40): All segment 
outputs are open drain devices with all sources con- 
nected to Vgg. Each segment output may source direct 
current of 1 5 mA at 2V on the output device. Figure 5(b) 
shows the output resistance (Rqn) of segment driver 
with respect to VqD- 

Power Failure Indications: Power failure indication is 
shown by the flashing of all "ON" digits at 1 Hz rate. 
A fast or slow set input resets an internal power failure 
latch and returns the display to normal. The power 
failure latch trips into the power failure mode prior 
to the loss of data stored in the time latches. When 
powered up, alarm and sleep outputs will be in the 
"OFF" state. In order to assure guaranteed power 
fail indication, power supply rise time should not exceed 
10 V/ms. 

LED CURRENT CONTROL INPUT AND REFERENCE 
OUTPUT (PINS 19 AND 18) 

Pin 18 controls the gate voltage at all the display outputs 
and the reference device. The output drivers can be 
disabled by connecting pin 18 to VgS- This wire-OR 
capability allows the display to be used for other func- 
tions (e.g., temperature, radio frequency wavelength). 



TABLE I. MM5385, MM5386, MM5396, MM5397 Display Modes 



•SELECTED 
DISPLAY MODE 


DIGIT NO. 1 


DIGIT NO. 2 


DIGIT NO. 3 


DIGIT NO. 4 


- 


Time Display 


10'sof Hours & AM/PM 


Hours 


10's of Minutes 


Minutes 


Seconds Display 


Blanked 


Minutes 


10's of Seconds 


Seconds 




Alarm Display 


10'sof Hours & AM/PM 


Hours 


10's of Minutes 


Minutes 




Sleep Display 


Blanked 


Blanked 


10's of Minutes 


Minutes 





*lf more than one display mode input is applied, the display priorities are in the order of Sleep (overrides 
all others), Alarm, Seconds, Time (no other mode selected). 

TABLE II. MM5385, MM5386, MM5396, MM5397 Setting Control Functions 



SELECTED 
DISPLAY MODE 


CONTROL 
INPUT 


CONTROL FUNCTION 


'Time 


Slow 


Minutes Advance at 2 Hz Rate 




Fast 


Minutes Advance at 60 Hz Rate 




Both 


Minutes Advance at 60 Hz Rate 


Alarm 


Slow 


Alarm Minutes Advance at 2 Hz Rate 




Fast 


Alarm Minutes Advance at 60 Hz Rate 




Both 


Alarm Resets to 12:00 AM (Midnight) (MM5385, MM5396) 




Both 


Alarm Resets to 0:00 (MM5386, MM5397) 


Seconds 


Slow 


Input to Entire Time Counter is Inhibited (Hold) 




Fast 


Seconds and 10's of Seconds Reset to Zero Without 
a Carry to Minutes 




Both 


Time Resets to 12:00:00 AM (Midnight) (MM5385, MM5396, 




Both 


Time Resets to 0:00:00 (MM5386, MM5397) 


Sleep 


Slow 


Subtracts Count at 2 Hz 




Fast 


Subtracts Count at 60 Hz 




Both 


Subtracts Count at 60 Hz 



*When setting time sleep minutes will decrement at rate of time counter, until the sleep 
counter reaches 00 minutes (sleep counter will not recycle). 



1-59 



functional description (Continued) 

The output current can be controlled two ways: 
1) driving the output in saturated mode; 2) driving 
the output in linear mode. (Refer to Figures 4 and S). 

1) The reference device (pins 18 and 191 is connected 
as a diode, and an external resistor is used to set the 
desired current in this diode (see Figure 4). The seg- 
ment drivers of all digits are connected as current 
mirrors. The drain voltage V1 of the segment drivers 
is selected such that these devices operate in saturation 
mode. Since the drain current variation in saturation 
mode operation of the MOS device is relatively 
constant, the segment drive current does not vary 
significantly, even though V1 is increased considerably. 
However, as the voltage across the output buffers 
increases, average power dissipation also increases 
linearly. This technique of current control is recom- 
mended to be used only with low current LEDs 
(1-7 mA). 



2) The high current drive requirement of large LED 
displays can be accomplished by operating the segment 
drivers in the linear mode. The circuit for high current 
LED drivers is shown in Figure 5. The reference output 
device is used in series with a reference LED, diode and 
current setting resistor. A high beta PNP transistor 
provides the current drive for all the segments. A refer- 
ence voltage V3 is developed which compensates for 
variations in MOS process parameter and the variations 
in the voltage drop across the LED. The resistor sets the 
current in the reference LED which sets the reference 
voltage V3. This in turn sets the current in the LEDs 
equal to resistor current less the base current of the 
transistor. Variation in second supply voltage does not 
vary the LED currents so long as the PNP transistor is 
kept operating in the linear mode. Full wave rectified 
power supply without any filtering can be used as a 
second supply voltage V2. The LED brightness can be 
varied by using a variable resistor. 



BRIGHTNESS V LE() SUPPLY 
/CONTROL OCORT 

RESISTOR 




OUTPUT 

DRIVER 

OPERATING 

REGION 




FIGURE 4(a). Low Current LED Drive Control Circuit (1-7 mA) 



FIGURE 4(b). Segment Current vs V| 

(Vrjo a* —18V) (Typical Output Characteristics) 



BRIGHTNESS CONTROL RESISTOR 
V LEI ) SUPPLY 




in I >19 



h r4 ?4 



OUTPUT 

DRIVER 

OPERATING 

REGION 



V S S V SS V SS 

FIGURE 5(a). High Current LED Drive Control Circuit (7-15 mA) 




-5 -10 -15 -20 -25 -30 

V D d(V> (REFERENCED TO V S s) 

FIGURE 5(b). R N v « V dd (V DS at -IV) 
(Typical Output Characteristics) 



functional description (continued) 

Figure 6 shows a LED drive circuit which uses a single 
resistor. The resistor controls the total current flowing 
through all the segments. Brightness shall vary depending 
on number of segments that are on at that time. 



Radio Frequency Interference: All display outputs 
include circuitry to slow up the switching transition 
time to minimize radio frequency interference. 



J> 



CURRENT 
LIMITING 
RESISTOR 



O CONTROL O O 



VSS LOGIC 



FIGURE 6. Simple LED Drive Circuit 













































>,. 1 


J i «■■ 






V(N 















22 

U1UI 
WW 
CO 00 
OJW1 

S2 
IS 

WW 

to 00 

^o> 



vdd 



"ss 



V, N IVI 



FIGURE 7. I| N vsV|N (Typical 
Input Depletion Load Characteristics) 




1— I I I I 



ID'S OF HOURS UNIT HOURS ID'S OF MINUTES UNIT MINUTES 

FIGURE 8. General Purpose Alarm Clock Using the MM5385 or MM5396 and LED Display 



1-61 



a 



Clocks 



MM5387AA, MM53108 digital alarm 
general description 

The MM5387AA, MM53108 digital alarm clocks are 
monolithic MOS integrated circuits utilizing P-channel 
low-threshold, enhancement mode and ion-implanted 
depletion mode devices. They provide all the logic 
required to build several types of clocks and timers 
with up to four display modes (time, seconds, alarm 
and sleep) to maximize circuit utility, but are specifi- 
cally intended for clock-radio applications. Both devices 
will directly-drive 7-segment LED displays in either a 
12 hour format (3'/ s digits) with lead-zero blanking, 
AM/PM indication and flashing colon, or 24 hour 
format (4 digits) through hard-wire pin selection; the 
timekeeping function operates from either a 50 or 
60 Hz input, also through pin selection. Outputs consist 
of display drivers, sleep (e.g., timed radio turn-off), and 
alarm enable. A power-fail indication mode is provided 
to inform the user of incorrect time display by flashing 
all "ON" digits at a 1 Hz rate, and is cancelled by 
simply resetting time. The device operates over a supply 
range of 24-26V which does not require regulation. 

The MM53108 is electrically identical to the 
MM5387AA, but with mirror-image pin-out to facilitate 
PC board layout when designing a "module" where the 
LED display and MOS chip are mounted on the same 
side; the MM5387AA is more suited for "L" shaped 
module designs (vertical LED display, horizontal com- 
ponent board). Both devices are supplied in a 40-lead 
dual-in-line package. 



clocks 
features 



12 hour format 



50 or 60 Hz operation 

Single power supply 

12 or 24 hour display format 

AM/PM outputs 

Leading-zero blanking 

24-hour alarm setting 

All counters are resettable 

Fast and slow set controls 

Power failure indication 

Elimination of illegal time display at turn "ON" 

Direct interface to LED displays 

9-minute snooze alarm 

Presettable 59-minute sleep timer 

Available in standard (MM5387AA) or mirror image 

(MM53108) pin-out 



applications 

■ Alarm clocks 

■ Desk clocks 

■ Clock radios 

■ Automobile clocks 

■ Stopwatches 

■ Industrial clocks 



Portable clocks 
Photography timers 
Industrial timers 
Appliance timers 
Sequential controllers 



block diagram 



OUTPUT 23IIBI 

COMMON O 

SOURCE 
12/24 HOUR 3H < 3) 
SELECT 



1 I 







SHAPING 
CIRCUIT 




50 OH ^60 






INPUT 


1 






H<OT HP - 36 I s ' 






t 


1 




SELECT 








PPS 



( TIME 



S 



1 




















L 


TIME 
SECONDS 
COUNTER 


1PPM 


TIME 
MINUTES 
COUNTER 


1PPH 


TIME 
HOURS 

COUNTER 








* 


25(16) 








1 










26(15) 
ALARM OFF O 


+ 




' 


' 


24(W) 


ALARMS, 

SLEEP 
CIRCUITS 




ALARM COMPARATOR 








. " l 1d > 


^f. 


L 


' 




i 


I 


> 
















SLEEP 




ALARM 




ALARM 




COU 


TE 


R 




COU 


TER 




COU 


YTER 



I SECONDS ^) 
| ALAHM \ 



SLEEP DIS O— 



ALARM OIS O— 



SECONDS OIS O— 



39 (2) 

40(1) 
1 (40) 
2(39) 

CODE 

CON- 
VERTERS 

AND 
OUTPUT 
DRIVERS 



At. 



10-15 



(26-31) 
16-22 



\b-U k 

— - — "\ tomin; 

r/ DIGIT 

(19-25) V 



Note. MM53108 pin connections shown in parenthesis 
FIGURE 1 



1-62 



absolute maximum ratings 












Voltage at Any Pin Except Segment Outputs Vss + 0.3 to Vss ~ 30V 










Voltage at Segment Outputs 


VSS + 0.3 to VSS - 15 V 










Operating Temperature 


-25° C to +70°C 










Storage Temperature 


-65°Cto+150°C 










Lead Temperature (Soldering, 10 seconds) 


300° C 










electrical characteristics 












Ta within operating range, Vss =: 24V-26V, Vqq = 0V, unless otherwise specified. 








PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Power Supply Voltage 


Output Driving Display 


24 




26 


V 




Functional Clock 


8 




26 


V 


Power Supply Current 


No Output Loads 












V S S = 8V 






4 


mA 




V S S = 26V 






5 


mA 


50/60 Hz Input 












Frequency Voltage 


VsS= 8V to 26V 


dc 


50 or 60 


10k 


Hz 


Logical High Level 




Vss-1 


vss 


VSS 


V 


Logical Low Level 




V D D 


VDD 


V D D+2 


V 


Input Leakage 








100 


UA 


All Other Input Voltages 












Logical High Level 




vss-1 


vss 


VSS 


V 


Logical Low Level 


Internal Depletion Load to V[)D 


VDD 


VDD 


V S S-6 


V 


Power Failure Detect Voltage 


(Vss Voltage), (Note 2) 


1 




7.5 


V 


Count Operating Voltage 




8 




26 


V 


Hold Count Voltage 




(Note 2) 




26 


V 


Output Current Levels 


Vss = 24V to 26V, 
Output Common = Vss 










10's of Hours (b & c), 10's of Minutes 












(a&d) 












Logical High Level, Source 


V0H = V S S-4V 


16 






mA 


Logical Low Level, Leakage 


vol = v S s -14V 






10 


J"A 


1 Hz Display 












Logical High Level, Source 


V0H = Vss -4 


24 






mA 


Logical Low Level, Leakage 


vol = v S s -H 






10 


A.A 


All Other Displays 












Logical High Level, Source 


V0H = VSS-4V 


8 




(Note 1) 


mA 


Logical Low Level, Leakage 


vol = v S s -14V 






10 


MA 


Alarm and Sleep Outputs 


V S S = 24V 










Logical High , Source 


VOH = V S S - 2 


500 






ma 


Logical Low, Sink 


vol = v ss -2 


1 






MA 


Note 1: Segment output current must be llimite 
at 25° C. 


d to 1 1 mA maximum by user; power diss 


ipation must 


De limited to 


900 mW at 7( 


)°Cand 1.2W 


Note 2: The power-fail detect voltage is 0.5V o 
above the voltage at which data stored in the time 


r more above the hold count voltage. The p 
latch is lost. 


ower-fail late 


trips into po 


wer-fail mode 


at least 0.5V 



1-63 



functional description 



A block diagram of the MM5387AA, MM53108 digital 
clock radio circuit is shown in Figure 1. The various 
display setting modes are listed in Table I, and Table II 
shows the setting control functions. The following 
description is based on Figure 1 and refers to both 
devices as they are electrically identical. 

50 or 60 Hz Input: A shaping circuit (Figure 31 is pro- 
vided to square the 50 or 60 Hz input. This circuit 
allows use of a filtered sinewave input. The circuit is a 
Schmitt trigger that is designed to provide about 6V of 
hysteresis. A simple RC filter such as shown in Figure 7 , 
should be used to remove possible line-voltage tran- 
sients that could either cause the clock to gain time or 
damage the device. The shaper output drives a counter 
chain which performs the timekeeping function. 

50 or 60 Hz Select Input: A programmable prescale 
counter divides the input line frequency by either 
50 or 60 to obtain a 1 Hz time base. This counter is 
programmed to divide by 60 simply by leaving 50/ 
60 Hz select unconnected; pull-down to Vqd is pro- 
vided by an internal depletion load. Operation at 50 Hz 
is programmed by connecting 50/60 Hz select to VsS- 

Display Mode Select Inputs: In the absence of any of 
these three inputs, the display drivers present time-of- 
day information to the appropriate display digits. 
Internal depletion pull-down devices allow use of simple 
SPST switches to select the display mode. If more than 
one mode is selected, the priorities are as noted in 
Table I. Alternate display modes are selected by apply- 
ing Vss to the appropriate pin. As shown in Figure 1 
the code converters receive time, seconds, alarm and 
sleep information from appropriate points in the clock 
circuitry. The display mode select inputs control the 



gating of the desired data to the code converter inputs 
and ultimately (via output drivers) to the display digits. 

Time Setting Inputs: Both fast and slow setting inputs 
are provided. These inputs are applied either singly or 
in combination to obtain the control functions listed in 
Table II. Again, internal depletion pull-down devices 
are provided; application of Vss to these pins affects 
the control functions. Note that the control functions 
proper are dependent on the selected display mode. 
For example, a hold-time control function is obtained 
by selecting seconds display and actuating the slow set 
input. As another example, the clock time may be reset 
to 12:00:00 AM, by selecting seconds display and actu- 
ating both slow and fast set inputs. 

Output Common Source Connection: All display out- 
put drivers are open-drain devices with all sources 
common (Figure 4a). The common source pin should 
be connected to Vgg. 

12 or 24 Hour Select Input: By leaving this pin uncon- 
nected, the outputs for the most-significant display 
digit (10's of hours) are programmed to provide a 
12-hour display format. An internal depletion pull- 
down device is again provided. Connecting this pin to 
Vss programs the 24-hour display format. Segment 
connections for 10's of Hours in 24-hour mode are 
shown in Figure 6. 

Power Fail Indication: If the power to the integrated 
circuit drops, indicating a momentary ac power failure 
and possible loss of clock, all "ON" segments will 
flash at 1 Hz rate. A fast or slow set input resets an 
internal power failure latch and returns the display to 
normal. 



connection diagrams 

Dual-ln-Line Package 



Dual-ln-Line Package 



AM OUTPUT - 

lOHRS-b&e - 

HRS-« - 

HRS - a - 

HRS-n - 

HRS-tj - 

HRS - d - 

HRS - c - 

HRS-e - 

lOMINS-f- 

10MINS-9- 

lOMINS-a&d - 

lOMINS-b- 

10MINS-B - 

10MINS-C - 

MINS-f - 

MINS-g - 

MINS-a . 

MINS-b. 

MINS-e - 



*u 


40 

— PM OUTPUT 
39 

— COLON (1 Hz) 
38 

— 12/24 HR SELECT 
37 

NC 

36 

50/60 Hi SELECT 

35 

50/60 Hz INPUT 

34 

— - FAST SET INPUT 

SLOW SET INPUT 

— SECOND DISPLAY INPUT 


PM OUTPUT 




COLON {1 Hz) 




12/24 HR SELECT 




NC 
50/60 Hz SELECT 




50/60 Hz INPUT 




FAST SET INPUT 




SLOW SET INPUT 




SECOND DISPLAY INPUT 




ALARM DISPLAY INPUT 

SLEEP 0ISPLAY INPUT 


ALARM DISPLAY INPUT 




SLEEP DISPLAY INPUT 




- v SS 

27 SS 

SLEEP OUTPUT 

26 

ALARM "OFF "INPUT 


V D D 

V SS 

SLEEP OUTPUT 




ALARM "OFF "INPUT 




ALARM OUTPUT 

24 

SNOOZE INPUT 


ALARM OUTPUT 




SNOOZE INPUT 




OUTPUT COMMON SOURCE 


OUTPUT COMMON SOURCE 




— MINS-c 
21 

— MINS-d 


MINS-c 




MINS-d 




TOP VIEW 

Order Number MM5387AAN 
See Package 24 

FIGURE 2(a). MM5387AA 



Order Number MM53108N 
See Package 24 

FIGURE 2(b). MM53108 (Mirror Image Pin-Out) 



1-64 



functional description 



(Continued) 



Alarm Operation and Output: The alarm comparator 
(Figure 1) senses coincidence between the alarm count- 
ers (the alarm setting) and the time counters (real time). 
The comparator output is used to set a latch in the 
alarm and sleep circuits. The latch output enables the 
alarm output driver (Figure 4b) which is used to 
control the external alarm sound generator. The alarm 
latch remains set for 59 minutes, during which the alarm 
will therefore sound if the latch output is not tempor- 
arily inhibited by another latch set by the snooze alarm 
input or reset by the alarm "OFF" input. 

Snooze Alarm Input: Momentarily connecting snooze 
to Vss inhibits the alarm output for between 8 and 9 
minutes, after which the alarm will again be sounded. 
This input is pulled-down to Vqd by an internal deple- 
tion device. The snooze alarm feature may be repeatedly 
used during the 59 minutes in which the alarm latch 
remains set. 



Alarm 

"OFF' 



"OFF" Input: Momentarily connecting alarm 
to Vgs resets the alarm latch and thereby 



silences the alarm. This input is also returned to VpD by 
an internal depletion device. The momentary alarm 
"OFF" input also readies the alarm latch for the next 
comparator output, and the alarm will automatically 
sound again in 24 hours (or at a new alarm setting). 
If it is desired to silence the alarm for a day or more, 
the alarm "OFF" input should remain at V$S- 

Sleep Timer and Output: The sleep output can be used 
to turn "OFF" a radio after a desired time interval of up 
to 59 minutes. The time interval is chosen by selecting 
the sleep display mode, (Table I) and setting the desired 
time interval (Table II). This automatically results in a 
current-source output which can be used to turn "ON" a 
radio (or other appliance). When the sleep counter, 
which counts downwards, reaches 00 minutes, a latch 
is reset and the sleep output current drive is removed, 
thereby turning "OFF" the radio. This turn "OFF" 
may also be manually controlled (at any time in the 
countdown) by a momentary Vss connection to the 
Snooze input. The output circuitry is the same as the 
other outputs (Figure 4b). 




* Effectively 



FIGURE 3. BO/60 Hz Input Shaping Circuit 



COMMON SOURCE BUS 



>H 



C 



FROM 
ALARM OR SLEEP >— I 
COMPARATOR 



OUTPUT 
[OPEN DRAIN} 




FIGURE 4(a). Segment Outputs 



FIGURE 4(b). Alarm and Sleep Outputs 



1-65 



functional description (Continued) 



TABLE I. MM5387AA, MM53108 Display Modes 



*SELECTED 
DISPLAY MODE 


DIGIT NO. 1 


DIGIT NO. 2 


DIGIT NO. 3 


DIGIT NO. 4 


Time Displav 


lO'sof Hours & AM/PM 


Hours 


10'sof Minutes 


Minutes 


Seconds Display 


Blanked 


Minutes 


1 0's of Seconds 


Seconds 


Alarm Display 


10'sof Hours & AM/PM 


Hours 


10's of Minutes 


Minutes 


Sleep Display 


Blanked 


Blanked 


10's of Minutes 


Minutes 



* If more than one display mode input is applied, the display priorities are in the order of Sleep (overrides 
all others), Alarm, Seconds, Time (no other mode selected). 



TABLE II. MM5387AA, MM53108 Setting Control Functions 



SELECTED 
DISPLAY MODE 


CONTROL 
INPUT 


CONTROL FUNCTION 


*Time 


Slow 


Minutes Advance at 2 Hz Rate 






Fast 


Minutes Advance at 60 Hz Rate 






Both 


Minutes Advance at 60 Hz Rate 




Alarm 


Slow 


Alarm Minutes Advance at 2 Hz Rate 






Fast 


Alarm Minutes Advance at 60 Hz Rate 






Both 


Alarm Resets to 12:00 AM (Midnight) (12-Hour Format) 




Both 


Alarm Resets to 00:00 (24-Hour Format) 




Seconds 


Slow 


Input to Entire Time Counter is Inhibited (Hold) 






Fast 


Seconds and 10's of Seconds Reset to Zero Without 
a Carry to Minutes 






Both 


Time Resets to 12:00:00 AM (Midnight) (12-Hour Fo 


mat) 




Both 


Time Resets to 00:00:00 (24-Hour Format) 




Sleep 


Slow 


Subtracts Count at 2 Hz 






Fast 


Subtracts Count at 60 Hz 






Both 


Subtracts Count at 60 Hz 





*When setting time sleep minutes will decrement at rate of time counter, until the sleep 
counter reaches 00 minutes (steep counter will not recycle). 





vss = 

VD0 


24V 








1 


= ' 




















6 

5 
































3 
2 
































1 














SLEEP 
DISPLAY 



OUTPUT (DRAIN) VOLTAGE BELOW Vgs 



Switch A must be ganged with Sleep display as shown. 



FIGURE 5. Typical Output Current 
Characteristics of MM5387AA, MM53108 



FIGURE 6. 24-Hour Operation: 
10's of Hours Digit Connections 



1 66 



typical applications 

Figure 7 is a schematic diagram of a general purpose alarm clock circuit (12-hour mode) using the MM5387AA or 
MM53108 and a 3 1/2-digit LED display. 



X 



1 




T T ? r ? r ? r ? r ? r ? r ? r 



S0.'60Hz 12/24 HR SLOW FAST ALARM SECONDS SLEEP ALARM SNOOZE 

SELECT SELECT SET SET DISPLAY QISPLAY DISPLAY OFF 



OUTPUT COMMON SOURCE 



V DU 10'SOF HOURS 



10'S OF MINUTES 



1" 



AM b & c d e t a b 9 t e 1 a&d fa 9 e A e I a b 8 

I I I I I I I I I I ! I I I I I I I I I 



1 



b: ' :l b// 6 //f b ■' 

o u'U J U>L 

'■■:■ ;;■ ■/ 6 /■ ..., 

U / \r~~~]\ j C0L0N / j [ ■ ) < ; 



o • o- 



COMMON CATHODE 



> 



I _" j 




•<r~ 



i i j 



1-67 




Clocks 



MM5402. MM5405 digital alarm clocks 
general description 



The MM5402, MM5405 digital alarm clocks are mono- 
lithic MOS integrated circuits utilizing N-channel 
low-threshold, enhancement mode and ion-implanted 
depletion mode devices. They provide all the logic 
required to build several types of clocks and timers 
with up to four display modes (time, seconds, alarm 
and sleep) to maximize circuit utility, but are specifi- 
cally intended for clock-radio applications. Both devices 
will directly-drive 7-segment LED displays in either a 
12-hour format (3 1/2 digits) with lead-zero blanking, 
AWI/PM indication and flashing colon, or 24-hour 
format (4 digits) through hard-wire pin selection; the 
timekeeping function operates from either a 50 or 
60 Hz input, also through pin selection. Outputs consist 
of display drivers, sleep (e.g., timed radio turn-off), and 
alarm enable. A power-fail indication mode is provided 
to inform the user of incorrect time display by flashing 
all "ON" digits at a 1 Hz rate, and is cancelled by 
simply resetting time. The device operates over a supply 
range of 7V — 1 1 V which does not require regulation. 

The MM5405 is electrically identical to the MM5402, 
but with mirror-image pin-out to facilitate PC board 
layout when designing a "module" where the LED 
display and MOS chip are mounted on the same side; 
the MM5402 is more suited for "L" shaped module 
designs (vertical LED display, horizontal component 
board). Both devices are supplied in a 40-lead dual-in- 
line package. 



12 hour format 



features 

■ 50 or 60 Hz operation 

■ Single power supply 

■ 12 or 24 hour display format 

■ AM/PM outputs 

■ Leading-zero blanking 

■ 24-hour alarm setting 

■ All counters are resettable 

■ Fast and slow set controls 

■ Power failure indication 

■ Elimination of illegal time display at turn "ON" 

■ Direct interface to LED displays 

■ 9-minute snooze alarm 

■ Presettable 59-minute sleep timer 

■ Available in standard (MM5402) or mirror-image 
(MM5405) pin-out 



applications 

■ Alarm clocks 

■ Desk clocks 

■ Clock radios 

■ Automobile clocks 

■ Stopwatches 

■ Industrial clocks 



Portable clocks 
Photography timers 
Industrial timers 
Appliance timers 
Sequential controllers 



block diagram 



OUTPUT Qi; 



COMMON 
12/24 HOUR ~ 38 ' 3 > 



50/60 HZ 35(6) 




SHAPING 
CIRCUIT 




: 50 OR ^60 




INPUT 


' 




PPS 


50/60 HZ 36(5) 






T 


SELECT 






I 



1 




















L 


TIME 
SECONDS 
COUNTER 


1 PPM 


TIME 
MINUTES 
COUNTER 


1 PPH 


TIME 
HOURS 
COUNTER 








* 


- 25(16) 








' 










26 (75} 
ALARM OFF O 


+ 




' 


' 


24(171 


ALARM & 

SLEEP 
CIRCUITS 




ALARM COMPARATOR 








27(14) 


\ 


L 






, 


. 


. 
















SLEEP 




ALARM 




ALARM 




COU 


m 


R 




COU 


TEB 


^ 


COU 


mfi 



SLEEP DIS O— 



SECONDS DIS O— 



^> 



s£> 



J> 



I ALARM 



QEUE^) 



Li 



39(2) 
10(1) 



2(39) 

C0OE 

CON- 
VERTERS 

AND 
OUTPUT 
DRIVEHS 



TD ID'S 

\ OF HRS 

DIGIT 



3-9 



(32-30) ' 

0-15 



(26-31) 

16-22 
(19-25) * 



TO ID'S 
0FMINS 
DIGIT 



Note. MM5405 pin connections shown in parenthesis. 



-68 



absolute maximum ratings (Noteu 



Voltage at Any Pin 
Operating Temperature 
Storage Temperature 



v SSto V SS +12V 

25 C to +70 C 

-65° C to + 150C 



Lead Temperature (Solder 
Segment Output Current 



^g, 10 seconds) 



300"C 
Note 1 



electrical Characteristics T A within operating range, V DD = 7V to 1 1 V, V SS = OV, unless otherwise specified. 



PARAMETER 



Power Supply Voltage 
Power Supply Current 



50/60 Hz Input 
Frequency 

Logical Low Level 

Logical High Level 
Input Leakage 

All Other Input Voltages 

Logical Low Level 

Logical High Level 
Power Failure Detect Voltage 
Count Operating Voltage 
Hold Count Voltage 
Alarm and Sleep Outputs 

Logical High, Source 

Logical Low, Sink 

Output Current Levels 

Common Anode 

10'sof Hours (b & c), 10's of Minutes 
(a&d) 

Logical High Level, Leakage 

Logical Low Level, Sink 

1 Hz Display 

Logical High Level, Leakage 
Logical Low Level, Sink 

All Other Segment Displays 
Logical High Level, Leakage 
Logical Low Level, Sink 

Output Current Levels 

Common Cathode 

10's of Hours (b & c), 10's of Minutes 

(a&d) 

Logical High Level, Source 
Logical Low Level, Leakage 

1 Hz Display 

Logical High Level, Source 
Logical Low Level, Leakage 

All Other Segment Displays 
Logical High Level, Source 
Logical Low Level, Leakage 



CONDITIONS 



Output Driving Display 
Functional Clock 

No Output Loads 
V DD = 7V 
VDD= hv 

VDD = 7Vto 11V 



Internal Depletion Load to Vqd 
(Vdd Voltage), (Note 2) 



V DD = 11V 
VOH = V S s + 2 
VOL = Vss + 2 

V DD = 9V to 11V 
Output Common = Vgg 



(Figure 5a) 



VOH = V D D 
VOL = V S S + 2V 

VOH = V DD 
VOL = V S s + 2V 

VOH = Vqd 
VOL= V S S + 2V 

Vqd = 9V to 11V 
Output Common = Vss "* 

(Figure 5b) 



VOH = V S S + 15V 

vol = v S s 

VOH = V S S + 15V 

vol = v S s 

VOH = Vss + 1.5V 
VOL= V S S 



dc 

vss 

VDD-3 



VSS 

VDD-3 

1 

7 
(Note 2) 



50 or 60 
VSS 
VDD 



VSS 
VDD 



10k 

Vss+0.5 

VDD 

100 

Vss+0.5 

VDD 

5 

11 
11 



V 
V 

mA 
mA 

Hz 
V 
V 

MA 

V 
V 
V 
V 
V 

MA 
mA 



10 


uA 




mA 


10 


uA 




mA 


10 


uA 




mA 


(Note 1) 






mA 


10 


u/\ 




mA 


10 


WA 




mA 


10 


uA 



NoteJ: Segment output current must be limited to IS mA maximum by user; power dissipation must be limited to 900 mW at 70°C and 1 .2W 
at 25 C. 

Note 2: The power-fail detect voltage is 0.25V or more above the hold count voltage. The power-fail latch trips into power-fail mode at least 
0.25V above the voltage at which data stored in the time latch is lost. 

Note 3: Power supply voltage should not exceed a maximum voltage of 1 2V under any circumstances, such as during plug in, power up display 
"ON'V'OFF", or power supply ripple. Doing so runs the risk of permanently damaging the device. 



U1 

o 



1-69 



functional description 



A block diagram of the MM5402, MM5405 digital 
clock radio circuit is shown in Figure 1. The various 
display setting modes are listed in Table I, and Table II 
shows the setting control functions. The following 
description is based on Figure 1 and refers to both 
devices as they are electrically identical. 

50 or 60 Hz Input: A shaping circuit (Figure 31 is pro- 
vided to square the 50 or 60 Hz input. This circuit 
allows use of a filtered sinewave input. The circuit is a 
Schmitt trigger that is designed to provide about 0.8V 
hysteresis. A simple RC filter such as shown in Figure 7 , 
should be used to remove possible line-voltage transients 
that could either cause the clock to gain time or damage 
the device. The shaper output drives a counter chain 
which performs the timekeeping function. 

50 or 60 Hz Select Input: A programmable prescale 
counter divides the input line frequency by either 
50 or 60 to obtain a 1 Hz time base. This counter is 
programmed to divide by 60 simply by leaving 50/ 
60 Hz select unconnected; pull-up to Vqd is pro- 
vided by an internal depletion load. Operation at 50 Hz 
is programmed by connecting 50/60 Hz select to Vgg. 

Display Mode Select Inputs: In the absence of any of 
these three inputs, the display drivers present time-of- 
day information to the appropriate display digits. 
Internal depletion pull-up devices allow use of simple 
SPST switches to select the display mode. If more than 
one mode is selected, the priorities are as noted in 
Table I. Alternate display modes are selected by apply- 
ing Vss t0 tne appropriate pin. As shown in Figure 1 
the code converters receive time, seconds, alarm and 
sleep information from appropriate points in the clock 
circuitry. The display mode select inputs control the 
gating of the desired data to the code converter inputs 
and ultimately (via output drivers! to the display digits. 



Time Setting Inputs: Both fast and slow setting inputs 
are provided. These inputs are applied either singly or 
in combination to obtain the control functions listed in 
Table II. Again, internal depletion pull-up devices 
are provided; application of Vgs to these pins affects 
the control functions. Note that the control functions 
proper are dependent on the selected display mode. 
For example, a hold-time control function is obtained 
by selecting seconds display and actuating the slow set 
input. As another example, the clock time may be reset 
to 12:00.00 AM, by selecting seconds display and actu- 
ating both slow and fast set inputs. 

Output Common: All display output drivers are open 
drain devices with all the sources connected to output 
common pin. This pin can be used as a common source 
or a common drain. When used as a common source, 
this pin is connected to Vss and when used as a com- 
mon drain, this pin is connected to VrjD- This allows 
the use of either common anode or common cathode 
LED's for displays. Figure 5 shows these connections. 

12 or 24 Hour Select Input: By leaving this pin uncon- 
nected, the outputs for the most-significant display 
digit (10's of hours) are programmed to provide a 
12-hour display format. An internal depletion pull- 
up device is again provided. Connecting this pin to 
Vss programs the 24-hour display format. Segment 
connections for 10's of hours in 24-hour mode are 
shown in Figure 6. 

Power Fail Indication: If the power to the integrated 
circuit drops, indicating a momentary ac power failure 
and possible loss of clock, all "ON" segments will 
flash at 1 Hz rate. A fast or slow set input resets an 
interna! power failure latch and returns the display to 
normal. 



connection diagrams (Top views) 

Dual-ln-Line Packai 



10HRS-b&c 




Dual-ln-Line Package 



COLON (1 Hz) 

12/24 HR SELECT 

ID HRb 124-HR) 

50/60 Hi SELECT 

50/60 Hi INPUT 

FAST SET INPUT 

SLOW SET INPUT 

SECOND 0ISPLAY INPUT 

ALARM DISPLAY INPUT 

SLEEP DISPLAY INPUT 

«DD 

«SS 

SLEEP OUTPUT 

ALARM "OFF" INPUT 

ALARM OUTPUT 

SNOOZE INPUT 

OUTPUT COMMON 

MINS -c 

MINS-d 



Order Number MM5402N 
See Package 24 

FIGURE 2(a).MM5402 



PM OUTPUT — 

COLON 11 Hi) 

12/24 HR SELECT 

10HRb(24HR| 

50/60 Hi SELECT 

50/60 Hi INPUT 

FAST SET INPUT 

SLOW SET INPUT 

SECOND DISPLAY INPUT 

ALARM DISPLAY INPUT 

SLEEP DISPLAY INPUT 

VDD 

«SS 

SLEEP OUTPUT 

ALARM "OFF" INPUT 

ALARM OUTPUT 

SNOOZE INPUT 

OUTPUT COMMON 

MINS-c 

MINS-d 




Order Number MM5405N 
See Package 24 

FIGURE 2(b). MMS405 (Mirror-Image Pin-Out) 



1-70 



functional description (Continued) 



Alarm Operation and Output: The alarm comparator 
(Figure 1) senses coincidence between the alarm count- 
ers (the alarm setting) and the time counters (real time). 
The comparator output is used to set a latch in the 
alarm and sleep circuits. The latch output enables the 
alarm output driver (Figure 4b) which is used to 
control the external alarm sound generator. The alarm 
latch remains set for 59 minutes, during which the alarm 
will therefore sound if the latch output is not tempor- 
arily inhibited by another latch set by the snooze alarm 
input or reset by the alarm "OFF" input. 

Snooze Alarm Input: Momentarily connecting snooze 
to Vss inhibits the alarm output for between 8 and 9 
minutes, after which the alarm will again be sounded. 
This input is pulled-up to Vqq by an internal deple- 
tion device. The snooze alarm feature may be repeatedly 
used during the 59 minutes in which the alarm latch 
remains set. 

Alarm "OFF" Input: Momentarily connecting alarm 
"OFF" to Vss resets the alarm latch and thereby 



silences the alarm. This input is also returned to VrjD by 
an internal depletion device. The momentary alarm 
"OFF" input also readies the alarm latch for the next 
comparator output, and the alarm will automatically 
sound again in 24 hours (or at a new alarm setting). 
If it is desired to silence the alarm for a day or more, 
the alarm "OFF" input should remain at VsS- 

Sleep Timer and Output: The sleep output can be used 
to turn "OFF" a radio after a desired time interval of up 
to 59 minutes. The time interval is chosen by selecting 
the sleep display mode, (Table I) and setting the desired 
time interval (Table II). This automatically results in a 
current sink output which can be used to turn "ON" a 
radio (or other appliance). When the sleep counter, 
which counts downwards, reaches 00 minutes, a latch 
is reset and the sleep output current drive is removed, 
thereby turning "OFF" the radio. This turn "OFF" 
may also be manually controlled (at any time in the 
countdown) by a momentary Vss connection to the 
Snooze input. The output circuitry is the same as the 
other outputs (Figure 4b). 




FIGURE 3. 50/60 Hz Input Shaping Circuit 



OUTPUt COMMON BUS 



A ►?„ 



FROM 
ALARM OR SLEEP >— I 
COMPARAtOR 



UtPUT 
(OPEN DRAIN) 




FIGURE 4(a). Segment Outputs 



FIGURE 4(b). Alarm and Sleep Outputs 



1-71 



functional description (Continued) 



TABLE I. MM5402, MM5405 Display Modes 



♦SELECTED 
DISPLAY MODE 


DIGIT NO 1 


DIGIT NO. 2 


DIGIT NO. 3 


DIGIT NO. 4 


Time Display 


10'sof Hours & AM/PM 


Hours 


10's of Minutes 


Minutes 


Seconds Display 


Blanked 


Minutes 


1 0's of Seconds 


Seconds 


Alarm Display 


10'sof Hours & AM/PM 


Hours 


10s of Minutes 


Minutes 


Sleep Display 


Blanked 


Blanked 


10'sof Minutes 


Minutes 



* If more than one display mode input is applied, the display priorities are in the order of Sleep (overrides 
all others), Alarm, Seconds, Time (no other mode selected I. 



TABLE II. MM5402, MM5405 Setting Control Functions 



SELECTED 
DISPLAY MODE 


CONTROL 
INPUT 


CONTROL FUNCTION 


♦Time 


Slow 


Minutes Advance at 2 Hz Rate 






Fast 


Minutes Advance at 60 Hz Rate 






Both 


Minutes Advance at 60 Hz Rate 




Alarm 


Slow 


Alarm Minutes Advance at 2 Hz Rate 






Fast 


Alarm Minutes Advance at 60 Hz Rate 






Both 


Alarm Resets to 12:00 AM (Midnight) (12-Hour Forrr 


at) 




Both 


Alarm Resets to 00:00 (24-Hour Format) 




Seconds 


Slow 


Input to Entire Time Counter is Inhibited (Hold) 






Fast 


Seconds and 10s of Seconds Reset to 2ero Withou 
a Carry to Minutes 






Both 


Time Resets to 12:00:00 AM (Midnight) (12-Hour Fo 


rmat) 




Both 


Time Resets to 00:00:00 (24-Hour Format) 




Sleep 


Slow 


Subtracts Count at 2 Hz 






Fast 


Subtracts Count at 60 Hz 






Both 


Subtracts Count at 60 Hz 





*When setting time sleep minutes wit! decrement at rate of time counter, until the sleep counter 
reaches 00 minutes (sleep counter will not recycle). 




COMMON ANODE 
LED 




COMMON CATHODE 



10HRM24HR] 

o 



-iM 



~/ H 



10 HR 
b&c 



FIGURE 5(a). Common 
Anode Application 



FIGURE 5(b). Common 
Cathode Application 



FIGURE 6. 24-Hour Operation: 
10's of Hours Digit Connections 



1-72 



typical applications 

Figure 7 is a schematic diagram of a general purpose alarm clock circuit (12-hour mode) using the MM 5402 or MM 5405 
and a 3 1/2 -digit LED display. 



rx 

0. 

T 



6i 6i o I 6 1 Oi 6i 4 1 

NC NC ol ol O I O ' Oi q\ ol 



{60 H^) (12 HR) 



OUTPUT COMMON 



MM5402 OR r,1M54Q5 



\j QD 10'S OF HOURS UNIT HOURS 



ID'S OF MINUTES 



-M- 




-w- 



i i i i r - ! - ] i i n n rn n r 

<M 



TT 






o 1 o- 



COMMDN ANODE 



r>H"i 



OOQ 

V LED 
SUPPLY 



I 



. J 



o 

is) 



oi 
o 

Ol 



47k 1 

T l__^__wSLEEP 

ra DRIVE 



^WHi 
4 7k 

o 



T 

L_l J 



1-73 



CO 



a 



Clocks 



USING NATIONAL CLOCK INTEGRATED CIRCUITS IN TIMER APPLICATIONS 



INTRODUCTION 



The following is a description of a technique which 
allows the use of the National MM5309, MM5311, 
MM5312 and MM5315 clock integrated circuits as 
timers in industrial and consumer applications. What 
will be presented is the basic technique along with some 
simple circuitry and applications. 

BASIC TECHNIQUE 

When first approaching the problem of using clock chips 
for timers, the most obvious technique is to attempt to 
compare the display data with preset BCD numbers. 
Because of the multiplexing and number of data bits 
this technique, while possible, is unwieldy and requires a 
large number of components. 



An easier method is to use one or more demultiplexed 
BCD lines as control waveforms whose edges determine 
timer data. In Figure 1 we examine the 1-bit of the BCD 
data of the units second time. 



From this waveform we observe a one second wide pulse 
every two seconds. If we look at the 4-bit of the 10 
minutes digit we find a pulse which is 20 minutes wide 
and occurs once each hour. 



Figure J is a chart showing the various pulses and their 
widths for all digits and the useful BCD lines. 



UNIT SECOND 
DIGIT TIME 



1 2 3 4 5 6 7 



ru^^uin_ 



FIGURE 1. 1 Second Pulse Every 2 Seconds 



2 3 4 5 12 3 4 5 



10MINITE DIGIT 
TIME 
BCD I 



FIGURE 2. 20 Minute Pulse Every Hour 



1-74 



> 

2 
■ 

W 



BCD 


PULSE RATE PULSE WIDTH 


BCD 


PULSE RATE PULSE WIDTH 




1 Sec Digit 




10 Sec Digit 


1 


1 every 2 sec 1 sec* 


1 


1 every 20 sec 10 sec* 


2 




2 


1 every min 20 sec 


4 


1 every 10 sec 4 sec 


4 


1 every min 20 sec 


8 


1 every 10 sec 2 sec 


8 






1 Min Digit 




10 Min Digit 


1 


1 every 2 min 1 min* 


1 


1 every 20 min 10 min* 


2 




2 


1 every hr 20 min 


4 


1 every 10 min 4 min 


4 


1 every hr 20 min 


8 


1 every 10 min 2 min 


8 






Units Hrs Digit (12 Hr Mode) 




Units Hrs Digit (24 Hr Mode) 


1 


1 every 2 hrs 1 hr* 


1 


1 every 2 hrs 1 hr* 


2 




2 




4 


1 every 12 hrs 4 hrs 


4 




8 


1 every 12 hrs 4 hrs 


8 






10 Hrs Digit (12 Hr Mode) 




10 Hrs Digit (24 Hr Mode) 


1 




1 


1 every 24 hrs 10 hrs 


2 


1 every 12 hrs 9 hrs 


2 


1 every 24 hrs 4 hrs 


4 


1 every 12 hrs 9 hrs 






8 


1 every 12 hrs 9 hrs 







•Square waves 



SIMPLE DEMULTIPLEXING 



MORE COMPLEX APPLICATIONS 



In the simple case where, for example, a four hour wide 
pulse each day is desired, perhaps to turn on lights in the 
evening, a simple demultiplexing scheme using one diode 
is shown in Figure 4. When power is applied, the internal 
multiplex circuitry will strobe each digit until the digit 
with the diode connected is accessed. This digit will 
sink the multiplex charging current and stop the multi- 
plex scanning. Thus, the BCD outputs now present the 
data from the selected digit. The waveforms as previously 
discussed are presented at the BCD lines. Note that these 
pulses are negative true for all BCD outputs. 

An advantage of this type of timer over mechanical 
types is the elimination of line power drop outs. The 
circuit shown in Figure 5 will maintain timing to within 
a few percent during periods of power line failure, but 
automatically return to the 60 Hz line for timing as soon 
as power is restored. 



Where it is desired to maintain the display, or in more 
complex timing of the "10 seconds every two hours" 
variety, external demultiplexing shown in Figure 6 can 
be used. In this figure the BCD lines are demultiplexed 
with MM74C74 flip-flops. Examining the waveforms of 
these circuits we see two edges which allow the 10 
second each two hours timing. These are differentiated 
by the NAND and INVERTERS and the first edge sets 
and the second resets the S-R flip-flop. The output of the 
flip-flop is ten seconds wide every two hours. By exam- 
ining the edges of the Figure 3 entries any combination 
of timings can be obtained with the circuit of Figure 6. 

LOW FREQUENCY WAVEFORM GENERATION 

The asterisked BCD lines in Figure 3 are those wave- 
forms which are symmetric. By the use of the simple 
diode demultiplexing scheme previously discussed we 



1-75 



CO 

z 

< 



MUX 

TIMING 

INPUT 



DIGIT 
LINE 



BCD LINES 
. FORSELECTED 
DIGIT 



3 



-*-M- 



"V/" 



d 

T 



r 



-AAV- 





X 



-5*£ — 



100k 

SET TO 

SO Hz 

WITH LINE 

UNCONNECTED 




MUX H10 

TIMING V DO DIGIT 16 



HI 




w- 



/ /FUST 

/RESET / SET 



FIGURE 5. Fail-Safe Automatic Lights Timer. Four Hours Each 24 Hours 



easily obtain square waves with periods of two seconds, 
two minutes, twenty minutes and two hours. In other 
cases, where the waveforms are asymmetric, a simple 
flip-flop can square, while dividing by two, these wave- 
forms producing other low frequency square waves as 
long as one per two days. 

SUMMARY 

We have shown some simple low cost timer and waveform 
generating examples using National clock integrated 



circuits. Because of the vast number of timing applica- 
tions possible, this can in no way be looked at as the 
limit of clock-timer circuits. Use of the Reset on the 
MM5309 and MM5315orthe use of clocks in conjunction 
with programmable counters such as the MM74C161 
allows other possibilities to meet specific applications. 
Also the clock chips themselves can run on frequencies 
other than 50 or 60 Hz (actually from dc to 10 kHz) 
which can allow scaling of the waveforms presented in 
Figure 3 to different timing rates. 



1-76 



CLK 



10k > 



> 
25 

t 
w 




liTJiJiirrLTLnj* 



RESULTANT 10 SEC EVERY 2 HRS 



FIGURE 6. More Universal Demultiplexing Technique 



1-77 




SECTION 2 
COUNTERS/TIMERS 



sa 



Counters/Timers 



MM5307 baud rate generator/programmable divider 



general description 



The National Semiconductor MM5307 baud rate 
generator/programmable divider is a MOS/LSI P-channel 
enhancement mode device. A master clock for the device 
is generated either externally or by an on-chip crystal 
oscillator (Note 4). An internal ROM controls a divider 
circuit which produces the output frequency. Logic 
levels on the four control pins select between sixteen 
output frequencies. The frequencies are chosen from 
the following possible divisors: 2N, for 3 < N < 2048; 
2N + 1 and 2N + 0.5 for 4 < N < 2048. Also one of the 
sixteen frequencies may be gated from the external 
frequency input. The MM5307AA is supplied with the 
divisors shown in Table I. 

features 

■ On-chip crystal oscillator 

■ Choice of 16 output frequencies from 1 crystal 



■ External frequency input pin 

■ Internal ROM allows generation of other frequencies 
on order 

■ Bipolar compatibility 

■ 0.01% accuracy (typ) exclusive of crystal 

■ 1 MHz master clock frequency 

applications 

■ DAR/T clocks 

■ System clocks 

■ Electrically programmable counters 



schematic and connection diagrams 




> 



EXTERNAL 
CLOCK 



>■ 



111 

V GG V 0D "SS 



PROGRAMMABLE 
DIVIDER 



C10CK 
GENERATOR 



OSCILLATOR 



qj 



MULTIPLEXER 



Dual-ln-Line Package 



< 



EXT. 
FREQ 



> 



1NALFRE0.— 


u 


2 
NC — 




OUTPUT- 




'S— 




EXTERNAL _£. 
CLOCK 




6 
CRYSTAL — 




CRYSTAL — 





-0OUT 
L RESET 



Order Number MM5307N 
See Package 1 8 



2-2 



absolute maximum ratings 

Voltage at Any Pin With Respect to Vss 

Power Dissipation 

Storage Temperature Range 

Operating Temperature 

Lead Temperature (Soldering, 10 seconds) 



+0.3V to Vss - 20v 

700 mW 

-65°Cto+150°C 

0°C to +70°C 

300°C 



dc electrical characteristics 

Ta within operating range, V'ss = 5V ±5%, Vqg = -12V ±5%, unless otherwise specified. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 




All Inputs (Except Crystal Pins) 












V|H 


Logical High Level 




VSS 15 




Vss+0.3 


V 


V|L 


Logical Low Level 




VSS-18 




V SS -4.2 


V 




Leakage 


V| N = -10V, T A = 25°C, 
All Other Pins GND 






0.5 


uA 




Capacitance 


V|N = 0V, f- 1 MHz, 

All Other Pins GND, (Note 1) 






7.0 


pF 




External Clock Duty Cycle 




40% 




60% 






Capacitance Measured Across 


f = 1 MHz, (Note 3) 






5.0 


pF 




Crystal Pins 














Output Levels 












VOH 


Logical High Level 


'SOURCE = -0.5 mA 


VSS-2.6 


vss 




V 


vol 


Logical Low Level 


'SINK = 1.6 mA 






Vss -4.6 


V 


*GG 


Power Supply Current 


f = 1 MHz 






35 


mA 



ac electrical characteristics 

Ta within operating range Vss = 5V ±5%, Vqg = -1 2V ±5%, unless otherwise specified. 



PARAMETER 



Master Frequency 
tA Access Time 

tpo Reset Delay Time 

RpyV Reset Pulse Width 

'OD Output Delay From Reset 

Output Duty Cycle = 0.5T + 1/f 



CONDITIONS 



C L = 50pF, (Note 2) 

f = Master Clock Frequency 



T - Output Period 
f - Master Frequency 



MIN 



500 + 4/f 



0.5T-1/f 



TYP 



MAX 



1.0 
16 

500 + 4/f 

500 + 4/f 
0.5T+1/f 



UNITS 



MHz 
MS 



Note 1 : Capacitance is guaranteed by periodic measurement. 

Note 2: Access time is defined ais the time from a change in control inputs (A, B, C, D) to a stable output frequency. Access time is a function of 

frequency. The following formula may be used to calculate maximum access time for any master frequency: Ta = 2.8ns + 1/f x 1 3, f is in MHz. 

Note 3: The MM5307 is designed to operate with a 1 MHz parallel resonant crystal. When ordering the crystal a value of load capacitance (C L ) 

must be specified. This is the capacitance "seen" by the crystal when it is operating in the circuit. The value of C L should match the capacitance 

measured at the crystal frequency across the crystal input pins on the MM5307. Any mismatch will be reflected as a very small error in the 

operating frequency. To achieve maximum accuracy, it may be necessary to add a small trimmer capacitor acrols the terminals. 

Note 4: If the crystal oscillator is used Pin 5 (external clock) is connected to Vss- If an external clock is used Pin 7 is connected to Vss- 



2-3 



o 

CO 

in 

2 



control table 



;<*Z 









nput Freq: 921.6 kHz Master Clock 




CONTROL PINS 


NOMINAL BAUD RATES 
(OUTPUT FREQUENCY/16) 


DIVISOR 
FOR AA 


A 


B 


c 


D 


AA AB FAG 











1 


50 50 50 


1152 








1 





75 200 75 


768 








1 


1 


110 110 110 


524 





1 








134.5 134.5 134.5 


428.5 





1 





1 


150 150 150 


384 





1 


1 





300 300 300 


192 





1 


1 


1 


600 600 600 


96 













900 900 1050 


64 










1 


1200 1200 1200 


48 







1 





1800 1800 45.5 


32 







1 


1 


2400 2400 2400 


24 




1 








3600 3600 56.9 


16 




1 





1 


4800 4800 4800 


12 




1 
1 


1 
1 




1 


7200 75 66.7 
9600 9600 9600 


8 
6 














EXTERNAL FREQ 





Positive Logic: 1 = V (-| 
0- V L 



typical applications 



Internal Oscillator 



External Clock 



EXT FREQ ► 




13 v ss (TO OPERATE) 

V GG (TO RESET) 
12 







» ' 








2 

NC 

, 3 






4 






5 






1 


6 
7 













o 

Vss 



13 ^ V ss (TO OPERATE) 
V GG (TO RESET) 



2-4 



timing diagram 




application hints 

APPLICATION NOTES 

The external clock is brought in on pin 5 and pin 7 is 
tied to Vss to enable the external clock input. Pin 6 
can be left open. 

1) To use the MM 5307 with an external clock, hook 
it up as follows: 



TIE PIN7T0 V S sT0 ENABLE 
NOR GATE 




EXTERNAL CLOCK 

2) To use a crystal directly: 



T0R0TEL -^X 01793 

30 pF 921.6kHz 180 pF 



^lh^A/V-J-| [-vss 




CLDCKTO INTERNAL 
CIRCUITRY 



3) Reset (pin 13) must be at Vgs to operate. It may be 
necessary to take this to 6ND or Vqg to reset the 
ROM select circuit. An option is to tie out (pin 14) 
to external Freq In (pin 1 ), if not otherwise used. 

4) An interesting application might use two MM5307's 
in series to generate additional frequencies, i.e., with 
one programmed from the 921.6 kHz to 800 Hz out, 
a second could divide that by 16 to give a 50 Hz 
crystal controlled signal. 

5) MM307AA divisors are on the data sheet. AB divisors 
are the same as the AA except: 1) Code 0010 is 
divided by 288 - 32 kHz out, 200 baud; 2) Code 
1110 is divided by 768-* 1.2 kHz, 75 baud. 

The MM5307 does not always generate an output when 
the power is up, even though the oscillator seems to be 
operating properly. In order to eliminate this problem, 
it is necessary to reset the chip at power "ON". This can 
be done manually, with a reset signal by a host system, 
or automatically by using R/C timing elements. The 
reset is done internally, when program inputs change. 
When using an R/C combination for auto resetting, 
the time constant must be several times larger than 
that of the power supply. For example, most lab power 
supplies take at least 0.5 sec for the voltage to reach 
90% of full level. A 10 kQ resistor and 300 [jF capacitor 
combination should be adequate for most applications. 



TO V<; S T0 ENABLE XTAL 
OSCILLATION 



2-5 



application hints (Continued) 



"DD 



-tf 



6-25 pF 



hQi-t — II — v - 



<>— VW-h> 



25 



6 7 

EXTERNAL 13 

CLOCK RESET 
5 



«SS 



VSS 



10k 



1 



— I — ,„„ r I MANUAL 

300 ^F j— RESET 



J 



VOLTAGE 



POWER SUPPLY TIMING 
AT POWER UP 

TIMING, 




« 0.5 SEC 

TIME 
FIGURE 1 



2-6 




Counters/Timers 



CO 

a> 

CO 



MM5369 17-stage programmable oscillator/divider 



general description 



features 



The MM5369 is a CMOS integrated circuit with 17 
binary divider stages that can be used to generate a 
precise 60 Hz reference from commonly available high 
frequency quartz crystals. An internal pulse is generated 
by mask programming the combinations of stages 1 
through 4, 16 and 17 to set or reset the individual stages. 
The programmable number the circuit will divide by can 
vary from 10000 to 98000. The MM5369 is advanced 
one count on the positive transition of each clock pulse. 
Two buffered outputs are available: the crystal fre- 
quency for tuning purposes and the 17th stage 60 Hz 
output. Mask options are available for use with com- 
monly available, low cost, high frequency crystals. 
Therefore, this design can be "customized" by special 
order to design specific programmable divider limits 
whereby the maximum divide-by can be 98,000 and 
the minimum divide-by can be 10,000. The MM5369 is 
available in an 8 lead dual-in-line epoxy package. 



■ Crystal Oscillator 

■ Two buffered outputs 

Output 1 cyrstal frequency 
Output 2 full division 

■ High speed (4 MHz at V DD = 10) 

■ Wide supply range 3-15V 

■ Low Power 

■ Fully static operation 

■ 8 lead dual-in-line package 

■ Low current 

Standard MM5369N Only 

■ 3.58 MHz (color TV oscillator) input frequency 

■ 60 Hz output frequency 



connection diagram 



block diagram 



Dual-ln-Line Package 






WIDER Vss 
(60 Hzl 
OUTPUT TOP VIEW 







□SCOUT 

I 








osc 








osc in — 


— 


■ • » 

r 


17 STAGE DIVIDER 


T 


BUFFER 


h DIVIDER 








W OUTPUT 


I 


.11 Ir- 


J 








BUFFER 




OUTPUT 




RESET PULSE GENERATOR 

FIGURE 2. 


t t 






Vss V 0O 



Order Number MM5369N 
See Package 1 7 



7-1 



CO 
CO 

in 

2 



absolute maximum ratings 

Voltage at Any Pin 

Operating Temperature 

Storage Temperature 

Package Dissipation 

Maximum V cc Voltage 

Operating V cc Range 

Lead Temperature (Soldering, 10 seconds) 



-0.3V to V cc +0.3V 

0°C to +70°C 

-65°Cto+150°C 

500 mW 

16V 

3V to 15V 

300° C 



electrical characteristics 

T A within operating temperature range, V ss = GND, 3V < V DD < 15V unless otherwise specified. 



PARAMETER 



Quiescent Current Drain 
Operating Current Drain 
Frequency of Oscillation 

Output Current Levels 

Logical "1" Source 
Logical "0" Sink 

Output Voltage Levels 

Logical "1" 
Logical "0" 



CONDITIONS 



V DD = 15V 

V DD = 10V, f IN = 4.19MHz 



'DD 



10V 



V 0D =6V 
V DD =10V 



V 



OUT 



= 5V 



V DD = 10V 
l = 10 mA 



MIN 



DC 
DC 



500 
500 



9.0 



TYP 



1.2 



MAX 



10 

2.5 

4.5 
2 



1.0 



UNITS 



MA 

mA 

MHz 
MHz 



MA 
MA 



functional description 



A connection diagram for the MM5369 is shown in 
Figure 1 and a block diagram is shown in Figure 2. 

TIME BASE 

A precision time base is provided by the interconnection 
of a 3,579,545 Hz quartz crystal and the RC network 
shown in Figure 3 together with the CMOS inverter/ 
amplifier provided between the OSC IN and the OSC 
OUT terminals. Resistor R1 is necessary to bias the 
inverter for class A amplifier operation. Capacitors C1 
and C2 in series provide the parallel load capacitance 
required for precise tuning of the quartz crystal. 

The network shown provides > 100 ppm tuning range 
when used with standard crystals trimmed for C L = 
12 pF. Tuning to better than ±2 ppm is easily ob- 
tainable. 



DIVIDER 

A pulse is generated when divider stages 1 through 4, 16 
and 17 are in the correct state. By mask options, this 
pulse is used to set or reset individual stages of the 
counter, thus varying the modulus of the counter from 
10000 to 98000. Figure 4 shows the relationship 
between the duty cycle and the programmed modulus. 

OUTPUTS 

The Tuner Output is a buffered output at the crystal 
oscillator frequency. This output is provided so that the 
crystal frequency can be obtained without disturbing the 
crystal oscillator. The Divide Output is the input fre- 
quency divided by the mask programmed number. Both 
outputs are push-pull outputs. A typical application of 
the MM5369 is shown in Figure 5. 



functional description (cont.) 



■>- 



VddOBUss- 






C1 3-579545 MHi 

5-JfipF C L ' 12 ff 



i 





too 

90 
80 
70 
SO 
50 
40 
30 
20 
10 
















































= 


-"STANDARD" 








£ 










■■ 
















o 
















5 




































" 














I 











w 



FIGURE 3. Crystal Oscillator Network 



10 20 30 JO 50 60 70 

DUTY CYCLE IS) 

FIGURE 4. Plot of Divide-By Vs Duty Cycle 




FIGURE 5. Clock Radio Circuit with Battery Back-Up 











1 

* 










jl 






^*""v 


DD = I0 


1*' 








_„V 








^1- 


"'VoD 


= 5V 



26.875 














32,764 




COUNTS 




COUNTS 















1 2 3 4 5 



FIGURE 6. Typical Current Drain Vs Oscillator Frequency FIGURE 7. Output Waveform for Standard MM5369 



To be selected based on xtal used 



2-9 




MM5865 universal timer 
general description 

The MM5865 Universal Timer is a monolithic MOS 
integrated circuit utilizing P-channel low-threshold, 
enhancement mode and ion-implanted depletion mode 
devices. The chip contains all the logic required to 
control the two 4-digit counters, blank leading zeros, 
compare the two counters and to cascade with another 
MM5865. Input pins start, stop, reset and set the 
counters, determine which of the 7 functions is per- 
formed, the resolution of the display (0.01 sec, 0.1 sec, 
1 sec, or external clock) and what modulo the counters 
divide by. Outputs include the comparator output, 
multiplexed BCD outputs and digit enables. The BCD 
outputs interface directly with MM14511, a BCD to 
7-segment decoder, which interfaces with a LED display. 
The digit enable outputs of 2 cascaded MM5865's 
interface directly with a DM8863 LED 8-digit driver. 
A DS8877 or DS75492 Hex Digit Driver may be used 
with a single MM5865. The digit enable outputs inter- 
face directly with a DM8863, a LED digit driver. The 
7 functions include start-stop with total elapsed time, 
start-stop with accumulative event time, split, sequential 
with total elapsed time, rally with total elapsed time 
program up count and program down count. The circuit 
uses a 32.8 kHz crystal or an external clock and is 
packaged in a 40-lead dual-in-line package. 

applications 

■ Stop watch 

■ Kitchen timer 

■ Oven timer 

■ Event timer/counter 

■ Rally timer 

■ Navigational timer 

■ Industrial timer/counter 



Counters/Timers 

For additional application information, see 
AN-168 and AN-169 at the end of this section. 



features 

■ Function 1 : Standard Start-Stop with total elapsed 
time memory 

" Function 2: Standard Start-Stop with total accumu- 
lative event time 

■ Function 3: Sequential with total elapsed time 
memory 

■ Function 4: Standard split 

■ Function 5: Rally with total elapsed time memory 

■ Function 6: Programmable up count. Repeatable 
upon command 

■ Function 7: Programmable down count 

■ Comparator output 

■ Crystal controlled oscillator (32.8 kHz) 

■ External clock input (option) 

■ Provides external clock 

■ Select resolution 

■ Select count up or down 

■ Select modulo 6 or 10 for digits 2, 3 and 4 

■ Blanking between digits 

■ Leading-zero blanking 

■ Multiplex rate output 

■ External multiplex rate input (option) 

■ Can be cascaded 

■ Waiting state indicator 

■ Simple interface to LED display 

" Elimination of illegal time display at turn-on 

■ Wide power supply range 7V— 20V 



block and connection diagrams 



ual-ln-Line Package 



PROGRAM \ 

DIGITS 1-4 (/ 


























CONTROL 
LOGIC 








DIVIDE N. 

SCALER y/ 

FUNCTIONS *\ 

i-i / 




u 








. 


COMPARATOR, 
DISPLAYSELECT, 
LATCHES, MULTI 
PLEXER AND LEADING 
ZERO BLANKING 


=C> 


BUF- 
FERS 


^> 






i — \ 


=> 




C2IN 






















ir 














C00NTER2 








OMPARATOR - 






























MULTIPLEXER 




18 STAGE DIVIDER 


*- 


OSCIL- 
LATOR 




OUT 















r 


r 1 






w 


1 










RESOLUTION 
SELECT 




BLANKING 




IN ram 








1 




t ' 










RESOLUTION 
KFIFnT 2 













DIVIDE SCALER 1 ■ 

DIVIDE SCALER 2- 

DIVIDE SCALER3- 

COMPARATOR ENABLE ' 

FUNCTION 1 ■ 

FUNCTION 2- 

FUNCTION 3' 

FUNCTION 4 ■ 

FUNCTION 5- 

FUNCTION 6- 

FUNCTION 1- 

FINAL EVENT STOP/. 

COMPARATOR OUT 

RESET 

START/STOP 

CLOCK IN/OUT 

RESOLUTION SELECT 1 

RESOLUTION SELECT 2 

BLANKING 

0SGIN 

0SC OUT 



PROGRAM DIGIT V 
LATCH CONTROL 
PROGRAM DIGIT 2 
PROGRAM DIGIT 3 
PROGRAM DIGIT 4/ 
WAITING STATE 
CONTROL C1 IN 
CONTROL CI OUT 




Order Number MM5865N 

See Package 24 

FIGURE 2. 



2-10 



absolute maximum ratings 

Voltage at Any Pin ' 

Operating Temperature 

Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 



+ 0.3V to V ss - 25V 

-25°Cto+70°C 

-65°Cto+150°C 

300°C 



electrical characteristics 

T A within operating range, 7V < V ss < 20V, 



V DD = 0V, unless otherwise specified. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


l DD Power Supply Current 






7 


15 


mA 


Input Frequency at OSC IN 


] 


dc 


32.8 


80 


kHz 


Multiplex Frequency 


J V ss > 10V 


dc 


0.4 


80 


kHz 


Blanking Frequency 


J 


dc 


0.8 


10 


kHz 


Clock Frequency 


V S s = 7V 


dc 


0.1 


10 


kHz 




V^ = 10V 


dc 




100 


kHz 


Input Levels 












Input Logic Low 


Internal Resistor 


Vdd 




V DD + 1 


V 


Input Logic High 


~100k to V DD 


Vss 1 




Vss 


V 



OUTPUT CURRENTS 



Digit and BCD Outputs 
Source Current 
Sink Current 

Blanking Output 
Source Current 
Sink Current 

Multiplex Output 
Source Current 
Sink Current 

Clock Output 
Source Current 
Sink Current 

Control C1, C2 Outputs 
Source Current 

Control CI, C2 Inputs 
Sink Current 

Comparator Output 
Source Current 
Sink Current 

Waiting State Indicator 
Source Current 
Sink Current 



Vss = 7V 




Vout = V ss 


-2V 


Vout = V ss 


-6.3V 


V ss = 7V 




Vout = V ss 


-2V 


Vout = V ss 


-6.3V 


V ss = 7V 




Vout ~ V ss 


-2.5V 


Vout = V S s 


-6.3V 


V ss = 7V 




Vout = V s s 


-4V 


Vout = v ss 


-6.3V 


V S s = 7V 




Vout = V ss 


-2.5V 


V S s = 7V 




V,n = V gs - 


6.3V 


V ss = 7V 




Vout = V S s 


-2V 


Vout = V S s 


-6.3V 


Vss = 7V 




Vout = V S s 


-2V 


Vqut = V S s 


-6.3V 



500 



10 
5 



500 



mA 
HA 

mA 
uA 

M 
uA 

MA 
HA 

UA 

HA 

mA 
MA 

mA 
MA 



2-11 



functional description 

A block diagram of the MM5865 Universal Timer is 
shown in Figure 7. A connection diagram is shown in 
Figure 2. Unless otherwise indicated, the following 
discussions are based on Figure 1. 

Function 1 



V DD to V ss switches the display from counter 2 to 
counter 1. Repetitive Start-Stop transitions switch the 
display between counter 2 and counter 1. 



Function 2 



tn Function 1, counters 1 and 2 count up beginning 
with a transition on the Start-Stop pin from V DD to 
V ss . Counter 2 is shown counting. A second transition 
from V DD to V ss on the Start-Stop pin inhibits the 
clock pulses to counter 2, stores and displays the con- 
tents of counter 2. Counter 1 continues to count. The 
third transition from V DD to V ss on the Start-Stop 
pin resets counter 2, enables clock pulses to counter 2 
and displays counter 2 counting. Subsequent Start- 
Stop transitions repeat this sequence, all this time 
counter 1 continues to count. At the conclusion of 
the last event to be timed, a Final Event Stop transition 
from V DD to V ss inhibits the clock to both counters 
and displays counter 2. A Start-Stop transition from 



In Function 2, counter 1 and 2 count up beginning with 
a transition on the Start-Stop pin. Counter 2 is displayed 
counting. A second transition on the Start-Stop pin 
inhibits the clock pulses to both counter 1 and counter 
2, stores and displays the contents of counter 2. The 
third transition on the Start-Stop pin resets counter 2, 
enables the clock to both counters and displays counter 
2 counting. Subsequent Start-Stop transitions repeat 
this sequence. At the conclusion of the last event to be 
timed, a Final Event Stop transition inhibits the clock 
to both counters and displays counter 2. A Start-Stop 
transition switches the display from counter 2 to 
counter 1. Repetitive Start-Stop transitions switch the 
display between counter 2 and counter 1. 



RESET 
FORCESTO- 
THIS STATE 




COUNTER I INHIBITED 

L0UNTEH2 INHIBITED 

DISI'lAY COUNTER 25 LAST COUNT 




Flow Chart for Function 1 



Flow Chart for Function 2 



2-12 



functional description (con't) 

Function 3 

In Function 3, counter 1 and 2 count up beginning with 
a transition on the Start-Stop pin. Counter 2 is displayed 
counting. A second transition on the Start-Stop pin 
stores and displays the contents of counter 2, resets 
counter 2, and initiates a new up-count in counter 2; 
however, the new up-count is not displayed. Counter 1 
continues to count. A transition on the Latch Control 
pin will display counter 2 counting until another transi- 
tion on the Start-Stop pin. A Final Event Stop transition 
inhibits the clock pulses to both counters 1 and 2 and 
displays the contents of counter 2. A Start-Stop transi- 
tion after the Final Event transition switches the display 
from counter 2 to counter 1. Repetitive Start-Stop 
transitions switch the display between counter 2 and 
counter 1 . 



Function 4 

In Function 4, counter 2 counts up beginning with a 
transition on the Start-Stop pin. Counter 2 is displayed 
counting. A second transition on the Start-Stop pin 
stores and displays the contents of counter 2. Subse- 
quent Start-Stop transitions update the display of 
counter 2. A transition on the Latch Control pin will 
display counter 2 counting until a transition on the 
Start-Stop pin. A Final Event Stop transition inhibits the 
clock pulses to counter 2 and displays the contents of 
counter 2. 



on 
00 

o> 





Flow Chart for Function 3 



Flow Chart for Function 4 



2-13 



functional description (con't) 



Function 5 



Function 6 



In Function 5, counter 1 and 2 count up beginning with 
a transition on the Start-Stop pin. Counter 2 is displayed 
counting. A second transition on the Start-Stop pin 
inhibits the clock pulses to counter 2, and the contents 
of counter 2 are displayed. Counter 1 continues count- 
ing. The third Start-Stop transition enables the clock 
pulses to counter 2 and counter 2 is displayed counting. 
Subsequent Start-Stop transitions repeat this sequence, 
all the time counter 1 continues counting. At the conclu- 
sion of the last event to be timed, a Final Event Stop 
inhibits the clock pulses to both counters 1 and 2, and 
displays counter 2. A Start-Stop transition switches 
the display from counter 2 to counter 1. Repetitive 
Start-Stop transitions switch the display between counter 
2 and counter 1. 



In Function 6, counter 1 is displayed at power-on or 
reset. Counter 1 is set to a specific count by Program 
Digit 1—4 pins. Then the comparator is enabled. Counter 
2 is displayed counting up beginning with a transition 
on the Start-Stop pin. When counter 2 is coincident with 
counter 1, the clock pulses to counter 2 are inhibited, 
the contents of counter 2 are displayed and the Com- 
parator Output is enabled. Upon the transition of Reset, 
counter 1 is again displayed with the time that was set, 
and the Comparator Output is disabled. Counter 1 can 
be reprogrammed by the Program Digit 1—4 pins if 
desired. A Start-Stop transition repeats the sequence. 

If the Comparator Output pin is connected to the 
Reset pin, Automatic Reset will occur, however, this 
connection must be broken during digit programming. 



HESET 
FORCES TO - 
THIB STATE 




COUNTER 1 INHIBITED 
COUNTER 1 INHIBITED 
DISPLAY C0DNTER2 




COUNTER 1 INHIBITED 
COUNTER Z INHIBITED 
DISPLAY CO DNTER 1 



COUNTER I COUNTING 

COUNTER 2 INHIBITED 

DISPLAY COUNTER 2'S LAST COUNT 




LL 



POWER ON RESET 

DISPLAY COUNTER I, 

SET COUNT IN COUNTER 1 

ENABLE COMPARATOR 




COUNTER 1 INHIBITED 

COUNTER 2 COUNTING UP 

DISPLAY COUNTER 2 




COUNTEfi 1 INHIBITED 

C0UNTER2 INHIBITED 

DISPLAY COUNTER 2 

COMPARATOR OUTPUT ENABLED 






RESE 
DISPLfl 


CQUNTER2 
Y COUNTER 1 








\ yE $ 






[no 





Flow Chart for Function 5 



Flow Chart for Function 6 



2-14 



functional description (con't) 



Function 7 



In Function 7, counter 1 is displayed all the time. 
Counter 1 is set to a specific count by Program Digit 
1-4 pins. Then the comparator and Control CI In 
are enabled. Pin 4 and pin 35 must be floating or con- 
nected to V DD during digit programming. Counter 1 
counts down from the set count beginning with a 
transition on the Start Stop pin. When counter 1 counts 
down to zero, the clock pulses to counter 1 are inhib- 
ited and the comparator Output is enabled. This is not 
fepeatable without setting a new count into counter 1. 
The comparator and Control C1 In must be inhibited 
and a reset pulse must occur before the new count 
may be entered. 



Stop to affect the counters, it must be held to V ss , 
a logic one. Logic zero results when the pin is tied to 
V DD or left floating (internal pull-up to V DD ). 

Final Event Stop/Comparator Output 

This pin is used to indicate to the circuit that no more 
events will be timed or counted. Final Event Stop affects 
the circuit when it is held to V ss . There is an internal 
pull-up to V DD . This pin is also an output pin, V ss 
indicates comparison between the two counters. 

Divide Scale Inputs 



POWER ON RESET 

DISPLAY COUNTER t, 

SET COUNT IN COUNTER 1 

ENABLE COMPARATOR 





COUNTER 1 INHIBITED 

DISPLAV COUNTER 1 

COMPARATOR OUTPUT ENABLED 




Flow Chart for Function 7 



These three inputs are used to determine whether the 
counters will count in Modulo 6 or Modulo 10. Table I 
shows the code for which digit will count in Modulo 6 
or Modulo 10. A logic one is when the pin is held to 
V ss . When the pin is tied to V DD or left floating (inter- 
nal pull-up to V DD ), a logic zero results. 



TABLE I. Divide Scaler Code 



DIVIDE 
SCALER 






COUNTER 






COUNTER 2 




1 2 


3 


D4 


D3 D2 


D1 


D4 


D3 D2 


D1 








10 


10 10 


10 


10 


10 10 


10 


1 





6 


10 10 


10 


6 


10 10 


10 


1 





10 


6 10 


10 


10 


6 10 


10 


1 1 





10 


10 6 


10 


10 


10 6 


10 





1 


10 


10 10 


10 


10 


10 10 


10 


1 


1 


10 


10 to 


10 


6 


10 10 


10 


1 


1 


10 


10 10 


10 


10 


6 10 


10 


1 1 


1 


10 


10 10 


10 


10 


10 6 


10 



Comparator Enable 

This input enables the comparator. To enable the com- 
parator, the pin is held to V ss or logic one. To disable 
the comparator, the pin is tied to V DD or left floating 
(internal pull-up to V DD ). 

Resolution Select Inputs 

These two inputs are used to select the frequency of the 
clock pulses to the counters. Table II shows the code for 
each frequency. A logic one is when the pin is held to 
Vss. A logic zero results when the pin is tied to V DD or 
left floating (internal pull-up to V DD ). 



Reset 



This input will reset all logic and counters in Functions 
1—5 and Function 7. In Function 6, Reset will reset 
logic but not counter 1. Reset is internally pulled to 
V DD , or a logic zero. For a reset to occur, the Reset pin 
must be held to V ss , a logic one. 

Start-Stop 

This input is used to control the counters. How it affects 
the counters is explained in each function. For Start- 



TABLE II. Resolution Select Code 



RESOLUTION 
SELECT 
1 2 


FREQUENCY 

OF CLOCK TO 

COUNTERS 


DISPLAY 
RESOLUTION 




1 

1 

1 1 


100 Hz 
10 Hz 
1 Hz 
External 


0.01 sec 
0.1 sec 
1 sec 



2 15 



functional description (con't) 

Clock In/Out 

This pin is either an input or output depending on the 
code at the Resolution Select inputs. If the pin is used as 
an output pin, it will output the clock frequency the 
Resolution Select inputs have selected. When used as an 
input, an external clock is used to clock the counters. 

Blanking Output 

This output is used to blank the display at the beginning 
and end of each digit time to allow for internal delay 
between two cascaded chips, see Figure 3. The display 
is blanked when the Blanking Output is at V DD . 



_T 



-fP 



'TTTir ir~ir~ irhrhnrnnr 



plex Output pin is four times the internal multiplex 
rate. To use the Multiplex Output pin, the Multiplex 
Input pin must be tied to V DD . The Multiplex Input 
must be used if the oscillator pins are not used. If the 
Multiplex Input pin is used, OSC IN, OSC OUT and the 
blanking output are not used. 

Control C 1 , C2 I n and Control C 1 , C2 Out 

These four input pins are used to cascade two chips 
together. When the Control C1 In pin is floating (inter- 
nal pull-up to V DD ) or tied to V DD , the clock pulses to 
counter 1 are inhibited. When Control C1 In is at V ss , 
counter 1 is enabled. Control C1 Out is at V ss when 
counter 1 is at it s maximum count, and it is floating 
at all other times. The Control C1 In pin must be 
floating (or connected to V DD ) while digit program- 
ming in Function 7. Control C2 pins operate on counter 
2 in a similar manner. 

Program Digits 1—4 

These four input pins are used to program or set any 
count desired in counter 1 in Functions 6 and 7. When 
Program Digit 1 is at V ss , the least significant digit of 
counter 1 advances at a 2.5 Hz rate. There is no carry- 
over from digit to digit. Program Digit 1 has no effect if 
tied to V DD or left floating (internal pull-up to V DD ). 
Only one Program Digit input may be held to V ss at 
a time. 



FIGURE 3. Blanking Output 

Oscillator In and Out 

A quartz crystal, resonant at 32.8 kHz, two capacitors 
and one resistor, together with the internal MOS circuits 
form a crystal controlled oscillator as shown in Figure 4. 
Varying one of the capacitors allows precise frequency 
settings. For test purposes, OSC IN is the input and OSC 
OUT is the output of an inverting amplifier. 






TtH[ 



^ 



H 



TO DIVIDER 



FIGURE 4. Crystal Oscillator 

Multiplex Input and Output 

The Multiplex Input pin allows an external multiplex 
rate to be used in the chip. The multiplex rate inside the 
chip is one fourth the Multiplex Input and Multiplex 
Output rate. When using the Multiplex Input pin, the 
Multiplex Output pin must be tied to V ss . The Multi- 



Program Digit 1/Latch Control 

This input has two functions; besides setting a count in 
digit 1 of counter 1 in Functions 6 or 7, it also affects 
Functions 3 and 4. In Functions 3 and 4, this input 
allows the display to show counter 2 counting as des- 
cribed in Functions 3 and 4. 

Program Digit 4/Waiting State Indicator 

This input besides setting a count in digit 4 of counter 1 
in Functions 6 and 7, also indicates that the chip has 
been reset and is in the stand-by mode at power-on. In 
Functions 1-5, the Waiting State Indicator is at V ss 
until a Start-Stop transition has occured. Once a Start- 
Stop transition has occured, the output remains at V DD . 

Leading Zero Blanking 

In Functions 1—5, leading zeros are blanked for both 
counters 1 and 2. In Functions 6 and 7, counter 2 has 
leading zero blanking. At power-on, the display is blank 
in Functions 1—5, and all zeros are displayed in Func- 
tions 6 and 7. 

Output Circuits 

For BCD and Digit Outputs, V ss is a logic one. Figure 5 
illustrates the circuit used for all outputs except for 
Control C1, C2 Out. The Control C1, C2 Out circuit is 
illustrated in Figure 6. Figure 7 illustrates the simple 
interface needed for an 8-digit stop-watch. Figure 8 
illustrates the MM5865 being used to count how many 
events occur in a specified time. Figure 9 shows the 
MM5865 as a simple industrial counter when the input 
clock is a constant frequency above 400 Hz. 



functional description (con't) 





FIGURE 5. Output Circuit 



FIGURE 6. Control CI Out Circuit 



"mm? 



■m — ►■ 



i_I 



1 1 4, 



TTT 



=1 



"W 



TT 



I I 



32.8 kHz 
~ 25 P Fl 



Display reads 12h 34m 56.78s 
Maximum time 99h 59m 99s 
Decimal point indicates waiting sta 



TTTii 



FIGURE 7. StopUVatch Application 



functional description (con't) 



ISO;! 

m> 



EVENT f 
(CLOCK IN) 



If 



PROGRAM 
DIGIT 



TT 



TT 



Hah' 

25 pF 



T 



J_L 



hi I I I I I I 



Display 15 events have occured in 1 minute 
Maximum events 99,999,999 
Maximum Time 99m 59s 



TTR5 



FIGURE 8. Application of MM5865 to Count Events in a Specified Time 



2U 



functional description (con't) 



-iJT. 



GNDO- 
+10V O- 



J_L 



«i I I I I i 



li I I I I I I I I hoi I 



jj I I ti 



Display readsa count of 1234 
Maximum couni 9999 



FIGURE 9. Industrial Counter 



2-19 



CO 

in 



a 



Counters/Timers 



MM53107 T7-stage oscillator/divider 



general description 



features 



The MM53107 is a low threshold voltage CMOS 
integrated circuit with 17 binary divider stages that can 
be used to generate a precise 60 Hz reference from a 
2.097152 MHz quartz crystal. An internal pulse is 
generated by the combinations of stages 1—4, 16 and 
17 to set or reset the individual stages. The number 
the circuit will divide by is 34,952. The MM53107 is 
advanced one count on the positive transition of each 
clock pulse. One buffered output is available: the 17th 
stage 60 Hz output. The MM53107 is available in an 
8-lead dual-in-line epoxy package. 



Divides by 34,952 

Input frequency-2. 097152 MHz 

Output frequency— 60 Hz 

Crystal oscillator 

High speed (2 MHz at V D D = 2.5V) 

Wide supply range 2— 6V 

Low power (0.5 mW @ 2 MHz/2. 57) 

Fully static operation 

8-lead dual-in-line package 



block and connection diagrams 



typical performance characteristics 



Dual-ln-Line Package 

V 0D TJC 0SC OUT 0SC IN 





DSC 














0SCIN 


175TAGE DIVIDER 




BUFFER 
























?E 


' ' 


I 








RESET PULSE GENERATOR 





DIVIDER 
' OUTPUT 



t t 




DIVIDER V s s NC MC 

OUTPUT 

TOP VIEW 

FIGURE 2 

Order Number MM53107N 
See Package 17 



Typical Current Drain vs 
Oscillator Frequency 




2-20 



absolute maximum ratings 

Voltage at Any Pin 

Operating Temperature 

Storage Temperature 

Package Dissipation 

Maximum Vcc Voltage 

Operating Vcc Range 

Lead Temperature (Soidering, 10 seconds) 



-0.3V to Vcc + 0.3V 

0°C to +70°C 

-65°Cto+150°C 

500 mW 

6V 

2.5V to 6V 

300°C 



electrical characteristics 

Ta within operating temperature range, Vgs = Gnd, 2.5V < Vqd < 6V unless otherwise specified. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Quiescent Current Drain 


V D D=6V 






10 


MA 


Operating Current Drain 


V DD = 2.5V, f in = 2.1 MHz 






200 


ma 


Frequency of Oscillation 


V DD =2.4V 


dc 




2.1 


MHz 




V DD =6V 


dc 




4.0 


MHz 


Output Current Levels 












Logical "1 " Source 


V DD = 4V, 


100 






MA 


Logical "0 " Sink 


V UT=2V 


100 






ma 


Output Voltage Levels 












Logical "1" 


V DD =6V 


5.0 






V 


Logical "0" 


Iq= 10mA 






1.0 


V 



functional description 

A connection diagram for the MM53107 is shown in 
Figure 2 and a block diagram is shown in Figure 1. 



TIME BASE 

A precision time base is provided by the interconnection 
of a 2,097,152 Hz quartz crystal and the RC network 
shown in Figure 3 togethe- with the CMOS inverter/ 
amplifier provided between the Osc In and the Osc Out 
terminals. Resistor R1 is necessary to bias the inverter 
for class A amplifier operation. Capacitors CI and C2 
in series provide the parallel load capacitance required 
for precise tuning of the quartz crystal. 



The network shown provides > 100 ppm tuning range 
when used with standard crystals trimmed for C|_ = 
12 pF. Tuning to better than ±2 ppm is easily obtainable. 

DIVIDER 

A pulse is generated when divider stages 1—4, 16 and 17 
are in the correct state. This pulse is used to set or reset 
individual stages of the counter, the modulus of the 
counter is 34,952. 

OUTPUT 

The Divide Output is the input frequency divided by 
34,952. The output is a push-pull output. A typical 
application of the MM53107 is shown in Figure 5. 



i> 



-Wv- 

R1 
20M 



V DD 0RV SS 



«ss— • 



D 



2,097,152 Hz 
36 pF C L M2pF 



1 



To oe selected based on the crystal used 
FIGURE; 3. Crystal Oscillator Network 



FIGURE 4. Duty Cycle 



2-21 



functional description (Continued) 



Jam 



6-3S.F Ji1»«f 



If h 



T 



MANUAL TV "ON" 



MANUAL TV "OFF" 



DISPLAY SELECT 



" V f \ 50/6DHZ 

^S ^ SELECT 



NORMALLY 

HARDWIRED 

FDR EACH 

APPLICATION 



BCD 1 

6ET32 
BfJtU 
BcTSb 



-ww|^_ 



Note. V SS of MM53107 and 
MM53100 are common. 



JUL 



FROM TV 
HORIZONTAL 

RETRACE 




FIGURE 5. Typical Application TV Channel and Time Display 



2-22 



a 



Counters/Timers 



MM 586 5 Universal Timer Applications 



introduction 



A single chip universal counter and timer is now available 
from National Semiconductor Corporation through 
distributors of their products. 

The MM5865 universal timer contains, in one 40-pin 
package, two 4-digit counters, oscillator, 18-stage divider, 
multiplexer, and all the logic required to control the 
counters, blank leading zeros, compare the two counters, 
program one of the counters, and cascade two MM5865 
integrated circuits 

The MM5865 provides input pins for seven modes of 
timing and/or counting operations. When the chip is 
used as a timer, two input pins may be programmed to 
provide a display resolution of 0.01 second, 0.1 second, 
1 second, or external clock. In addition, the modulo by 
which the counters divide may be programmed using 
three divide scaler input pins. 

The outputs include the comparator output, multiplexed 
BCD segment outputs, and digit enable. The BCD seg- 
ment outputs interface directly with the MM 14511 
(CD4511), a BCD to 7-segment latch/decoder/driver 
which interfaces with an LED display. The digit enable 
outputs of cascaded MM5865s interface directly with a 
DS8863 (DM8863), an MOS to LED 8-digit driver. A 
single MM5865 interfaces directly with a DS8877 or 
DS75492 6-digit driver. 

When a suitable crystal is used with the MM5865 oscil- 
lator, the counters of a single chip (or those of two chips 
cascaded) may be used as timers with the following 
functions: 

1. Counter 2: Start-Stop timing 
Counter 1: Total elapsed time 

2. Counter 2: Start-Stop timing 
Counter 1 : Total accumulated time 

3. Counter 2: Sequential event timing 
Counter 1 : Total elapsed time 

4. Counter 2: Split-timing with total elapsed time 
Counter 1 : Not actively used 

5. Counter 2: Total accumulated time 
Counter 1: Total elapsed time 

6. Counter 2: Up counter 
Counter 1 : Programmable counter 

7. Counter 2: Programmable down counter 
Counter 1 : Not actively used 



Therefore, one or two MM5865s along with two other 
integrated circuits and a 4- or 8-digit display may be 
used in the following applications: 

1. Photographic enlarger timer, with each digit indi- 
vidually programmable 

2. Stopwatch 

3. General purpose timer 

4. Event timer/counter 

5. Rally timer 

6. Navigational timer 

7. Industrial timer/counter 

The MM5865 may also be used as a frequency counter, 
or it may be used as the time reference of a larger 
frequency counter. The maximum oscillator frequency 
of the MM5865 is 80kHz; the maximum clock input 
frequency is 100kHz. 



how the MM5865 operates 

As can be assumed from the brief description above, the 
MM5865 is a very powerful integrated circuit, capable 
of many applications. Therefore, in order to fully stim- 
ulate the imagination of readers, its repertoire will be 
presented in detail. 

A block diagram of the MM5865 universal timer is shown 
in Figure 7, and the connection diagram is shown in 
Figure 2. As nearly as possible, all technical terms in the 
following discussion conform to definitions presented 
in the Radio Shack Dictionary of Electronics, edited by 
Rudolf F. Graf. 

Multiplexer 

Because of the internal multiplexer, only one BCD to 
7-segment latch/decoder/driver need be used to inter- 
face one or two MM5865s to a suitable display. The 
multiplexer may be controlled in three ways. 

An externally generated multiplex frequency may be 
applied to the Multiplex Input pin of the MM5865. An 
external clock is then applied to the Clock Input pin. 
(For example, an LM555C may be used as a square-wave 
oscillator to provide the necessary input to pin 23.) 



2-23 



00 
CO 

I 

z 
< 



PROGRAM 
DIGITS 1-4 



DIVIO 

SCA 



CONTROL CI IN 

CONTROL C2 IN 

RESET 

START/STOP 

FINAL EVENT 




COMPARATOR ENABLE 



MULTIPLEX OUT ^- 
MULTIPLEXIN — 



CLOCK IN/OUT 



RESOLUTION 

SELECT 2 



CONTROL 
LOGIC 



rr> 



JJ 



COMPARATOR 

DISPLAY SELECT, 

LATCHES. MULTIPLEXER 

AND LEADING 

ZERO BLANKING 



2 




-^ CONTROL CI OUT 



BCD OUTPUTS 



DIGIT OUTPUTS 



-"► CONTROL C2 OUT 



MULTIPLEXER 



4*4- 



OSCIL- 
LATOR 



r?TFn 



^ OSCIN 

► OSCOUT 



RESOLUTION 
SELECT 



-^ BLANKING 



Figure 1 . Internal block diagram of the MM5865 Universal Timer. 



DIVIO; SCALER 1 1 


W 


!L« 


DIVIDE SCALER 2 1 




2L- PROGRAM DIGIT 1,'LATCH CONTROL/LSD 


DIVIDE SCALER 3 




-—PROGRAM DIGIT 2 
— PROGRAM DIGIT 3 


COMPARATOR ENABLE - 




FUNCTION 1 




-^—PROGRAM DIGIT 4/Vi'AITING STATE/MSD 
3b 

■——CONTROL CI IN 
i CONTROL CI OUT 

31 e ™ 2 A '■ J SEGMENTS 
-_BCO^ 


FUNCTION 2 




FUNCTION 3 




FUNCTION,,— | 




FUNCTION 5-—T 
FUNCTION 6 — - 


MM 586 b N 


FUNCTION 7 




— BCD B ; 

^| — DIGIT 1.-LSUMM586S/N 


ENrSTOP.'COMPAFATOR OUT — 1£ 




RESET 




START 'STOP 




CLOCK IN'OUT 




— DIGIT 1'MSU 
i^— CONTROL C2 OUT 


RESOLUTION SELECT 1 




RESOLUTION SELECT2 — — 




ii— CONTROL C2 IN 
-2— MULTIPLEX IN 
JS-WILTIfLEXOUT 


BLANKING— — 




OSCIN — 
OSCOUT 






— »D0 



Figure 2. MM5865 connection diagram. 



When an external multiplex rate is applied to the Multi- 
plex Input pin, the Multiplex Output pin must be con- 
nected to Vss- a ncl tne Oscillator In.. Oscillator Out, and 
Blanking pins should be floating. The multiplex rate 
inside the chip is one fourth the frequency applied to 
the Multiplex Input pin. In this mode of operation two 
MM 586 5s may not be cascaded. In fact, to make use of 
the Multiplex Output pin, the Multiplex Input pin must 
be connected to Vqq. The frequency at the Multiplex 
Output pin is the same as that applied to the Multiplex 
Input pin. 

The multiplexer may also be controlled by using internal 
MOS circuits to form a crystal controlled oscillator. To 
form the oscillator a crystal, two capacitors, and one 
resistor must be added externally. One of the capacitors 
should be variable to allow precise frequency settings. 
When these external components are connected to the 
Oscillator Input and Oscillator Output pins, the Multi- 
plex input pin must be connected to Vql> 
When the input clock is at a constant frequency above 
400Hz the Multiplex Input pin may be connected to the 
Clock Input pin. In this mode of operation the input 
clock which is being counted is also used as the exter- 
nally generated multiplex frequency. The multiplex 
rate inside the chip will be one fourth the clock input 
frequency as described above. 



2-24 



Oscillator 

Figure 3 shows how external components may be 
connected to the Oscillator Input and Output pins. A 
frequency counter used to adjust the frequency of the 
oscillator may be connected to the Oscillator Output pin 
through a 50pF capacitor. 



vss 



7" 



1 1 



ti 



^ 



♦-►to 

DIVIDER 
CIRCUITS 



-T *" 

I EXTERN, 

I" 



Figure 3. Crystal oscillator connections. 



Divider 

The divider stages produce the blanking output by 
dividing the oscillator input frequency by 41. This 
output is used to biank the display at the beginning and 
end of each digit time to allow for internal delay between 
two cascaded chips. The display is blanked when the 
Blanking Output is at V DD . 

The divider stages then divide the blanking output by 2 
to generate the Multiplex Output. The frequency which 
appears at the Multiplex Output pin is further reduced in 
frequency by the divider stages so that the Resolution 
Select pins may be used to program the resolution of the 
display. Table I shows how these two inputs are used to 
select the frequency of the internal clock pulses to be 
applied to the two counters. The frequencies and display 
resolutions for an oscillator frequency of 32.8kHz are 
given. 



Control Logic 

The block labeled "Control Logic" contains the logic 
required to select one of the seven functions, reset all 
logic and counters, start and stop the counters, indicate 
that a final event has occurred, and display counter 2 in 
Functions 3 and 4. 

The selection of a function is accomplished by connect- 
ing one of the seven function pins to Vss; the other six 
function pins are left floating. 

The Reset Input will reset all logic and counters in 
Functions 1-5 and Function 7. In Function 6, Reset 
will reset logic and counter 2, but not counter 1. For 
reset to occur the Reset pin must be momentarily 
connected to Vgg. Internal control logic provides power- 
on reset, however, to insure proper power-on resetting 
of all logic and the counters a 10/jF, 35V Solid Tantalum 
Capacitor (Allied - 852-5680) should be used across the 
Vss~ Vdd P° wer busses. 

In Function 6, the Reset Input pin may be connected 
to the Comparator Output pin in order to automatically 
reset logic and counter 2. When this connection is made, 
a Start/Stop transition is all that is needed to repeat the 
up count of counter 2. 

The Start Stop Input is used to control the counters by 
momentarily connecting pin 14 to Vgs- The manner in 
which this input affects the counters during the execu- 
tion of each function will be explained as the descrip- 
tions of the functions are given. 

The Final Event Stop/Comparator Output pin is used to 
indicate to the circuit that no more events will be timed 
or counted. Final Event Stop affects the circuit when it 
is momentarily connected to Vgg. When this pin is used 
as the comparator output, a V S s level at the pin indicates 
comparison between the two counters. 

Additional Control Logic 

The three Divide Scaler inputs permit the counters to 
be programmed to count in Modulo 6 or Modulo 10. 
Table II shows the possible codes which may be applied 
to the Divide Scaler pins. A zero indicates that the pin 
is left floating {or connected to V DD ); a one indicates 
that the pin is connected to Vss- 



Table I. Resolution Select Code. A zero indicates that the pin is 
left floating for connected to Vq[)); a one indicates that the pin 
is connected to Vgg- Note that when an external clock is applied 
to pin 15, pins 16 and 17 must be connected to Vss- 



Table II. Divide Scaler Code 



Resolution Select 


Frequency of 
Clock to Counters 


Display Resolution 


Pin 16 


Pin 17 





1 
1 



1 


1 


100 Hz 

10Hz 

1Hz 

External 


0,01 sec 

1 sec 

1 sec 



The Clock Input/Output pin is either an input or an out- 
put depending on the code at the Resolution Select input 
pins. If the pin is used as an output it will output the 
clock frequency selected by the program applied to pins 
16 and 17. When it is used as an input an external clock 
must be used to clock the counters. 



Divide 










Modu 


lo 




Scaler 


Counter 1 


Counter 2 


Pin 






Di 


git 






Digit 


1 2 


3 


4 


3 


2 


1 


4 


3 2 1 








10 


10 


10 


10 


10 


10 10 10 


1 





6 


10 


10 


10 


6 


10 10 10 


1 





10 


6 


10 


10 


10 


6 10 10 


1 1 





10 


10 


6 


10 


10 


10 6 10 





1 


10 


10 


10 


10 


10 


10 10 10 


1 


1 


10 


10 


10 


10 


6 


10 10 10 


1 


1 


10 


10 


10 


10 


10 


6 10 10 


1 1 


1 


10 


10 


10 


10 


10 


10 6 10 



A zero indicates that the pin is left floating (or connected to 
Vprj); a one indicates that the pin is connected to Vss 



2 25 



For example, if the Resolution Select pins are program- 
med to give a 1 second display resolution (code "10") in 
a stopwatch application, and if the Divide Scaler code is 
"110," then the maximum possible count for both 
counters 1 and 2 would be 9959 (99 min, 59 sec). This 
means that the unit minutes display will advance by one 
digit every 60 seconds. 

Connecting pin 4 to Vss enables the comparator. In 
functions 1 -5 the Comparator Enable pin must be left 
floating (or connected to Vrjrj). In function 6 the 
Comparator Enable pin must be connected to V$s after 
digit programming; if the Comparator Enable pin is con- 
nected to Vss (comparator enabled) at power on, the 
Reset pin must be momentarily connected to Vss before 
a Start/Stop transition will begin the counter 2 count-up. 

In function 7, if the Comparator Enable pin is floating 
(or connected to Vpp) when power is applied to the 
chip, or when the function switch is switched to func- 
tion 7, the Comparator Enable pin must be connected to 
Vss after digit programming as in function 6; however, 
in function 7, if the Comparator Enable pin is connected 
to Vss (comparator enabled) at power on (or when the 



function switch is switched to function 7), the compara- 
tor must be disabled by 1 ) disconnecting the Comparator 
Enable pin from Vss- and 2} momentarily connecting 
the Reset pin to Vss; this must be done before the digits 
are programmed. This is necessary, of course, because 
connecting the Reset pin to Vss after digit programming 
will simply reset counter 1 to "0000." In function 6, a 
Reset transition after digit programming does not reset 
counter 1 to "0000." 

In addition, the Control C1 In pin (pin 35} must be 
floating (or connected to Vqd) during digit programming 
in function 7. After digit programming, the Control C1 
In pin must be connected to Vss before the count-down 
begins. A DPDT, Center "OFF" switch connected as 
shown in Figure 4, may be used to control both the 
Comparator Enable pin and the Control C1 In pin. In 
one position the DPDT switch connects the Control C1 
In pin to Vss f° r functions 1 - 5. Digit programming may 
be accomplished in function 7 by placing the switch in 
the Center "OFF" position. In the third position both 
the Comparator Enable and the Control C1 In pins are 
connected to Vss f° r functions 6 and 7. 







S11>^NUAL S12 "(_ START/STOp 



Figure 4. Stopwatch/Timer application showing the connections for a single MM5865. Two cascaded MM5865s may also be used, as 
described in the text. 



2-26 



Pins 36-39, the Program Digit 1-4 pins, are used to 
program a desired count into counter 1 when using 
functions 6 and 7. When any of the four Program Digit 
pins are connected toV ss , the display digit of counter 1 
associated with that pin advances at a 2.5 Hz rate (assum- 
ing the oscillator frequency is 32.8kHz). The Program 
Digit 1 pin advances the least significant digit of counter 
1 ; the Program Digit 4 pin advances the most significant 
digit. There is no carry over from digit to digit, and only 
one Program Digit Input may be connected to Vgs at 
a time. 

The Program Digit 1 pin also functions as a counter 2 
latch control in functions 3 and 4. In functions 3 and 4, 
momentarily connecting the Program Digit 1 /Latch 
Control pin to Vgg permits the display to show counter 
2 counting. 

The Program Digit 4 pin also serves two purposes; in 
functions 1 -5 this pin indicates that the chip has been 
reset and is in the standby mode at power-on. Visual 
indication of this condition may be accomplished by 
connecting a transistor between the Program Digit 4/ 
Waiting State Indicator pin and the Segment DP Anode 
of a multiplexed display. With the transistor connected 
as shown in Figure 4, the Waiting State Indicator pin will 
be at Vg S at power-on until a Start/Stop transition 
occurs. After a Start/Stop transition occurs, the Waiting 
State Indicator pin will remain at Vqq until power is 
removed from the chip. 

Leading Zero Blanking 

In functions 1-5, leading zeros are blanked for both 
counters. In functions 6 and 7, counter 2 has leading 
zero blanking but counter 1 does not. At power-on the 
display is blank (or ali decimal points if the Waiting 
State Indicator pin is used) in functions 1 -5; ali zeros 
are displayed in functions 6 and 7. 

Control C1, C2 In and Control C1, C2 Out 

These four pins are used to cascade two chips together. 
In this mode of operation the primary MM5865, which 
is directly controlled by the crystal oscillator, connects 
to another MM5865 in the following manner: the 
Control C1 In pin of the primary chip is connected 
to Vgs except during digit programming in function 7; 
the Control C1 Out pin connects to the Control C1 In 
pin of the other MM5865; the Control C2 In pin of the 
primary chip is connected to V S s; the Control C2 Out 
pin connects to the Control C2 In pin of the other 
MM5865; the Control C1 Out and the Control C2 Out 
pins of the second chip are left floating. 

When the Control C1 In pin is floating (or connected 
to V DD ), the clock pulses to counter 1 are inhibited. 
When the Control C1 In pin is connected to Vgg, counter 
1 is enabled. Control CI Out is at V ss when counter 1 is 
at its maximum count, and it is floating at all other 
times. The Control C2 pins affect counter 2 in a similar 
manner. 

Other possible connections between the two chips are: 
1} all function pins connected together, 2) pins 12, 13, 
14, and 15 connected together, 3) all BCD pins con- 
nected together, and 4) pins 39 connected together in 
functions 1 - 5 only. 

When two MM5865s are cascaded as described above, 
eight momentary switches or individual electrical signals 



must be provided if every digit of the display is to be 
programmable. In addition, another switch would have 
to be provided to break the pin 39 connection between 
the two chips in functions 6 and 7. Of course, all of the 
switching action could be provided by one ganged 
rotary switch if desired; even the function 6 Reset to 
Comparator Out connection could be accomplished if 
the proper switch were used. 

Electrical Characteristics 

The maximum supply voltage which may be connected 
between V ss and V DD (V DD = OV) is 20V. National 
specifies that the minimum voltage at which the chip 
will operate is 7V; however, some chips will operate well 
down to Vss ~ 5V. With a 9V transistor battery used as 
the power supply, and display inhibited, the power 
supply current will be approximately 7mA to 15mA for 
a one-chip stopwatch. 

The maximum input frequency at the oscillator is 80kHz; 
however, the oscillator and dividers are designed for stop- 
watch applications using a 32.8kHz crystal. (A 
32.768kHz crystal, available from Quest Electronics, 
P.O. Box 4430 E, Santa Clara, CA 95054, may be used 
without much loss in accuracy.) 

Drivers must be provided forthe Digit and BCD Outputs. 
Two MM5865s interface directly with the MM14511 
Segment Driver and the DS8863 Digit Driver. A DS8877 
or DS75492 Hex Digit Driver may be used with a single 
MM5865. 

The Seven Functions 

The one-chip circuit shown in Figure 4 indicates all 
connections necessary to employ the MM5865 as a 4- 
digit stopwatch/timer. The seven available functions will 
be described using this figure, in which the desired 
function is selected by switching S5. When necessary, 
refer also to Figures 1 through 3. 

Function 1 

In function 1, at power-on (S1 closed) four decimal 
points are visible on the display, indicating that the 
counters have been reset, but not necessarily all logic. 
If the Comparator Enable pin is connected to Vss (S3 
in Function 6*7 position) at power-on, a Start/Stop 
transition (obtained by momentarily closing S12) will 
cause the decimal points to disappear from the display; 
however, the chip will not begin counting. First it is 
necessary to place S3 in the Functions 1-5 position, 
then to reset the logic (by momentarily closing S11). 

Once all logic is reset (either by applying power with S3 
in the Functions 1-5 position or by the method dis- 
cussed above), a Start/Stop transition will cause both 
counters to begin counting up. The up-count of counter 
2 is displayed, the least significant digit advancing at a 
1 Hz rate. A second Start/Stop transition inhibits the 
clock pulses to counter 2 and stores and displays the 
contents of counter 2; however, counter 1 continues to 
count. A third Start/Stop transition resets counter 2, 
enables clock pulses to counter 2 and, again, displays 
counter 2 counting up. Subsequent Start/Stop tran- 
sitions repeat this sequence. Counter 1 continues to 
count, from the time of the first Start/Stop transition, 
until the occurrence of a Final Event Stop transition 
(obtained by momentarily closing S10). A Final Event 



: -27 



Stop transition inhibits the clock pulses to both counters 
and displays counter 2. After this Final Event Stop 
transition has occurred, a Start/Stop transition switches 
the display from counter 2 to counter 1. Each subse- 
quent Start/Stop transition alternately displays one of 
the counters. 

To summarize, in function 1 both counters start counting 
up with an initial Start/Stop transition. Counter 1 
continues to count (recording total elapsed time) until 
a Final Event Stop transition. Counter 2 (alternately) 
starts, then stops counting with each Start/Stop transi- 
tion (timing as many intervals as desired), until a Final 
Event Stop transition. Any time a Reset transition 
occurs both counters are reset to "0000" and the display 
blanks. 



Function 2 

The only difference between functions 1 and 2 is that in 
function 2, whenever a Start/Stop transition inhibits the 
clock pulses to counter 2, the clock pulses to counter 1 
are also inhibited. Start/Stop transitions which reset 
counter 2 and enable clock pulses to counter 2 also 
enable clock pulses to counter 1; counter 1 does not 
reset, however. The up-count in counter 1 resumes at the 
stored count; therefore, counter 1 records total accumu- 
lated time. 

Function 3 

In function 3 the power-on conditions are the same as 
those in functions 1 and 2. Once all logic is reset a Start/ 
Stop transition causes both counters to begin counting 
up Counter 2 is displayed counting. A second Start/Stop 
transition stores and displays the contents of counter 2, 
resets counter 2, and initiates a new up-count. However, 
the new up-count is not displayed. Counter 1 continues 
to count. The initial count remains displayed until a 
third Start/Stop transition. This third Start/Stop transi- 
tion and subsequent Start/Stop transitions repeat the 
sequence described above, indicating the length of time 
between successive Start/Stop transitions. 

The occurrence of a Latch Control transition (obtained 
by momentarily closing S5) any time after the second 
Start/Stop transition will cause counter 2 to be displayed 
while counting. The count will continue to be displayed 
until a Start/Stop transition. This Start/Stop transition 
also stores and displays the contents of counter 2 and 
then resets counter 2. As before, counter 1 continues to 
count, but counter 2 begins a new count. 

A Final Event Stop transition inhibits the clock pulses 
to both counters and displays the contents of counter 2. 
A Start/Stop transition occurring after the Final Event 
Stop transition switches the display from counter 2 to 
counter 1. Repetitive Start/Stop transitions switch the 
display between counter 2 and counter 1. Any time a 
Reset transition occurs, both counters are reset to 
"0000" and the display blanks. 



Function 4 

In function 4 the power-on conditions are the same as 
those in functions 1 -3. Once all logic is reset a Start/ 
Stop transition causes counter 2 to begin up-counting. 
Counter 2 is displayed counting. A second Start/Stop 



transition stores and displays the contents of counter 2. 
Subsequent Start/Stop transitions update the display of 
counter 2. A Latch Control transition will display 
counting until the occurrence of a Start/Stop transition. 
This Start/Stop transition, following the Latch Control 
transition, does not reset counter 2 as it does in function 
3. Rather, counter 2 continues to count up. A Final 
Event Stop transition inhibits the clock pulses to 
counter 2 and displays the contents of counter 2. A 
Reset transition at any time resets counter 2 to "0000." 



Function 5 

Again, in function 5 the power-on conditions are the 
same as those in functions 1 -4. Once all logic is reset a 
Start/Stop transition causes both counters to begin 
counting up. Counter 2 is displayed counting. A second 
transition on the Start/Stop pin inhibits the clock pulses 
to counter 2, and the contents of counter 2 are dis- 
played. Counter 1 continues to count. A third Start/ 
Stop transition enables the clock pulses to counter 2; 
counter 2 resumes counting where it left off, and counter 
2 is displayed counting. 

Subsequent Start/Stop transitions repeat this sequence 
with counter 1 counting continuously. A Final Event 
Stop transition inhibits the clock pulses to both counters 
and displays counter 2. A Start/Stop transition switches 
the display from counter 2 to counter 1. Repetitive 
Start/Stop transitions switch the display between 
counter 2 and counter 1 . A Reset transition at any time 
resets both counters to "0000." 



Function 6 

At power-on in function 6, counter 1 is displayed with 
"0000." If the comparator is enabled (S3 in the 
Function 6-7 position) at power on, a Reset transition 
(obtained by momentarily closing S11) is necessary 
before a Start/Stop transition can begin the counter 2 
count-up. 

Counter 1 is programmed to the desired count by 
holding each of the four Digit Programming Switches 
Closed in turn. The comparator must then be enabled by 
placing S3 in the Function 6-7 position (unless it was 
already enabled at power-on). Counter 2 is displayed 
counting up beginning with a Start/Stop transition. 
When counter 2 is coincident with counter 1, the clock 
pulses to counter 2 are inhibited, the contents of 
counter 2 are displayed, and the Comparator Output is 
enabled. A Reset transition after the counter 2/counter 1 
coincidence disables the Comparator Output and 
displays counter 1 with the programmed time. The Reset 
transition can be obtained either by momentarily 
closing S11 or by connecting the reset Input pin to the 
Comparator Output pin after Digit Programming so that 
logic and counter 2 are reset automatically whenever 
counter 2 is coincident with counter 1. 

After each Reset transition, subsequent Start/Stop 
transitions repeat the sequence. Counter 1 may be re- 
programmed after any Reset transition, if desired. If a 
Reset transition occurs while counter 2 is counting up, 
the clock pulses to counter 2 are inhibited, counter 2 
is reset, and counter 1 is displayed with the programmed 
time. 



2-28 



If a Start/Stop transition occurs while counter 2 is 
counting up, the clock pulses to counter 2 are inhibited 
and counter 1 is displayed with the programmed time. 
With the next Start/Stop transition, counter 2 resumes 
counting where it was stopped. 

If the Reset Input pin is not connected to the 
Comparator Output pin and if a Final Event Stop tran- 
sition occurs while counter 2 is counting up, the clock 
pulses to counter 2 are inhibited and the contents of 
counter 2 are displayed. The next Start/Stop transition 
displays counter 1 with the programmed time. Repeti- 
tive Start/Stop transitions switch the display between 
counter 2 and counter 1 . A Reset transition followed by 
a Start/Stop transition starts the counter 2 up-count 
sequence again. 

In function 6, and also in function 7, the digit which is 
preprogrammed to count in Modulo 6 cannot, of course, 
be programmed to a digit greater than 5. 



output drive capability of 25mA. The DS8863 is an 
8-digit driver; each driver is capable of sinking up to 
75mA. The MM14511 may be operated at supply 
voltages up to 15V; however, the DS8863 cannot be 
operated with supply voltage greater than 10V. For 
operation with supplies up to 18V, the DS8963 is a 
direct replacement for the DS8863. 

The NSA398 is a 9-digit common cathode LED numeric 
display with a 1/8-inch character height. Eight inputs 
are provided for selection of the appropriate segments 
and decimals (anodes) and nine inputs for digit 
(cathodes) selection. The anodes are internally inter- 
connected for multiplexing. The NSA398 has a red 
faceplate which provides excellent visual contrast and 
ease of visibility over a wide angle. Figure 5 shows the 
physical dimensions and pin connections of the NSA398. 



Function 7 

In function 7 counter 1 is displayed with "0000" at 
power-on. If S3 is in the Function 6-7 position at 
power-on, it must be placed in the "OFF" position; 
then S1 1 must be momentarily closed. Counter 1 is 
set to a specific count by holding each of the four Digit 
Programming Switches closed in turn; then the 
Comparator must be enabled by placing S3 in the 
Function 6 - 7 position. 

Counter 1 counts down from the set count beginning 
with a Start/Stop transition. When counter 1 counts 
down to zero the clock pulses to counter 1 are inhibited 
and the Comparator Output is enabled. This is not 
repeatable without a new count being entered into 
counter 1. A Final Event transition halts the counter 1 
down-count, and subsequent Start/Stop transitions have 
no effect on counter 1 or counter 2. A Reset transition 
resets counter 1 to "0000." 



Peripheral 

The other components shown in Figure 4 consist of 
input/output interfaces between the user and the 
MM5865. The crystal used in this stopwatch timer 
circuit is a watch crystal cut to oscillate at 32.768kHz. 
(A 32.8kHz crystal would be best.) This means that the 
blanking frequency is 799.2 Hz, the multiplex frequency 
is 399.6Hz, and the clock frequency to the counters is 
0.99902Hz. 

The oscillator frequency may be adjusted by connecting 
a counter to pin 20 of the MM5865 through a 50pF 
capacitor and then varying the capacitance of C3. Any 
attempt to alter the values of R1 , C2, or C3 will probably 
fail; that is, the oscillator will probably not oscillate. 

Most of the switches which control the MM5865 are 
momentary push-buttons which are available from many 
sources. The function switch, however, is a very small 
8-position switch in a TO-5 package; it is available from 
James Electronics, P.O. Box 822, Belmont, CA 94002. 

The 2N4400 (a 2N3904 can also be used) drives the 
decimal point anode of the display and is itself driven 
by the Waiting State output of the MM5865. 

The MM14511 provides the functions of a 4-bit storage 
latch, an 8421 BCD-to-seven segment decoder, and an 



practical applications of the 
stopwatch/timer 

Now that the basic operation of the MM5865 has been 
presented, it is possible to examine practical applications 
of the seven function universal timer shown in Figure 4. 
This timer, as shown, has a maximum timing capability 
of 99 minutes, 59 seconds. If another MM5865 is added 
to the circuit, this timing capability may be extended to 
99 hours, 59 minutes, 99.99 seconds. For very accurate 
timing, the crystal should be cut to oscillate at 32.8kHz, 
and the oscillator frequency should be precisely tuned 
to 32.8kHz. 

When the stop watch /timer is being used to time any 
event, the display should be disabled with S2 as much 
as possible so that battery power will be conserved. 

Function 1 may be used to time two events occurring 
simultaneously in the following manner. A driver often 
travels from his heme to a city some hours away. On the 
way he passes a small town about halfway between his 
home and the city. He wishes to know how long it takes 
him to travel from his home to the small town, how long 
it takes to travel from the town to the city, and finally, 
how long it takes him to travel from his home to the 
city. 

At the beginning of the trip the driver presses the Start/ 
Stop switch. The display begins to record the time 
accumulating in counter 2. As he passes through the 
small town he presses the Start/Stop switch again and 
records the traveling time from his home to the town. 
Then he presses the Start/Stop switch again. As he 
arrives at the city he presses the Final Event Stop switch 
and records the time shown in the display as being the 
traveling time from the town to the city. He then 
presses the Start/Stop switch and sees in the display the 
traveling time from his home to the city. 

Function 2 may be used to record the total accumulated 
time of several events while each event is being timed 
individually. For example, a television repairman spends 
his day ordering parts, talking to customers, and repair- 
ing televisions on the bench. He wants to record the time 
he spends repairing each set so that customers may be 
properly billed, and he wishes to record his total bench 
time for the day. 



2-29 









'H 









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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 

FRONT VIEW 



flED FACE PLATE 









t 




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1 








5/32"- 


«— 1 


► 



PIN CONNECTIONS 

PIN NC 

PIN 1 DIGIT 1 CATHODE 

PIN 2 SEGMENT C ANODE 

PIN 3 DIGIT 2 CATHODE 

PIN 4 SEGMENT OP ANODE 

PIN 6 DIGIT 3 CATHODE 

PIN 6 SEGMENT A ANODE 

PIN 7 DIGIT 4 CATHODE 

PIN 8 SEGMENT E ANODE 

PIN 9 DIGIT 5 CATHODE 

PIN 10 SEGMENT D ANODE 

PIN 11 DIGIT 6 CATHODE 

PIN 12 SEGMENT G ANODE 

PIN 13 DIGIT 7 CATHODE 

PIN 14 SEGMENT 8 ANODE 

PIN 15 DIGIT 8 CATHODE 

PIN 16 SEGMENT F ANODE 

PIN 17 DIGIT 9 CATHODE 




• DP 



SEGMENT 
DESIGNATION 



Figure 5. Physical dimensions and pin connections of the NSA398. 



At the beginning and end of every bench job he presses 
the Start/Stop switch to record the time for each job. At 
the end of his day he presses the Final Event Stop switch, 
then the Start/Stop switch to record his total bench 
time. 

As an example of a function 3 application, consider an 
assembly line position at which a worker must fasten 
three parts to a piece of equipment. A supervisor wishes 
to record the time it takes the worker to fasten each part 
and the amount of time the equipment spends at this 
position. 

As the worker receives the piece of equipment, the 
supervisor presses the Start/Stop switch. The display 
begins counting up. As the worker finishes with the 
first part, the supervisor presses the Start/Stop switch. 
This time will remain in the display until the next Start/ 
Stop transition; the supervisor therefore has a chance to 
record the first event time. 

As the worker finishes with the second part, the super- 
visor presses the Start/Stop switch again and records the 
time of the second event. After the worker finishes with 
the third part the supervisor presses the Final Event 
Stop switch. The display will show the third event time. 
The supervisor can then press the Start/Stop switch to 
record the total time this worker handled the equipment. 



With function 4, the total time of an event may be 
accumulated, and the display may be updated while 
counter 2 is accumulating the total time. For example, 
a long distance runner desires to pace himself over a 5- 
mile run. As he starts out he presses the Start/Stop 
switch. Then, as he passes known checkpoints, he presses 
the Start/Stop switch to update the display and note the 
time of arrival at each check point. At the end of the 5- 
mile run he presses the Final Event Stop switch to 
record the total time for the run. 

Function 5 may be used to record both total accumu- 
lated time and total elapsed time. As an example of an 
application of function 5, consider a pilot who wants to 
record total flying time as well as total trip time. 

As the pilot starts out he presses the Start/Stop switch. 
He then presses the Start/Stop switch each time he lands 
and each time he resumes flying. At the end of his trip 
he presses the Final Event Stop switch and records total 
flying time. He then presses the Start/Stop switch to 
record total trip time. 

With proper interfacing, function 6 can be used as an 
enlarger timer. A photographer programs the desired 
printing time into the display with the Digit Programming 
switches, closes the Comparator Enable switch, and 
closes the Automatic Reset switch. For each print he 



2-30 



ARCHER 279 059 




+15V ' 

vss 




7 5 4 1 

DM8863 
2 3 6 8 18 



3 



40 35 33 32 31 30 29 28 27 23 24 22 

I 

MM 5865 
9 13 14 15 16 17 



-& 







t r TT 



RESET START 



1 ' 1 

z£ o.o3nFi; 

r+ 



vss 



s 6 2 1 
4 LM555C 
3 7 8 



vss 



Figure 6. The MM5865 used in a simple counting circuit. 



simply presses the Start/Stop switch to turn on the 
enlarger for the desired length of time. 

It is not necessary to enable the display while operating 
the timer. The display must be enabled only to program 
counter 1. The Reset switch may be pressed at any time 
to turn off the enlarger. The enlarger may be turned on 
for adjusting negatives by pressing the Start/Stop switch 
without enabling the comparator. 

With proper interfacing, function 7 may be used as a 
down-count timer for many applications, including 
cooking and washing. The desired time is simply pro- 
grammed into counter 2, the comparator is enabled, 
and then the Start/Stop switch is pressed. Counter 2 will 
count down to zero and turn off the appliance. 

A few applications (some for which two MM5865s are 
required) have been presented to illustrate the utility 
of the MM5865. The Stopwatch/Timer discussed above 
is but one general application for which the MM5865 
may be used. 

Figure 6 shows a simple manual counting circuit in 
which the MM5865 is used to count the closures of a 
manual switch. Of course, the manual clock could be 
replaced by electrical pulses. 



The 74C00 in this circuit debounces the switch used as a 
clock, S3. An LM555 is used to provide a multiplexer 
input frequency of 233 Hz. 

The MM5865 is operating in function 5, and displays the 
up-count of counter 2. After an initial Start/Stop transi- 
tion, each closure of the manual switch advances the 
displayed digits by one count. A Reset transition resets 
counter 2 to "0000." 



conclusion 

The emphasis of this presentation has been on the 
general timing and programmable capabilities of the 
MM5865 rather than on specific applications. Because 
so many functions are available in one package, it is 
possible to use the MIVI5865 as a general purpose chip, 
adding another MM5865 when it is necessary. In most 
applications only one or several of the seven functions 
need be used; however, because of its general purpose 
nature, the MM5865 lends itself well to the concept of 
quantity purchasing. 



2-31 



00 
CD 

r- 

z 
< 



A final note: Unless the start pulse is externally synchro- 
nized to the clock (available at pin 15 of the MM5865, if 
the internal oscillator is used), the amount of time which 
will elapse between the arrival of the start pulse at pin 14 
of the MM5865 and the appearance of the first digit in 
the display will not be equal to the programmed display 
resolution. It is possible to develop a start pulse that is 



synchronized to the clock using an MM74C221 Dual 
Monostable Multivibrator as shown in Figure 20. The 
time constant of R1 -C1 should be equal to the display 
resolution, the time constant of R2-C2 should be less 
than the programmed display resolution, and the time 
constant of R3 - C3 should be less than the time constant 
of R2-C2. 




Figure 21 . Start -Pulse Synchronizer. Time constant of R1 - C1 = 
display resolution. Time constant of R2 - C2 < display resolution. 
Time constant of R3 - C3 < time constant of R2 -C2. 



2-32 




Counters/Timers 



A 4-Digit, 7-Function Stopwatch/Timer 



introduction 

This construction article is the second of a series which 
is to concentrate on applications of the MM5865 uni- 
versal timer. The first article, "MM5865 Universal 
Timer Applications," presented in detail the program- 
mable and functional characteristics of the MM5865. 

This second article illustrates the construction and use 
of a 4-digit, 7-furction stopwatch/timer in which the 
display resolution and counter modulo may be pro- 
grammed with printed circuit board jumper wires. 

Other than switches, all components of the stopwatch/ 
timer are mounted on a glass-epoxy or glass-polyester 
board which is laminated with 1-ounce copper foil on 
one side. The board is mounted in the attractive instru- 
ment/clock case available from James Electronics. 

This instrument/clock case has provisions for the display, 
precut holes for H: our calculator-type switches, and a 
precut line cord hole. In addition, the case is sold with 
a red display bezel, four rubber feet, and a flip-top to 
conceal the four switches which may be assembled in 
the precut holes. 

A display resolution of 1 second, 0.1 second, or 0.01 
second may be programmed by on-board jumpers or a 
suitable switch. Furthermore, the counters may be 
programmed to count in modulo 6 or modulo 10. 

When used as a photographic enlarger timer or as an 
appliance timer, each digit is individually programmable 
with one of four pushbutton switches. The comparator 
output of the timer may be coupled to an enlarger/ 
appliance control circuit that can be permanently 
mounted to the enlarger or appliance. 

Applications for the stopwatch 'timer include, but are 
not limited to, the following: 

• Laboratory reaction and interval timer 

• Photographic enlarger and chemical processing timer 

• Stopwatch 

• Event timer 

• Appliance timer 

A simple listing of possible applications for the timer 
does not adequately describe the enormous power of 
the instrument. A tabulation of the seven functions 
which includes a break-out of the functions performed 
simultaneously by counters 1 and 2 of the MM5865 is 
much more revealing, and is presented below: 



1. Counter 2 
Counter 1 

2. Counter 2 
Counter 1 

3. Counter 2 
Counter 1 



Start-stop timing 
Total elapsed time 

Start-stop timing 
Total accumulated time 

Sequential event timing 
Total elapsed time 



4. Counter 2: Split-timing with total elapsed time 
Counter 1 : Not actively used 

5. Counter 2: Total accumulated time 
Counter 1 : Total elapsed time 

6. Counter 2: Up counter 
Counter 1: Programmable counter 

7. Counter 2: Programmable down counter 
Counter 1 : Not actively used 



operation 

The switches which control the operation of the stop- 
watch timer are visible on top of the case shown in the 
photographs of Figures 1a and 1b. Each switch Is 
indicated in the schematic drawing of Figure 2. 

In Figure 1a, the switch in the rear right hand corner of 
the case is a 7-position rotary Function Switch (F). At 
the front of the case the switches are, from left to right, 
Digit 4 Programming Switch (D4), Digit 3 Programming 
Switch (D3I, Comparator Switch (C), Digit 2 Program- 
ming Switch (D2|, and Digit 1 Programming (D1)/ 
Latch Control (LC) Switch. Digit 1 is the least significant 
digit (LSD): Digit 4 is the most significant digit (MSD). 

There are four switches under a center flip-cover. These 
are shown in Figure 1b. From left to right they are 
Final Event Switch (FE), Beset Switch (R), Start/Stop 
Switch (SSI, and Automatic Reset Enable Switch (ARE). 

The ARE switch is used only in function 6; it must be 
OFF for all other functions. The C switch has three 
positions: Comparator/Count Enable (CCE), used for 
functions 6 and 7; Program Enable (PE), used for 
function 7: and Count Enable (CE), used for functions 
1 through 5. The D1/LC switch is a dual purpose switch; 
for functions 3 and 4 it serves as the latch control switch, 
and for functions 6 and 7 it serves as the Digit 1 program- 
ming switch. There is no ON-OFF switch. Power is 
applied to the stopwatch/timer by plugging the line cord 
into a 120VAC/60Hz outlet. 

Table I is a tabulation of the abbreviations used for the 
switches and the functions to which they apply. If the F 
switch is set to any of the stop watch functions (1 
through 5) when power is initially applied to the 
stopwatch/timer, the display will remain blank. See 
"MIVI5865 Universal Timer Applications" for information 
on using pin 39 as a power on indicator. 

To operate the stopwatch/timer in any of the stopwatch 
functions, rotate the F switch to one of the stopwatch 
function positions, piace the ARE switch in the OFF 
position, place the C switch in the CE position, and press 
the R switch. 



2 33 






(a) (b) (c) 

Figure 1. External Photographs of Stopwatch/Timer, a) View of Function Switch, Comparator Switch, and Digit Programming Switches, 
b) With flip-cover raised, four additional switches are seen. The flip-cover is designed so that a press of the closed cover closes the Start/ 
Stop Switch, c) A miniature jack is mounted at the rear of the case so that a cable may be run to the appliance control box. 




Figure 2. Schematic Diagram of the 4 Digit, 7-Function Stopwatch/Timer. As drawn, the display resolution is 1 second. A SPST switch 
may be included between pin 16 of IC2 and Vgg to provide a display resolution of 0.01 second or 1 second. Another option, shown in 
the figure, is the Display Control Switch, which may be used to inhibit the display. 



Abbreviation 



Table I. Switch Abbreviations 



Switch 



Functions 



ARE 


Automatic Reset Enable 


6 


C 


Comparator 


1-7 


D1 


LSD Programming 


6, 7 


D2 


Digit 2 Programming 


6, 7 


D3 


Digit 3 Programming 


6, 7 


D4 


MSD Programming 


6, 7 


F 


Function 


1-7 


FE 


Final Event 


1-5 


LC 


Latch Control 


3, 4 


R 


Reset 


1-7 


SS 


Start/Stop 


1-7 



2-34 









100 Hz 


0.01 sec 





1 


10Hz 


0.1 sec 


1 





1Hz 


1 sec 


1 


1 


External 


- 



Divide 






Counter 1 
Digit 


Modu 


o 


Cour 


ter ; 

git 




Scaler 




> 


Pin 




D 




1 2 


3 


4 


3 2 


1 


4 


3 


2 


1 








10 


10 10 


10 


10 


10 


10 


10 


1 





6 


10 10 


10 


6 


10 


10 


10 


1 





10 


6 10 


10 


10 


6 


10 


10 


1 1 





10 


10 6 


10 


10 


10 


6 


10 





1 


10 


10 10 


10 


10 


10 


10 


10 


1 


1 


10 


10 10 


10 


6 


10 


10 


10 


1 


1 


10 


10 10 


10 


10 


6 


10 


10 


1 1 


1 


10 


10 10 


10 


10 


10 


6 


10 



Table II. Resolution Select Code. A zero indicates that the pin ma de. The operation of each function is detailed in the 

is left floating lor connected to V DD I. a one indicates that the f f ; , , h - . 

pin is connected to V ss . Note that when an external clock is 

applied to pin 15, pins 16 and 17 must be connected to v ss . To operate the timer in function 6, rotate the F switch 

to function 6, place the C switch in the CCE position. 

Resolution Select ! F ~!" and press the R switch. The display will show four zeros 

' Vi i. ^ . Display Resolution when the R switch is pressed. 

Pin 16 i Pin 17 Clock to Counters 

The count-up time is programmed into the timer by 
pressing D1 through D4, one switch at a time, until the 
desired count-up time appears in the display. 

After digit programming, place the ARE switch in the 
ON position if automatic resetting is desired. The initial 
press of the SS switch will cause the display to blank, 
then to indicate the count-up to the programmed time. 
Table III. Divide Scaler Code During the up-count the CA3059 will be enabled, 

- _ allowing the appliance to be turned on. When the count- 

up reaches the programmed time, the comparator output 
will go from volts to 8.4 volts. At this time the CA3059 
will be inhibited, and the appliance will turn off. 
Pressing the R switch any time after the digits have been 
programmed causes the comparator and counter 2 to 
reset. Switching the C switch to OFF causes the com- 
parator output pin to go to V DD as long as it is OFF. 
If the C switch is again placed in the CCE position 
(before the R switch is pressed), the comparator output 
pin will go back to V ss . Of course, any time the FE 
switch is pressed the comparator output will go to Vss- 

If the ARE switch is ON, the count-up sequence may be 

repeated by pressing the SS switch again. Nothing need 

be changed until it is necessary to reprogram the digits. 

A ,-ero indicates that the pin is left floating (or connected to When reprogramming is necessary, simply change the 

V DD I; a one indicates that the pin is connected to v ss time shown in the display to the new time, with the 

ARE switch in the OFF position, using the digit program- 
ming switches. Then press the SS switch to start the up- 
count. If the ARE switch is OFF, it is necessary to press 
Press the SS switch to initiate a sequence of timing the reset before starting a new count-up. 

series. Press the SS switch again to end a serial (functions 
1, 2, 3, 5) and simultaneously initiate a new serial while 

freezing the display (function 31, or to freeze the display To °P era,e the timer in function 7, rotate the F switch 

during a continuous count sequence (function 4). to functlon 7 . P'ace the ARE switch in the OFF position, 

place the C switch in the PE position, and press the R 
Press the SS switch a third time to initiate a new timing switch. The count-down time is programmed into the 

serial (functions 1, 2, 3, 5! or to update the display timer by pressing D1 through D4, one switch at a time, 

during a continuous count sequence (function 4). until the desired count-down time appears in the display. 

Subsequent presses of the SS switch will repeat the The C switch must then be placed in the CCE position, 

action described above. 

Press the LC switch to display a continuing, undisplayed PreSSm9 the SS Switch Wl " cause counter 1 to be 9 m lts 

count (functions 3 and 4). Press the FE switch to end a down-count from the programmed time to "0000" and 

sequence. A final press of the SS switch at the end of a Wl " CaUSe the CA3059 t0 be enabled ' turmn 9 on the 

sequence is required to display total elapsed time ^'^^ ^"'"if^Tr:' 6 ' ' ^^ 

(functions 1,3, 5) or total accumulated time (function 2). 000 ° «"= CA3059 will be inhibited, turning the 

Subsequent presses of the SS switch after the end of a a PP hance ° ff - The down-count ,s displayed, and may be 

sequence simply repeat the display of the final serial ha ' ted at a " V time by preSSIn9 the FE switch; the dowrv 

time, then the total elapsed or total accumulated time. count may not be resumed. Pressing the R switch any 

time after digit programming will reset counter 1. 

The operations which may be performed in each function 

are shown in the flow charts of Figures 3 through 8. When using function 7, the comparator must be disabled 

The first line of type in each PROCESS rectangle indi- and the R switch must be pressed before digit program- 

cates a switch or the display upon which an action may ming. Then the comparator must be enabled. This is 

be performed. The second line of type indicates the unlike function 6, in which digit programming is allowed 

position in which the switch must be placed or the at any time, regardless of the state of the comparator, 

action to be performed. The parallelograms in the flow In addition, the ARE switch must not be used in 

charts indicate points at which a DECISION must be function 7. 

2-35 



0> 
(O 

2 

< 



f START J 



COMPARATOR 




/^ END \^ 

< of > 


_/ TIME \. i\ 
< ANOTHER >!■ 
\ EVENT / 


o_k/ s 

Pf F l\! 


VESY^ 




\^FQiJtMCE-^ 




DISPLAY 
RECORD 




YEsY"^ 




J k. 




HNAL FVENT 
PRESS 




START^TOP 
PRESS 










+ 




A h. 




DISPLAY 
HECORO 

















Figure 3. Functions 1 and 2. Pressing START/STOP after FINAL EVENT has been pressed gives Total Elapsed Time in Function 1, 
Total Accumulated Time in Function 2. 



f START J 




Figure 4. Function 3. Pressing START/STOP after FIMAL EVENT has been pressed gives Total Accumulated Time. 



2-36 



( START j 


-< r 


\ u^crmf. 



COMPARATOR 



( END ) 




Figure 5. Function 4. 







( START 

1 


) 










FUNCTION 






4- 








AUTO RESET 
OFF 






i 








COMPARATOR 
CE 






+ 








RESFT 
PRESS 






























4- •*" 
















START ST0° 
PRESS 


DO 
r NOTHING 












sl 








1 


'4- 

^NO ji< STOF ^* 

T ""X. tivi'jg j 


[no 

r V^TIMING jT—~ 


VES 


DO 

NOTHIIVC- 


N. EVEN! /^~" 




T 




T 




U k START STOP 
r PRESS 




RECORD TOTAL 
ELAPSED TIME 






|Y£S 






A 


k 






FINAL EVEMT 
PRESS 


. RECORD TOTAL 
♦ ACCUMULATED 
TIME 


+ 


START STOP 
PRESS 



Figure 6. Function 5. 



2-37 



en 




interfacing the stopwatch/timer 
with an appliance circuit 



There are ,Tiany ways to interface the comparator output 
with an appliance control circuit. One method of inter- 
facing the MM5865 with an appliance control circuit is 
shown enclosed in dotted lines in Figure 2. Figure 2 is 
the schematic diagram cf the stopwatch/timer. 

The 74C02 has been included as the interfacing element 
between the comparator output pin and the trigger 
circuit of a triac. Figure 9 is a detailed schematic of the 
74C02 connections which form a NOR latch. 



I>^T#C> 



( END J 



Figure 9. Detail of the 74C02 NOR Latch. The latch interfaces 
the MM5865 to the CA3059. 



Figure 7. Function 6. 



( START J 



COMPARATOR 




CED 



Figure 8. Function 7. 



The appliance control circuit does not cause RFI because 
the triac is triggered by a zero-voltage switch. Triac 
firing can be inhibited by the application of a positive 
(up to 10V) voltage to pin 1 of the CA3059. 
When power is initially applied to the stopwatch/timer 
the S and R inputs of the latch are both "0." When the 
R switch is pressed, the output of the latch will go to 
V ss , inhibiting the CA3059 pulses to the triac. 
When the SS switch is pressed (after digit programming) 
the output of the latch will go to V d and tne CA3059 
will be enabled, turning on the appliance. As the pro- 
grammed time is reached by counter 2 of the MM5865 
(function 6), or as counter 1 reaches "0000" (function 7), 
the comparator output will go to Vss, tne output of the 
latch will go to V S s. and the CA3059 will be inhibited, 
turning off the appliance. 

The inhibit level provided by the latch may be removed 
from the CA3059 by opening the Appliance Enable 
Switch. This allows the appliance to be turned on for 
adjustments. For example, when the timer is used with 
an enlarger, the Appliance Enable Switch permits 
enabling of the enlarger lamp for focusing and mag- 
nification adjustments. 

The output of the latch is connected to the appliance 
control circuit via a tape recorder cable which plugs into 
a jack mounted at the rear of the stopwatch/timer case 
and a jack mounted on the appliance control circuit 
housing. The housing for the appliance control circuit 
should also have a socket into which the appliance may 
be plugged, unless a direct connection is desired. 



2 38 



As shown in Figure 2, the appliance control circuit 
consists of a triac and its trigger circuit. When the 
CA3059 zero voltage switch is enabled, the trigger 
circuit applies a brief gate signal to the triac for every 
alternation of the AC line voltage. After the triac is 
turned on by the gate signal, it remains on for the 
complete half cycle until the zero-crossing point is 
reached at the end of the alternation. The appliance 
receives the full AC line voltage under these conditions. 
If the NOR latch inhibits the trigger circuit while the 
triac is conducting, the triac cuts off when the line 
voltage approaches zero. It remains off until another 
gate signal is applied. Therefore, the NOR latch controls 
the AC input to the appliance. 

With the heat sink specified the triac can safely handle 
appliances rated up to 100 watts (0.83 Amp). For 
greater appliance loads a larger heat sink should be used. 
The specified triac is able to handle appliance loads up 
to 10 Amps. Of course, the fuse must be large enough to 
handle the current drawn by the appliance. Use a fast 
blow fuse if possible. 



construction 

The printed circuit board was designed specifically for 
the James Electronics' instrument/clock case only after 
assurance that the company has a permanent source for 
the cases; however, the board may be mounted in any 
case of sufficient size. 

Because the layout of the PC board requires that some 
traces be proximate, the board must be inspected while 
it is being etched. During these inspections proper 
resolution of the traces is maintained, if necessary, by 
rinsing the board in water and carefully scraping the 
photoresist from any copper which forms a short circuit 
between adjacent traces. The scraping is done best with 
an X-Acto blade. Etching should be continued with 
frequent inspections. 



If the exposure time, the amount of light, and the 
development time are exactly correct, trace resolution is 
usually not a problem. However, it is difficult to compute 
and control these variables without performing many 
experiments. The inspection method described above 
can save many boards which otherwise would be lost 
because of trace resolution defects. 

In addition to the care which must be given to the PC 
board during the etching process, excessive solder should 
be avoided when soldering to the pads. In case of diffi- 
culty with timer operation during thecheckout procedure, 
suspect the board immediately. 

Furthermore, no thought should be given to the idea of 
not using sockets for the integrated circuits. James 
Electronics has four socket styles. All are adequate 
except the wire wrap sockets. (The diameter of the wire 
wrap leads is too large.) However, it is easier to insert 
and remove ICs from the standard tin and gold sockets. 
The drilling guides shown in Figure 10 indicate all drill 
sizes for the parts shown in the parts list. Every effort 
has been made to allow the board to accommodate a 
variety of components. For this reason, there are extra 
pads and punch guides on the drilling guides. Refer also 
to the component layouts shown in Figure 11. The 
boards may be prepared using the XI positives shown in 
Figure 12. 

The bottom half of the James case should be prepared 
for the board by removing the 6 plastic pegs at the front 
of the case if they are present. The pegs may be removed 
by grasping them in the jaws of a long-nose pliers and 
shaking them from side to side while pulling on the 
pliers. 

The earphone socket should be drilled out from the 
outside of the bottom half of the case with a 31/64-inch 
drill bit. This will allow a 7 function rotary switch to be 
mounted in the right hand (facing the display) corner of 
the rear section of the top half of the case. When doing 
this, first press the bit to the 3/8-inch hole in the bottom 
half of the case, then turn on the drill. The bit should 
slice the earphone socket off with 4 or 5 turns of the 
chuck. 



o 


60 


60 -/ 


v- 6D \ 

A- 60 V. 6D 

V. 60 


\ 


7\ 65 -. 

IS K0LSS • \ \ 


V. 


!!V i0 ° 


o 


v 60 


O 




v H 


\y 


I 


60 -^, 


60 ^ <y 


6 1/16 — ' 






v„ 








^v« 


2 HOLES 


S/22 OBILL 

4 HGIES ~7 


65 '1^ 

«>" V 

J> 6S ^ 
70 --So 
'0 -* <- 60 

64 — -*• ^ ^* 

GO -^ 


v s V, 


6 i 


c/ 


V s 
v \ 

65 ^ ^65 

• o 


r N 




'B CHILI - 4 HOLES 



Figure 10. Drilling Guides for the Printed Circuit Boards, a) Drill sizes and hole locations for the Stopwatch/Timer PC board, b) Drill 
sizes and hole locations for the appliance control circuit. Dimensions are in inches. 



2-39 




4 « 

t t 



"O 



Figure 11. Printed Circuit Board Component Layouts, a) Layout for the Stopwatch/Timer PC board, b) Layout for the Appliance 
Control PC board. (Approximately 4/5 size shown). 





(b) 



Figure 12. Positives for the Printed Circuit Boards, a) Positive for the Stopwatch/Timer, b) Positive for the Appliance Control circuit. 
(Approximately 4/5 size shown). 



2-40 



The center portion of the top half of the case has been 
designed for a switch assembly composed of three push- 
button switches and one slide switch. The assembly is 
made of calculator-tyoe switches and a flex-circuit; 
however, James Electronics provides neither the switches 
nor the flex-circuit. 



Figure 13a shows the layout of the flex-circuit, Figure 
13b is a view of the flex-circuit after it has been folded 
over the thin plastic insulator which is shown in Figure 
13c. The insulator must be oriented so that the circular 
cutouts are between the two sets of four copper hexa- 
gons. The copper trace through each hexagon forms one 
contact of a SPST switch. 



0> 

to 




(c) 



<d) 

Figure 13. Flex-Circuit Assembly, a) Layout of the flex circuit, bl Layout of the flex-circuit after it has been folded to form the 
contacts of three SPST momentary pushbutton switches and one SPST slide switch, c) Thin plastic insulator which must be inserted 
between the folded portions of the flex-circuit, dl Plastic cover which fits over the flex-circuit assembly to hold it in place in the top of 
the case. 



If the automatic reset feature for function 6 is to be 
included, cut the slide switch hexagon connection to 
V ss as shown in Figure 14 and cut a little square piece 
from the thin insulator. This small square should be just 
large enough to allow a solder connection to be made 
between the trace going to the slide switch hexagon and 
the trace going to the FE switch hexagon. To solder 
the traces together, pretin both traces slightly, fold the 
flex-circuit as shown in Figure 13b, and apply a small 
soldering iron tip to the trace going to the slide switch 
hexagon at a point above the insulator cutout. 



The switches should then be placed in the top of the box 
in the spaces provided. The flex-circuit is then placed 
over the switches. Finally, the plastic cover fits over the 
entire assembly as shown in Figure 15. Holding the 
plastic cover firmly in place, touch a clean soldering iron 
tip to each of the plastic pegs protruding through the 
holes in the plastic switch assembly cover until the 
assembly cover is sealed to the top of the case. Cut the 
single tall plastic peg to the rear of the switch assembly 
cutout if there is one. 



o o o 
O o O c 




o 

.1. 




o o I 

o o 


o o 

° (D c 




o o o o 

dfo^rr® o 

o 



Figure 14. Full-Size Partial Drawing of the Flex-Circuit Layout Showing the Trace which Must be Cut if the Auto Reset Option is 
Desired. 



2-41 




Figure 15. Photograph Showing the Internal Construction of the Stopwatch/Timer. Note how flex-circuit runs from the top of the case 
to the trace-side of the printed circuit board. 



Drill the holes for the rotary function switch, the 
comparator switch, and the four programming switches 
as shown in the drilling guide of Figure 16. The drilling 
guide must be modified as shown in Figure 17 if the 
Centralab PS-101 switch is used. The holes for the 
rotary switch must be marked and drilled precisely. 
In addition, if the Centralab PS-101 switch is used the 
filter capacitor, CI, must lie on its side to make room 
for the function switch. Mounting the top of the case to 
the bottom is easier if the Centralab PS-101 switch is 
used. If desired, a jack may be mounted in the bottom 
half of the case in the right hand rear corner, behind C1 , 
to provide a quick connection to an enlarger or appliance 
control circuit. The fit will be tight, but a miniature jack 
can be mounted without much difficulty. This completes 
the case preparations. 



Before parts are mounted to the PC board, the fit of the 
board to the case should be checked. It may be necessary 
to adjust the mounting holes slightly with a small round 
file. Try not to completely break the traces surrounding 
the mounting holes. There are six mounting holes in the 
PC board. These holes match six plastic pegs in the 
bottom of the case. Two of the pegs are to be inserted 
through the transformer mounting flanges if a trans- 
former of the correct size is used. If the Radio Shack, 
or some other transformer which does not fit precisely, 
is used, it may not be pos'. : ble to fit the pegs through the 
transformer mounting flanges. 

After the IC sockets are mounted, the transformer and 
C1 should be mounted. If the Centralab PS-101 switch is 
used, the filter capacitor should be attached to the board 



2-42 




I*- 6 -tljft- 0.6 -»j 

—<sf — © — (if— & — ©- 




> 

z 

I 

5) 
(0 



Figure 16. Drilling Guide for the Case Top if the MRC 1 10 Rotary Function Switch is Used. (Dimensions in inches.) 




k-0.6 -»|«-a.6-»j 

5 — S> — (+f—® — ©- 




Figure 17. Drilling Guide for the Case Top if the PS 101 Rotary Function Switch is Used. (Dimensions in inches. I 



with leads that are long enough to permit the capacitor 
to lie on its side. The diameter of CI must not be greater 
than 0.7 inch and its length must not be greater than 
1.2 inch. 

The display mounting pins should be soldered to the 
display before the display is mounted to the board. Be 
careful not to lift the display pin pads when soldering. 

Wires must be soldered to the board and connected to 
the switches mounted to the top of the case. Refer to 
the wiring diagram shown in Figure 18. 



Wire jumpers may be used to program the display 
resolution and the modulo of the counters using the 
charts shown in Tables I and //. The connections shown 
in Figure 2 cause the display to read in tens of minutes, 
minutes, tens of seconds, and seconds; maximum time is 
99 min 59 sec. A pad which allows a connection to an 
external clock is available at pin 15 of the MM5865. 
After all components have been mounted and all wire 
connections have been made, proceed to the preliminary 
checkout and adjustments section before applying 
power to the board. 



2-43 




Figure 18. Wiring Diagram for the Switches Mounted in the Case 
Top. 

preliminary checkout and adjustments 

The following tests and adjustments should be carefully 
completed before power is applied to the stopwatch/ 
timer or the appliance control circuit. 
Rotate the F switch to function 7, place the ARE switch 
in the OFF position, place the C switch in the CCE 
position, and disconnect the tape recorder plug from the 
jack at the rear of the stopwatch/timer case. Adjust R1 
for minimum resistance. Do not connect any appliance 
to the appliance control circuit, but do place a fuse in 
the fuse holder. 

Measure the following points for the indicated amount 
of resistance: 

1. Across the stopwatch/timer line cord plug > 50 ohms 

2. Across CI, with VOM on X1K scale and common 
probe to Vqd. > 5k ohms, after CI charges 

3. Across R1 < 15 ohms 

4. Across C2> 100 ohms 

5. Across the appliance control circuit line plug > 10k 
ohms 

If these values of resistance cannot be found at the 
points indicated, check the PC boards for opens or shorts 
as necessary. Then, with a VOM connected across C2, 
apply power to the stopwatch/timer; the VOM should 
read slightly more than 1 volt. Increase the resistance of 
R1 until the VOM reads 8.4 volts. Slightly under 8.4 volts 
is better than slightly over. Pressing the reset switch 
should cause "0000" to appear on the display, unless the 
display already reads "0000." 

If the display is blank or indicates only one or two 
zeroes, the oscillator is probably not oscillating. Rotate 
C3, 360 degrees if necessary, while observing the display. 
If the display still fails to respond properly, check the 
voltage at pin 20 of the MM5865; it is very close to 6 
volts when the oscillator is functioning. 



After oscillation has been confirmed the display should 
be examined for segment and digit defects. If any 
segment or digit does not appear in the display (The g 
segment does not appear when the display reads all 
zeroes. I, the board and the display mounting pin connec- 
tions must be checked. 

When handling the stopwatch/timer before it is mounted 
in its case, extreme care must be used to not break the 
connections between the flex-circuit and the printed 
circuit board. However, these connections need not be 
made until the oscillator and display have been checked 
out. 

After the oscillator and display checkout, the frequency 
of the oscillator should be adjusted to the crystal fre- 
quency using C3. Then the board may be placed in the 
bottom of the case. The balance of the preliminary 
checkout consists of stepping through the operational 
flow diagrams in Figures 3-8; a VOM should be con- 
nected to the output jack during the functions 6 and 7 
checkout. If any of the switches under the flip cover 
fail to respond, check to see if the flex-circuit is broken 
at the point where it connects to the board. 

final assembly and checkout 

The board may be fastened to the bottom of the case by 
forcing =6 tinnerman nuts over the plastic pegs which 
appear through the holes indicated in Figure 11. This 
may be done easily with a 5/16 inch nutdriver. Then 
force the line cord in the cutout provided. 
The top of the case may then be carefully fitted to the 
bottom, with the red plastic filter partially in place. 
A slot in each half of the case retains the filter when the 
case halves are fastened. If the MRC-1-10 switch is used, 
the fit will be tight because of its proximity to C1. The 
cutout for the line cord in the top half of the case must 
be forced over the line cord. 

Once the two halves are fitted properly, fasten them 
together using the four screws provided with the case. 
Install the rubber feet and proceed with the final check- 
out. 

The final checkout is a repetition of the operational 
checks using the flow diagrams. Each option at each 
decision point in every flow diagram should be exercised. 

resolution and accuracy 

If a crystal is used for the time base of the stopwatch/ 
timer, the accuracy of the displayed count will, of 
course, depend upon the particular crystal used. In 
addition, because the MM5865 begins to count on the 
leading edge of the start/stop pulse, the width of this 
pulse becomes important when the event time is very 
short. 

For example, when coupling the timer to an appliance, 
if the width of the start/stop pulse is longer than the 
event time, the appliance will not turn off at the end of 
the programmed time. 

This is why C5 and R4 have been included. Together 
they insure that the start/stop pulse will not be longer 
than 0.01 second. This pulse width should be adequate 
for most users. C5 and R4 may be omitted if the length 



2 44 



of time the start/stop switch is to be held closed will 
always be less than any timed event. When C5 and R4 
are omitted, the SS switch simply connects to Vgg. 
As to crystal accuracy, the stopwatch/timer will lose 
0.001 sec/sec if a 32.768kHz crystal is used instead of a 
32.8kHz crystal. This should be insignificant for most 
users. 

Also, the display resolutions which may be programmed 
by on board jumper wires will be adequate for most 
users. Figure 2 illustrates the connections to the MM5865 
which will cause the display to read in tens of minutes, 
minutes, tens of seconds, and seconds. 

When it becomes desirable to achieve a display resolution 
which allows the timing of events that are hours in 
length, it is necessary to provide the MM5865 with an 
external time base. This may be done by cascading two 
MM5865s or by using a simple timing circuit built around 
an LM555 timer or a digital clock. Figure 19 shows how 
an MM5315 digital clock may be used as a time base for 
the MM5865. The MM5315 itself uses the line frequency 
as a time base. The MM5315 is shown as it would be 
connected for a 60Hz line frequency. 

When an external time base is provided for the MM5865 
in this manner, an external multiplexer must also be 
provided. The oscillator formed with the 74C14 supplies 
the desired multiplex frequency as shown in Figure 19. 

A final note: Unless the start pulse is externally synchro- 
nized to the clock (available at pin 15 of the MM5865, if 
the internal oscillator is used), the amount of time which 



will elapse between the arrival of the start pulse at pin 14 
of the MM5865 and the appearance of the first digit in 
the display will not be equal to the programmed display 
resolution. It is possible to develop a start pulse that is 
synchronized to the clock using an MM74C221 Dual 
Monostable Multivibrator as shown in Figure 20. The 
time constant of R1 -CI should be equal to the display 
resolution, the time constant of R2-C2 should be less 
than the programmed display resolution, and the time 
constant of R3 - C3 should be less than the time constant 
of R2-C2. 



START SWITCH 



TO 

PIN 14 

OF 

MM5865 



> 

z 

I 
O 

CO 




Figure 20. Start-Pulse Synchronizer. Time constant of R1 -CI = 
display resolution. Time constant of R2 - C2 < display resolution. 
Time constant of R3 - C3 < time constant of R2 - C2. 




TO PIN IB OF IC2 
TO PIN 4 OF IC6 



Rt 201(11, V.W, 5% RESISTOR 

R2 220kU, V.W, 5% RESISTOR 

R3 100k(>, ViW. 5% RESISTOR 

C1 0.1 »iF CAPACITOR 

C2-C4 D.QIyF CAPACITOR 

Dt 1N4002 DIODE 

02 8.2VZENER DIODE 



Figure 19. Using an MM5315 Digital Clock and an External Multiplexer to Provide an External Time Base for the MM5865 to Generate 
a Display Resolution of 1 Minute. 



245 



PARTS LIST 

R1 5kf2 trimpot 

R2 240J2, 54W, 5% resistor 

R3 20MSJ, 'AW, 5% resistor 

R4 1 MSI, %W, 5% resistor 

R5 100k$2, y«W, 5% resistor 

R6 5.1kJ2, 'AW, 5% resistor 

R7 4.7k£2, %W, 5% resistor 

R8 10kS2, 1W, 5% resistor 

C1 470- 1000mF, 25V capacitor 

C2 10mF, 25WVqc solicl tantalum capacitor 

C3 6-25pF variable capacitor. Sprague GT1-1E 

4- 30pF may be used. 

C4 25 - 27pF, disc ceramic capacitor 

C5 0.01mF disc ceramic capacitor 

C6 lOOmF, 25WV DC capacitor 

C7 0.05mF, 200WV D c ca Pa cit ° r 

Di,D 2 IN4003 

T1 10- 16.5 V AC @ 300mA transformer 

IC1 LM317T voltage regulator 

IC2 MM5865 universal timer 

IC3 CD14511 decoder/driver/latch 

IC4 DS8877 or DS75492 digit driver 

IC5 RA07- 150 resistor array 

IC6 74C02 quad 2-input NOR gate 

IC7 CA3059 zero voltage switch 



Triac HEPR1723 

F1 1 A fast or normal blow fuse 

XTAL 32.8kHz crystal (32.768kHz can be substi- 

tuted. Timer will lose about 35 sec in 11 hr 
20 min of use.) 

SI, S3, S5 SPST, NO, momentary pushbutton switches; 
part of flex-circuit switch assembly. 

S2 SPST slide switch; part of flex-circuit switch 

assembly. 

S4 DPDT, center OFF toggle switch 

S6-S9 SPST, NO, momentary pushbutton switches 

510 7-12 position rotary switch - Centralab 
PS-101 or Alcoswitch MRC-1-10. 

511 SPST toggle switch 

512 SPDT toggle switch (optional) 

Display National Semiconductor NSB5411 4-digit 
multiplexed display. 

Heat Sink TO-220 heat sink. Two needed. 

Misc. 16 display mounting pins (strip of 16 pins); 

1 case; Clock/Instrument (available from 
James Electronics); 1 flex-circuit; 1 flex- 
circuit insulator; 2 Tinnerman nuts, #6; 
fuseholder; appliance control box, — LMB 
C.R.-234; 115V A c chassis mounting socket; 
miniature jacks; phone cable (shielded); IC 
sockets. 



NSB5411 4 FULL 03GITS 




i ! 

-In 



on dp 



mammmm 



RED FACE PLAtE 



t 2 3 4 5 6 7 8 9 10 11 12 13 14 IS 16 
FRONt VIEW 



t 

0.760" 

1 

i 




0.262" — 


4 — 



PIN CONNECTIONS 



ANODE G— PIN 1 
ANODE F— PIN2 
ANODE E — PIN 3 
ANODE D —PIN 4 
ANODE A— PIN 5 
ANODE C — PIN 6 
ANODE B— PIN 7 
ANODE AM/PM INDICATOR —PIN 8 



PIN 16— ANODE COLON TOP 
PIN 15— CATHODE 5 
PIN 14— CATHODE 4 
PIN 13— CATHODE 2 AND 3 
PIN 5 2— CATHODE 1 AND AM/PM 
PIN 11— LIGHT SENSOR 
PIN 10— LIGHT SENSOR 
PINO— ANODE COLON BOTTOM 




Figure 21. Dimensions and Pin Connections for the National Semiconductor Corp. NSB5411 4-Digit, Multiplexed Display. Mounting 
holes for a photocell are included on the display board. 



2-46 




SECTION 3 
ELECTRONIC ORGAN CIRCUITS 







Electronic Organ Circuits 



MM5554 frequency divider 
general description 

The MM5554 frequency divider provides six stages 
of binary division to produce six octave related 
outputs of an electronic musical instrument tone 
generator. Each divider stage consists of an asyn- 
chronous, DC-coupled flip-flop. The six stages are 
internally connected in cascades of one, two, and 
three flip-flops. Each flip-flop drives a push-pull 
output buffer, which provides low output impe- 
dance in both logic states. Two of the internal 
cascades also provide trigger outputs for use in 
cascading the divider stages. The timing diagram 
shown results from connecting the same input 
trigger to all three inputs. 

The MM5554 complements the MM5555/MM5556 



chromatic frequency generator ; output charac- 
teristics and power supply requirements are com- 
patible. The MM5554 is packaged in a 14-lead 
dual-in-line package. 

features 

■ to 500 kHz toggle frequency 

■ 1-, 2-, 3-stage partitioning 

applications 

■ Electronic organs 

■ Electronic music synthesizers 

■ Musical instrument tuners 



logic and connection diagrams 



Typical Organ Tone Generator 





TRiCGsn iNPin > ' ' >— 










^ S A 


' 








r ^ 










101 > 








_ 










, 




1 


1 




-- 


7 S 5 S 3 2 

a s in ii 12 u i 




9 10 11 12 13 14 


CHROMATIC 




n~ 


II II 




1 1 1 1 1 










, 


1 1 1 1 1 1 1 1 1 
1 1 1 1 1 1 1 1 1 




1 








UMS&MS 














nn, 


I 




1 






~rii 




X~ 


1 G s a 3 2 1 
MMSiM 




IZnQTAU 
MM&5W 

frequency 
dividers 


WMS554 

9 111 11 12 13 14 


=h 


m\\\ 




p\ 


■ttll 




fttlll 



KEYswncHiNti cipcuiT- 



Dual-ln-Line Package 




- OUTPUT 26 

- OUTPUT 2A 

- OUTPUT 1 

- OUTPUT 3C 

- OUTPUT 3B 

- OUTPUT 3A 

- QHD 



Order Number MM55S4N 
See Package 18 



3-2 



absolute maximum ratings 



Logic Supply Voltage fV GG ) 
Buffer Supply Voltage (V Ba i 
Trigger Input Voltage (V (T ) 
Power Dissipation (P D ) 
Storage Temperature IT S ) 
Operating Temperature (T A ) 



V ss + 0.3V to V ss -33V 

V ss +0.3V to V ss - 18V 

V ss + 0.3V to V ss - 18V 

250 mW 

-55°Cto +100°C 

0°C to +70° C 



electrical characteristics 

T A within operating range (V GG = -27 + 2V, V BB = -10 ± .5V), unless otherwise noted. 



timing diagram 



■-" WLJinmrLJiri^^ — 



STAGE 1 OUTPUT 



TRIGGER OUTPUT 



STAGE 2 OUTPUT 



TRIGGER OUTPUT 2 



STAGE 3 OUTPUT 




J I P 

n 



PARAMETER 


SYMBOL 


MIN 


TYP 


MAX 


UNITS 


Trigger Inputs: 
Frequency 


flT 


DC 




500 


kHz 


Rise and Fall Times {10% to 90%) 


V tf 






25 


ns 


Pulse Width (at 90%) 


pw 


1 






MS 


Logical High Level 


V,TH 


■2.5 




Vss 


V 


Logical Low Level 


ViTL 


-18.0 




-7.0 


V 


Leakage Current 


I.TL 






1.0 


JJA 


Trigger Outputs: (loaded 10M ohm 
to ground, T A = 25°C] 
Logtcai High Level 


VoTH 


-1.5 







V 


Logical Low Level 


VqTL 






-10 


V 


Buffer Outputs: (loaded 20K ohm 
to ground and 20K ohm to V BB , 
T A = 25°C) 
Logical High Level 


Von 


-1 







V 


Logical Low Level 


Vol 


Vbb 




-8.0 


V 


Supply Currents: (no output 
! oads, T A = 25°C) 
Logic Supply 


'gg 






4 


mA 


Buffer Supply 


'bb 






20 


MA 



33 



a 



Electronic Organ Circuits 



MM5555, MM5556 chromatic 
general description 

The National Semiconductor MM5555, MM5556 
chromatic frequency generators are MOS/LS1 
frequency synthesizers designed to generate musi- 
cal frequencies. The circuits provide thirteen semi- 
tone outputs, fully spanning the equal tempered 
octave. The divisors have been carefully selected 
to offer excellent tuning accuracy and to eliminate 
any "locked" (just-intoned) fifths. Output charac- 
teristics are fully compatible with the MM5554 
Frequency Divider. The MM5555 or MM5556 is 
packaged in a 14-lead dual-in-line package. 



frequency generators 
features 

■ Single-phase squarewave input 

■ 7 kHz to 2.2 MHz input frequency 

■ Accuracy of 0.5129 cent 

applications 

■ Electronic organs 

■ Electronic music synthesizers 

■ Musical instrument tuners 



connection and logic diagrams 

Dual-ln-Line Package 

XT 



Dual-ln-Line Package 



•Used only foi testing. Pir 
4 is normally grounded. 



TJ" 



Order Number MM5555N 
See Package 18 



Order Number MM5556N 
See Package 1 8 



Typical Organ Tone Generator 





-27V > 


■ " ♦ 


, 










14V >— 
-1QV> 


, 

f~ 




• 










V 




• 


1 


-• 

1 


"1 


iE; 






a 9 in ii « i 

1 Ml 


1 

— • 


1 6 i i 3 I 1 

1 I t 1 1 1 I 






1 


i i i 
i i i 


1 1 1 1 1 1 — < 

1 1 1 1 1 


■ 


< < 






UL_ 




— •- 


III 




WM5bM 




1 


111, 


™ 


«M 


7 6 5S 3 ? 1 


t J 


?T 


\\\\\l 


J 


P\ 


111 


j 

B 


N 


ttt!ll. 



OUtput details (2.12608-MHz input) 

MM5555 







OUTPUT 


E.T S. 


CENT 


NOTE 


DIVISOR 


FREQUENCY 


FREQUENCY 


ERROR 


ca 


b08 


418b 20 


4186.01 


-0.326 


C9 


254 


8370.39 


8372.02 


0.326 


B8 


269 


7903.64 


7902.13 


*0.321 


a -■-■ a 


285 


7459 93 


7458.6? 


+0 295 


A8 


30? 


7040 00 


704000 





G -8 


3?0 


6644 00 


6644.88 


-0 721 


(=8 


319 


62/1 62 


62/1 93 


-008? 







OUTPUT 


E.T.S. 


CENT 


NOTE 


DIVISOR 


FREQUENCY 


FREQUENCY 


ERROR 


F :-"H 


3b9 


V.)?? 73 


b9 19.91 


■0.658 


F8 


380 5 


588/ 80 


558 7 85 


017 


E8 


403 


b?/b 83 


5274.114 


■ 807 


D -8 


42/ 


4979 1 1 


4978 03 


■0 364 


08 


45? 5 


4698 b? 


4698 64 


-0 042 


C ^8 


479 5 


44 33 9b 


44 34 92 


368 



3-4 



absolute maximum ratings 

Clock Generator Voltage (V GG ) 0.3V to -33V 

Logic Supply Voltage (V DD ) 0.3V to -25V 

Buffer Supply Voltage (V BB ) 0.3V to ~18V 

Trigger Input Voltage (V, T ) 0.3V to -18V 

Power Dissipation (P D ) 800 mW 
Storage Temperature (T s ) -55°C to +100°C 

Operating Temperature (T A ) 0°C to +70°C 



electrical characteristics 

T A within operating range (V GG = -27V +2V, V OD = -14V ±1 V, V B 



1 -10V ±0.5V), unless otherwise noted. 



PARAMETER 



T 



Trigger Input 
Frequency 

Capacitance 

Rise and Fall Times 
(10% to 90% at 2.2 MHz) 

Pulse Width (at -5.0V) 

Logical High Level 

Logical Low Level 

Leakage Current 

Buffer Outputs: (loaded 20 kI2 to 
ground and 20 kli to V BB , 
T A = 25°C) 
Logical High Level 

Logical Low Level 

C8 Duty Cycle 

C #8 thru C9 Duty Cycle 

Supply Currents: (no output loads, 
T A = 25°C) 

Clock Generator Supply 
' MM5555 



Logic Supply j 
Buffer Supply 



MM5556 



SYMBOL 



fix 

C,T 

tr. tf 

pw 

V IT H 
V,TL 



'do 



MIN 



7.0 



0.4T 

-2.0 
-16 



-1.0 



1.5 
16 
22 



TYP 



2126.08 




-10 



50 
30 



MAX 



2200 

7.0 
30 

0.6T 

0.3 

-8.0 

1.0 



UNITS 



kHz 

pF/pkg 

ns 



(T = 

V 
V 
MA 



V 
V 

% 
% 



1 



3.5 


mA 


34 


mA 


40 


mA 


25 


MA 



typical performance characteristics 



'DD vs Ambient Temperature T/\ 



IqD vs v DD 



f.T = 
VlTL 

-25 
Vdd 


2.2 MHz 
- -12V 

-• V G < 
■-15V 


-3D 


- 








MM5556 


H I 


h*— < — ~. MM5555 








j 







'it " 

V.TL 

-2S 


2.2 MHz 
■-12V 

•' v GG < 

25"C 


-30 


- - 




^j#S^ 




T "" 


r^^'' 


^ 


-"""i ^""^ 










i , i j ! 



20 30 40 50 60 70 
- TEMPERATURE CC) 



3-5 



01 
IT) 
IT) 
IT) 




Electronic Organ Circuits 



MM5559 serial-to-parallel converter 
general description 

The MM5559 serial-to-parallel converter provides 33 bits 
of conversion in a single package. A serial output facili- 
tates cascading these devices to provide larger conversions. 



applications 



Matrix displays and printers 

Musical instrument keyboard/tone generator interface 

controllers 



features 

■ 33 Parallel outputs 

■ Serial output 

■ DC-to-250 kHz operation 



logic and connection diagrams 



CLOCK 

input" 



2PHASE 
CLOCK GENERATOR 



SERIAL 
DATA- 
INPUT 



TRANSFER 
ENABLE" 



33 BIT SHIFT REGISTER 



SERIAL 
. DATA 
OUTPUT 



33 OUTPUT LATCHES 



VSS. 

(OV) 



TYPICAL , VrjEXTI 

CIUTPUT I L0AD 



OUTPUT BUFFERS 



Vrj EXTERNAL 
| LOAD 



(Vss-lOV) 



(V SS -2DV) 



OUTPUT LOAD 
REFERENCE 
VOLTAGE 

(V SS T0V SS 30V) 



33-Bit Serial-to-Parallel Converter 

timing diagram 



Dual-ln-Line Package 




vss 

DATA OUT 
TRANSFER ENABLE 



Order Number MM5559N 
See Package 24 



DATA OUT 
(SERIAL! 



TRANSFER 
ENABLE 



JC 



)CZDC 



— -- iid— ■— ■— 'W — - 



riDczDc 



DATA OUT 
(PARALLEL) 



X 



3-6 



absolute maximum ratings 


Voltage At Any Pin V$3 + 0.3 to Vgg - 25V Storage Temperature -55"C to +100 "C 


Voltage At Any Output Pin V$S + 0.3 to V$S " 33V Lead Temperature (Soldering, 10 seconds) 300°C 


Operating Temperature C to +70° C 


dc electrical characteristics 


Ta within operating range, V$S = 0V, Vqd = -10V, ±10%, VqG = -20V ±10%, output load reference voltage = 


0V to —30V (via external load resistor) 


PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Data Input Voltages 












Logic High Level 




V S S '2.2 




VSS 


V 


Logic Low Level 




VSS " 




VSS"? 


V 


Clock and Transfer Enable Input Voltages 












Logic High Level 




VSS ' ' o 




vss 


V 


Logic Low Level 




vss- 11 




VSS 8 - 6 


V 


Input Capacitance 








7 


pF 


Input Leakage Current 


T A = 25°C. V| N = Vss-" 






10 


MA 


Clock Input Frequency 


Duty Cycle = 50% 







250 


kHz 


Rise and Fait Times 


V S S- 2.2 through VsS"8.6 






0.2 


MS 


Transfer Enable Input 












Pulse Width 


Time at VsS" 8.6 


1.6 






MS 


Rise and Fait Times 








0.2 


MS 


Parallel Outputs 












Output Voltage 


lO - 2 mA 


VSS 2 






V 


Leakage Current 


T A = 25°C, V O = V S s-30 






10 


MA 


Serial Output Voltages 












Logical High Level 


Loaded 56 k£2 to Vqq 


VSS- 2 




VSS 


V 


Logical Low Level 


Loaded 560 ki2 to Vss 


VDD 




VSS "8 


V 


Power Supply Currents 












Drain Supply, \qq 








10 


mA 


Gate Supply, \qq 


(Note 1) 




7.5 


20 


mA 


Note 1: The magnitude of \qq is modulated by the parallel output data; the current is inversely proportional to the number of outputs 


that are high (sourcing current). The typical value of 7.5 mA is representative of an alternating 1 's and O's output pattern. 


ac electrical characteristics 


PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


t r j s Data Setup Time 


Referenced from Vgg -■ 7 on Data In 
to Vss 8.6 on Clock In 


0.4 






Ms 


t c j|-, Data Hold Time 




0.2 






Ms 


'td Transfer Delay 


Referenced from V$S 8.6 


0.6 






Ms 


t\\ Transfer Strobe Width 




1.6 






(JS 


Propagation Delay 












tpds Se,!al 


High-to-Low (Vss t0 V DD> 


3.0 






Ms 




Low-to-High 


1.2 






Ms 


tpdp Parallel 


Low-to-Hiqh with 10 ki> Load 


1.2 






MS 






Electronic Organ Circuits 



MM5823, MM5824 frequency dividers 



general description 



These frequency dividers provide six stages of binary 
division to produce six octave-related outputs of an 
electronic musical instrument tone generator. Each 
divider stage consists of an asynchronous, decoupled 
flip-flop. 



The MM5823 and MM5824 complement the MM5832, 
MM5833 and MM5555, MM5556 chromatic frequency 
generators; output characteristics and power supply 
requirements are compatible. The MM5823 and MM5824 
are packaged in a 14-lead dual-in-line package. 



The six stages of the MM5823 are internally connected 
in cascades of two, one, one, and two flip-flops. Each 
flip-flop drives a push-pull output buffer which provides 
very low output impedance in both logic states. 

The six stages of the MM5824 are internally connected 
in cascades of one, two and three flip-flops. Each flip- 
flop drives a push-pull output buffer which provides very 
low output impedance in both logic states. Two of the 
internal cascades also provide trigger outputs for use in 
cascading the divider stages. 

The timing diagram shown results from connecting the 
same input trigger to all three inputs. 



features 

■ to 100 kHz toggle frequency 

■ 1, 2, 3 or 2, 1, 1, 2 stage partitioning 

applications 

■ Electronic organs 

■ Electronic music synthesizers 

■ Musical instrument tuners 



connection diagrams 



Dual-ln-Line Package 



Dual-ln-Line Package 





U 




V GG 

2 






n 


13 


3 


n 


12 


4 


LH 


11 


5 

NC 

S 


n 


10 


n 


9 


7 


MM5823 


8 



OUTPUT IB 
OUTPUT 1A 
OUTPUT 2 
0UTPUT3 
OUTPUT 4B 
OUTPUT 4A 



INPUT 1 
INPUT 3 



1 


U 


14 


2 


sTE~ 


13 


3 


r^L_ 


12 


4 

h 


J WE: 


10 


6 


r^ 


9 




Li? 






MM5B24 





OUTPUT 28 
OUTPUT 2A 
OUTPUT 1 
OUTPUT 3C 
OUTPUT 36 
OUTPUT 3A 



Order Number MM5823N 
See Package 18 



Order Number MM5824N 
See Package 18 



3-8 



absolute maximum ratings 



Logic Supply Voltage (V GG ) 0.3V to -30V 

Buffer Supply Voltage (V DD ) 0.3V to -18V 

Trigger Input Voltage (V IT ) 0.3V to -25V 

Power Dissipation (P D ) 250 mW 

Storage Temperature (T s ) -55C to +150°C 

Operating Temperature (T A I 0°C to +70°C 



electrical characteristics 

T A within operating range (V GG = -27 ±1 V, V DD = -1 1 .5 ±0.5V, V ss = OV), unless otherwise noted. 



Ul 
00 

ro 



oo 
ro 



PARAMETER 


MIN 


TYP 


MAX 


UNITS 


Inputs: 










Frequency (f lT ) 


DC 




100 


kHz 


Rise and Fall Times (10% to 90%) (t r , t f ) 






25 


MS 


Pulse Width (at 90%) (pw) 


2 






/"S 


Logical High Level (V| TH ) 


-2.0 


Vss 


0.3 


V 


Logical Low Level iV| TL ) 


-18 


-10 


-8.0 


V 


Leakage Current @ V ITL = -18V (l ITL | 






1.0 


MA 


Trigger Outputs: (loaded 10M ohm 










to ground, T A ^ 25 C) 










Logical High Level (V OTH ) 


V ss -1.5 




Vss 


V 


Logical Low Level (V 0TL ) 


-18 




-10 


V 


Outputs: (loaded 10k ohm to ground 










and 10k ohm to V DD , T A = 25'CI 










Logical High Level (V OH ) 


0.5 




0.3 


V 


Logical Low Level !V OL ) 


V DD +0.3 




V DD +0.5 


V 


Supply Currents: (No output loads, T A = 25X) 










Logic Supply (l GG ) 




2.0 


8.0 


mA 


Buffer Su|jply H D ol 






20 


MA 



3-9 



CNJ 

00 

in 



typical application 



CO 
00 

in 



2.00024 MHz 

TRIGGER INPUT > 

-27 V >- 

-t4V >■ 

-10V >- 














































" 












_ 
















































1 














I 














7 6 5 4 3 2 1 

MM5833 
B 9 10 11 12 13 14 




7 6 5 4 3 2 1 

MM5832 

8 9 10 11 12 13 14 


CHRDMATIC 
FREQUENCY 
GENERATOR 




^ 






1 II II 




I I I I I 
















,1111 1 1 1 1 1 










> 








III I 1 1 1 1 
















T09 ADO'L 

MM5B24 


















i 














































II, 
















Mi 
















II, 








7 6 5 4 3 2 1 

MM5B24 

8 9 10 It 12 13 14 






7 6 5 4 3 2 1 

MM5824 

8 9 10 11 12 13 14 


12 (TOTAL) 

MM5824 

FREQUENCY 

DtVIOERS 




7 6 5 4 3 2 1 

MM5824 

8 9 10 11 12 13 14 






: 






i 












L 






► 










i 








> 










J 


r 


J 










J 


r 


J 










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76 543C=2DB "Z" 



7 6 5 4 3 02 



CB — 7 6 5 4 3 2 C9 



timing diagram 



85 OUTPUT FREQUENCIESTO 
KEYSWITCHING CIRCUITRY 



Typical Organ Tone Generator 



TRIGGER 
INPUT 



^uuinjuu^i 



1 I L 

J L 



3-10 




Electronic Organ Circuits 



MM5832, MM5833 chromatic frequency generator 



general description 



The National Semiconductor MM5832, MM5833 chro- 
matic frequency generator is an MOS/LSI frequency 
synthesizer designed to generate musical frequencies. 
The circuits provide thirteen semi-tone outputs, fully 
spanning the equal tempered octave The divisors have 
been carefully selected to offer excellent tuning accu- 
racy. Output characteristics are fully compatible with 
the MM5554, MM5823and MM5824 Frequency Dividers. 
The MM5832 or MM5833 is packaged in a 14-lead dual- 
in-line package. 

features 

■ Single-phase squarewave input 



■ 7 kHz to 2.1 MHz input frequency 

■ Maximum error of 1.16 cent 

applications 

■ Celeste tone generator 

■ Electronic music synthesizers 

■ Organ tone generators 

■ Chorus tone generators 



connection diagrams 



Dual-ln-Line Package 



GNO- 
TRIGGER 'NPUt- 



TJ 



GMD< 
TRIGGER INPUT. 



Dual-ln-Line Package 



"Used only foi testing. Pin 4 is 
normally grounded. 



Order Number MM5832N 
See Package 18 



Order Number MM5833N 
See Package 18 



3-11 



absolute maximum ratings 



Clock Generator Voltage (V GG ) 
Logic Supply Voltage (V DD ) 
Buffer Supply Voltage (V BB ) 
Trigger Input Voltage (V, T ) 
Power Dissipation (Pp} 
Storage Temperature (T s ) 
Operating Temperature (T A ) 



+ 0.3V to V s 



33V 



V ss + 0.3V to V ss - 25V 

V ss +0.3V to V ss - 18V 

V ss +0.3V to V ss - 18V 

800 mW 

-55° C to+100°C 

0°C to +70°C 



electrical characteristics 

T fl within operating range (V GG = ~27V±2V, V DD = -14V + 1V, V B 



-10V ±0.5V, V ss = 0V), unless otherwise noted. 



PARAMETER 


MIN 


TYP 


MAX 


UNITS 


Trigger Input 










Frequency (f| T ) 


7.0 


2000.24 


2100 


kHz 


Capacitance (C| T ) 






7.0 


pF/pkg 


Rise and Fall Times (t r , t f ) 






30 


ns 


(10% to 90% at 2.1 MHz) 










Pulse Width (at -5.0V) (pw) 


0.4T 




0.6T 


(T=1/f IT ) 


Logical High Level (V, TH ) 


+0.3 





-2.0 


V 


Logical Low Level (V| TL ) 


-16 




-8.0 


V 


Leakage Current (I itl ) 






1.0 


MA 


Buffer Outputs: (loaded 20 kfi to 










ground and 20 ki2 to V BB/ T A = 25 C) 










Logical High Level (V n) 


-2.0 







V 


Loyical Low Level (V OL ) 


V BB 




-8.0 


V 


C8 Duty Cycle 




50 




% 


C =8 thru C9 Duty Cycle 




30 




% 


Supply Currents: (no output loads, 










T A -' 25°C) 










Clock Generator Supply (l GG ) 


1.5 




3.5 


mA 


Logic Supply (l DD ) 


16 




34 


mA 


Buffer Supply (l BB ) 






25 


M 



typical performance characteristics 



'DD vs Ambient 
Temperature T ^ 



Iqd vs v DD 





f 1T = 2.1 MHz 






V 1TL =-12V 




38 

34 
30 


Vod = 


-15V 


— — - 






MM5B33 ^ 






22 














i 
1 


i ! 



f IT =2.1 MHz 


ft 








V ITL = -12V 
-25<V GG <-3 






T fl = 25 C 








\ T~ \ 


— 








MM5832/MM583 


^^- 














i ' 











-10 10 20 30 40 50 60 70 
T A - TEMPERATURE! C) 



3-12 



typical application 



2.00024 MHz 

TRIGGER INPUT > 

-27V > 

14V > 

-10V > 


























































. 


















































1 












1, 














7 6 5 4 3 2 1 

MMS833 
B 9 10 11 12 13 14 




7 6 5 4 3 2 1 

\WI5832 

8 9 10 11 12 13 14 


CHROMATIC 
FREQUENCY 
GENERATOR 










1 1 1 1 1 




1 1 1 1 1 
















,111 1 1 1 1 1 










1 








III 1 1 1 1 1 
















T09 ADDL 
MM5824 












. 


" 




i 














































III 
















III 
















II, 








7 6 5 3 2 1 

MM 58 24 

8 9 10 11 12 13 14 






7 6 5 4 3 2 1 

MM5824 

8 9 10 11 12 13 14 


12 (TOTAL. 

MM5924 

FREQUENCY 

DIVIDERS 




1 6 5 i 3 2 1 

WM5824 
8 9 10 11 12 13 14 










1 


















1 
















1 










J 


r 


J 






I 




J 


r 


J 










J 


r 


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7 6 5 4 3 C =2 



6 5 4 3 D2 



W 
00 
CO 
ISJ 



at 
oo 

CO 
CO 



6 5 4 3 2 C9 



Typical Organ Tone Generator 



output details 12.00024 mhz input) 



NOTE 


DIVISOR 


OUTPUT 
FREQUENCY 


E.T.S. 
FREQUENCY 


CENT. 
ERROR 


C8 


478 


4184.61 


4186.01 


-0.565 


C9 


239 


8369.21 


8372.02 


-0.565 


B8 


253 


7906.09 


7902.13 


0.842 


A=8 


268 


7463.58 


745862 


1.119 


A8 


284 


7043.10 


704000 


0.740 


G=8 


301 


6645.32 


6644.88 


0.112 


G8 


319 


6270.34 


6271.93 


0.424 



NOTE 


DIVISOR 


OUTPUT 
FREQUENCY 


E.T.S. 
FREQUENCY 


CENT. 
ERROR 


F ^8 


338 


5917.87 


5919.91 


0.580 


F8 


358 


5587.26 


558765 


0.117 


E8 


379 


5277.68 


5274.04 


1.160 


D =8 


402 


4975.72 


4978.03 


-0.780 


D8 


426 


4695.40 


4698.64 


1.159 


C=8 


451 


4435.12 


4434.92 


0.076 



3-13 



CO 
00 



a 



Electronic Organ Circuits 



MM5837 digital noise source 



general description 

The MM5837 digital noise source is an MOS/MSI 
pseudo-random sequence generator, designed to produce 
a broadband white noise signal for audio applications. 
Unlike traditional semiconductor junction noise sources, 
the MM5837 provides very uniform noise quality and 
output amplitude. The shift register starts at a random 
non-zero state when power is applied. The circuit is 
packaged in an 8-lead Epoxy-B mini-DIP. 

features 

■ Uniform noise quality 



Uniform noise amplitude 
Eliminates noise preamps 
Self-contained oscillator 
Single component insertion 



applications 



Electronic musical rhythm instrument sound 

generators 

Music synthesizer white and pink noise generators 

Room acoustics testing/equalization 



logic and connection diagrams 



Dual-ln-Line Package 



<]q- 



17 BIT SHIFT REGISTER 



CLOCK OSCILLATOR 




IT 



TOP VIEW 

Order Number MM5837N 

See Package 1 7 



absolute maximum ratings 

Optional Gate Supply Voltage, V GG 

Logic Supply Voltage, V OD 

Storage Temperature, T s 

Operating Temperature, T A 

Lead Temperature (Soldering, 10 seconds) 



V ss - 33V to V ss + 0.3V 

V ss - 25V to V ss + 0.3V 

-55°C to+100°C 

0°Cto+70°C 

300° C 



2 
Ul 
00 

w 



electrical characteristics 

T A within operating range, V ss = 0V, V DD = -14V +1.0V, V GG 



-27V ±2V, unless otherwise noted. 



PARAMETER 



CONDITIONS 



MIN 



TYP 



MAX 



UNITS 



Output (Loaded 20 kfi to V ss 
and 20 kO to V DD 

Logical "1" Level 

Logical "0" Level 

Logical "0" Level 

Supply Currents 
'do 
Igg 

Half Power Point 
Cycle Time 



T A = 25"C 



Vgg =-14V±1V 



No Output Load 



V ss -1.5 
Vdd 
Vdd 



24 
1.1 



Vss 


V 


Vdd + 1-5 


V 


V DO +3.5 


V 


8 


mA 


7 


mA 


56 


kHz 


2.4 


Sec 



3 15 



a 



Electronic Organ Circuits 



MM 5871 rhythm pattern generator 
general description 



The MM5871 rhythm pattern generator is an MOS/LSI 
circuit, fabricated with P-channel enhancement-mode 
and ion-implanted, depletion-mode devices. The PLA 
implementation is programmed to produce 6 rhythm 
patterns which may be combined in any manner and 
provide 5 instrument-trigger outputs. Trigger output 
pulse width is determined by an external RC network, 
(Figure 1). A similar network, including a potentiometer, 
determines tempo of the on-chip oscillator. This circuit 
is packaged in a 16-pin Epoxy-B DIP, (Figure 2). Figure 
3 illustrates the standard pattern coding. Figure 4 is a 
programming worksheet for ordering custom patterns. 

features 

■ On-chip tempo oscillator 

■ Variable output pulse width 

■ 6 rhythm patterns 



■ 5 trigger outputs 

■ Flexible supply voltages 

■ Low power dissipation 

standard patterns 

• Waltz (3/4) 

■ Swing (3/4) 

■ Country/Western (3/4) 

■ March (4/4) 

■ Latin (4/4) 

■ Rock (4/4) 

applications 

■ Electronic organs 

■ Portable rhythm boxes 



block and connection diagrams 



STROBE 
GENERATOR 

~? 



ROCK- 
MARCH- 



} 



SVSTEM 

CONTROL 

LOGIC 



FIGURE 1. 

Dual-ln-Line Package 



TEMPO CONTRO 
POLSE WIOTH CONTROL 



PATTERN 
SELECT 
INPUTS I MARCI 




-SWING (Ei 

■ C0UNTRY/WE5TERN IF 

■ WALTZ (D) 
-SNARE NOISE 

■ BRUSH NOISE 
• BONGO ORUM 
■WOOD BLOCK 
■BASSOHOM 



Order Number MM5871 N 
See Package 19 



3 16 



absolute maximum ratings 



MIN 



MAX 



UNITS 



V G G "33 


0.3 


V 


Vdd "22 


0.3 


V 


-18 


0.3 


V 


T S -55 


100 


°C 


TA o 


70 


"c 


10 seconds) 


300 


°c 



Supply Voltages 

Input Voltage 

Storage Temperature 

Operating Temperature 

Lead Temperature (Soldering, 10 seconds) 



electrical characteristics 

Ta within operating range, Vss = 0V, Vqd = "14V -*-2V, Vqg = -27V ±2V, unless otherwise noted. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Tempo Control Input 


C to Vss = 0.0056 jjF 










Minimum Tempo 


R to Vqd =1-1 MP. 


<2.7 






bps 


Maximum Tempo 


R to Vdd= 120 ko (N ote 1) 






>n 


bps 


Pulse Width Control Input 


Cto Vss = 0.0056 mF 












R to Vqd = 100 ko (Note 1) 


2 


3 


4 


ms 


Select Inputs 












Logic High Level 


(Active Level) 


VSS-O.75 


vss 


Vss + 0.3 


V 


Input Current 


V|H = Vss 






0.2 


mA 


Logic Low Level 




vdd 


vdd 


VDD+0.75 


V 


Trigger Outputs 












Logic High Level 


(Active Level) (w/20k to Vdd) 


Vss-0.37 




VSS + 0.3 


V 


Leakage Current 


V0L= V DD , (Note 2) 






-10 


PA 


Supply Currents 


(No Output Loads) 












!DD 






20 


mA 




'gg 






5 


mA 



Note 1: Both the Tempo Control and Pulse Width Control inputs utilize external RC networks to determine tempo and strobe pulse width. Addi- 
tionally, these parameters are affected by the Vg S V DD voltage. Therefore, for these tests the RC values apply to Vss V DD " 14 ( °' 5 volts - 
Note 2: All trigger outputs are open-drain transistors. The active output level is therefore high, and the off condition is high impedance as indicated 
by the specified leakage current. 



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3-18 




Electronic Organ Circuits 



00 
CO 



MM5891 MOS top octave frequency generator 



general description 

The MM5891 top octave frequency generator is an 
MOS/LSI frequency synthesizer designed to generate 
musical frequencies. The circuit provides 13 semitone 
outputs, which encompass the equal tempered octave. 
The divisor set approximates the 12v'2 semitone interval 
to an accuracy of ±1 .16 cent. 

Low threshold voltage enhancement-mode and depletion- 
mode devices are utilized; the MM 5891 therefore 
operates from a single, wide range power supply. 
Power dissipation is less than 600 mW. The circuit is 
packaged in the 16-pin Epoxy B dual-in-line package. 

Potential RFI emission of the input clock is minimized 
by positioning the clock input between the Vgg and 



Vqd Pins. Chip layout also isolates the clock and output 
buffer areas. Additionally, the outputs are slew-limited 
to reduce RF spectral content of the output signals. 

features 

■ Single power supply 

" Broad supply voltage operating range 

■ Low power dissipation 

■ High output drive capability 

MM5891 AA-50% output duty cycle 
MM5891 AB-30% output duty cycle 



block diagram 



connection diagram 



2.00024 MHz 
CLOCK - 



CLOCK 
DRIVER 



►DD — ►□-»•< 




Dual -In-Line Package 



«ss — 


u 


CLOCK 




«0D — 




4 
451 




5 
-426 — 




6 
402 




7 
379 




8 
-358 





239 
253 
268 



Order Number MM5891N 
See Package 19 



3-19 



absolute maximum ratings 



recommended operating conditions 



(0°C < T A < 50° C) 



Voltage on Any Pin Relative to Vss 
Operating Temperature (Ambient) 
Storage Temperature (Ambient) 



+0.3V to -20V 

0°C to +50° C 

^I0°C to+100°C 





MIN 


MAX 


UNITS 


Supply Voltage (V s s> 








V 


Supply Voltage (V DD ) 


-1 1 .0 


-16.0 


V 



electrical Characteristics 0°C<Ta<50°C; Vss= 0. VdD = -11 to -16V unless otherwise specified 



PARAMETER 



MIN 



TYP 



MAX 



UNITS 



V|H 
VlL 

f| 
ti. tf 

tON. 'OFF 
C| 

vol 

VOH 

tro. 'fo 
tON 

! DD 



Input Clock, High 

Input Clock, Low 

Input Clock Frequency 

Input Clock Rise and Fall Times, 10% to 90% 
at 2.5 MHz 

Input Clock "ON" and "OFF" Times at 2.5 MHz 

Input Capacitance 

Output, Low at 0.70 mA 

Output, High at 0.75 mA 

Output Rise and Fall Times, 500 pF Load 

Output Duty Cycle 
MM5891AA 
MM5891AB- (Pin 16, 50%) 

Supply Current 




VDD*1.0 
100 



2000.240 



200 
5 



VDD + 15 

VSS" io 
250 



50 
30 

24 



-1.0 
VDD 
2500 
30 



10 
VDD 

vss 

2500 



37 



V 

V 

kHz 



pF 
V 
V 



320 



switching time waveform 



en 
oo 

10 




typical performance characteristics 



'SINK vs v OUT 



'source vs v OUT 




0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 
SINK CURRENT TO CHIP(V DD ) 




0.1 0.2 03 04 0.5 0.6 0.7 0.8 0.9 
SINK CURRENT FROM CHIP (V ss ) 



output loading 



Output Loading tf Test 



Output Loading t ro Test 




_L_ 

VOD 

MM5891 

Vss 



"X 



20.75k 



^T>, 500 pF 







SECTION4 
TV CIRCUITS 







00 
CO 

in 



a 



MM5318 TV digital clock 
general description 

The MM5318 digital clock is a monolithic MOS 
integrated circuit utilizing P-channel low-threshold, 
enhancement mode devices. The circuit contains all the 
logic required to give a 4 or 6-digit, 12 or 24-hour dis- 
play from a 50 or 60 Hz input. The digit select inputs 
enable an external digital system to select which digit 
will be available at the BCD and 7-segment outputs. 
An example of this is a television receiver. By using the 
MM5318 with a MM5841 in a television receiver, the 
time of day can be displayed with the TV channel 
selected on the TV screen. The MM5841 determines 
what digit it requires from the MM5318, where on the 
screen it will be displayed and presents the information 
to the TV receiver. The MM5318 is packaged in a 28- 
iead dual-in-line package. 



TV Circuits 



features 

* 12 or 24 hour operation 

■ 50 or 60 Hz input 

■ 4 or 6-digit display 

■ BCD outputs 

■ Digit select inputs 

■ Leading zero blanking in 12-hour mode 

■ High output currents for simplified display interfacing 

■ Single power supply 

applications 

■ TV time display 

■ Computer real time clock 



block and connection diagrams 



ti 



3Z. 



HOUR 
COUNTER 
n OR 24 



V 



3Z 



SECONDS, MINUTES AND HOURS MULTIPLEXER 



I | tr>> 

Ij. decoder 1/ 

^> AND f' 

V ROM «\ 



FIGURE 1. Block Diagram 






MULTIPLEXED 
7 SEGMENT 
OUTPUTS 



Dual-ln-Line Package 



MULTIPLEXED 

BCD OUTPUTS 

(NEGATIVE 

TRUE) 




TOP VIEW 

FIGURE 2. Connection Diagram 



Order Number MM5318N 
See Package 23 



absolute maximum ratings 

Voltage at Any Pin 

Operating Temperature 

Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 



V S S + 0.3V to V S S-20V 

0°C to+70°C 

-65°C to+150°C 

300° C 



electrical Characteristics Ta within operating range, Vqd = 0V, Vgs = 14V +10%, unless otherwise specified. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Power Supply Current 


Vgs = 14V (No External Output Loads 
All BCD Outputs at Logical "1") 


4 




30 


mA 


50/60 Hz Input Frequency 




dc 


50 or 60 


60k 


Hz 


50/60 Hz Input Voltage 












Logic "1" 




VSS-2 


vss 


vss 


V 


Logic "0" 




-2 


VDD 


4 


V 


Digit Select Input Delay 




400 




2000 


ns 


All Logic Inputs 


Internal 20k, Resistor to Vss 










Logic "1 " 


(Except Digit Select Inputs) 


vss-i 


vss 


vss 


V 


Logic "0" 




-2 


VDD 


4 


V 


BCD Outputs 












Logic "1 " 


Output Voltage at Vgs - 2 


2 




10 


mA source 


Logic "0" 


0.01 mA Sink 


VDD 




0.3 


V 


7-Segment Outputs 


Output Voltage at Vgg — 2 










Logic "1" 




2 




20 


mA source 


Logic "0" 








0.01 


mA leakage 


Digit Enable Outputs 












Logic "1 " 


0.1 mA Source 


VSS-0.3 




vss 


V 


Logic "0" 


Output Voltage at Vgs — 2 


5 




15 


mA sink 



functional description 

A block diagram of the MM5318 digital clock is shown 
in Figure 1. A connection diagram is shown in Figure 2. 
Unless otherwise indicated, the following discussions are 
based on Figure 1. 



50 or 60 Hz Drive: This input is applied to a Schmitt 
Trigger shaping circuit which provides approximately 
5V of hysteresis and allows using a filtered sinewave 
input. A simple RC filter such as shown in Figure 6 
should be used to remove possible line voltage transients 
that could either cause the clock to gain time or damage 
the device. The shaper output drives a counter chain 
which performs the timekeeping function. 

50 or 60 Hz Select Input: This input programs the 
prescale counter to divide by either 50 or 60 to obtain 
a 1 Hz timebase. The counter is programmed for 60 Hz 
operation by connecting this input to Vrjp. An internal 
20k pull-up resistor is common to this pin; simply leaving 
this input unconnected programs the clock for 50 Hz 
operation. 

Time Setting Inputs: Both fast and slow setting inputs, 
as well as a hold input, are provided. Internal 20 kJ2 
pull-up resistors provide the normal timekeeping function. 



Switching any of these inputs (one at a time) to Vqq 
results in the desired time setting function. Fast set 
advances hours information at one hour per second and 
slow set advances minutes information at one minute per 
second. The Hold Input stops the clock to the prescale 
counter. 

12 or 24 Hour Select Input: This input is used to 
program the hours counter to divide by either 12 or 24, 
thereby providing the desired display format. The 12- 
hour display format is selected by connecting this input 
to Vpp; leaving the input unconnected (internal 20 kfi 
pull-up) selects the 24-hour format. 

Digital Select Inputs (DX, DY, DZ): These three inputs 
are used to determine what digit will be displayed, Table 
I shows the code for each digit. A logic "1" is when the 
pin is held to Vgg. When the pin is tied to VrjQ, a logic 
"0" results. 

Out put C ircuits: Figure 3 illustrates the circuit used for 
the BCD outputs. Figure 4 shows the circuit used for the 
7-segment outputs. The digit enables output circuit is 
shown in Figure 5. Figures 6 and 7 illustrate typical 
applications for the MM5318. 



4-3 



functional description (Continued) 



output circuits 



TABLE I. Digit Select Code 



DIGIT 

SELECT 

LINES 


DIGIT DISPLAYED 


SI 


S10 


* M1 M10 * 


hi mo 


DX 
DY 
DZ 


1 

1 





1 




110 

11 


1 

1 1 
1 1 



Output blanked 



V SS V SS 




8CD OUTPUT Q 



V SS U SS 




(OPEN DRAIN} 



7SEGMENT 
OUTPUT 



{> 1 




FIGURE 3. BCD Output Circuit FIGURE 4. 7-Segment Output Circuit 



U D0 V DD 

FIGURE 5. Digit Enable Output Circuit 



typical applications 



60 H? fc 
(12V RMS)* 



+ 12V 

4 



FAST SET 

slows: 



:B 



12 HR GNO fe 
24HR+12V 



MODE CONTROL *- 



MM53ia 
17 26 



t^^^nz 



HORIZONTAL 

POSITION 

A0J. 



<4^Hr- 



VERTICAL I i H| ♦ 20 1 

POSITION V it 

ADJ. , —V</V • \— 21 1. 

+,7V ^lOtN I J I T" 



+12VFOR8DIGIT 
GND FOR 5 DIGIT 



TO TV VIDEO 
OUTPUT CIRCUIT 



+12V FOR CHANNEL AND TIME 
GNO FOR CHANNEL ONLY 




FIGURE 6. TV Channel and Time Display 



typical applications (Continued) 



s ,00k ~ik 

:: — i 



0.01.-F 
FAST 



DIGITAL 

SYSTEM 



FIGURE 7. Typical Application 



4-5 




TV Circuits 



MM5320 TV camera sync generator 



general description 



The MM5320 TV camera sync generator is an 
MOS, P-channel enhancement mode, LSI chip 
designed to supply the basic sync functions for 
either color or monochrome 525 line/60 Hz 
interlaced camera and video recorder applications. 
Required power supplies are +5V and — 12V, or 
any other combination resulting in V ss — 17V. All 
inputs and outputs are TTL compatible without 
the use of external components. 



features 

■ Multi-function gen lock input provides flexi- 
ble control of multiple camera installations 

■ 16 lead dual-in-line package 

■ Conventional +5V, -12V power supplies 

■ Uses 2.04545 MHz or 1.260 MHz input ref- 
erence 

■ Field indexing provided for VTR applications 

■ Color burst gate and sync allow stable color 
operation 



logic and connection diagrams 

H>-i 



™% o i_* 



: o- — -• — » 



HORIZ0NTAI SYNC 



HORIZONTAL BLANKING 



vertical blanking 



VERTICAL DRIVE 



EQUALIZATION GATING 



SERRATION GATING 



I 1 



COMPOSITE 
SYNC 
LOGIC 



zr 



COMPOSITE 

BLANKING 

LOGIC 



.J ^ S. „ COLOR BUHS 

^J ^"^ - HORIZONTAL 

" *1 /~" OfllVf OUT 

^1 ^s^ n COLOR BUR! 

" 'I jS~~~~^ S¥NC 0UT 






Dual-ln-Line Package 



v„» — 


, 


u . 


— CQMPSVNC OUTPUT 


DIVIDER CONTROL 


2 


n 


— Hi DRIVE 


ci»c«i»«n — 


3 


i. 


— COMP BLANKING 


Hi RESET 


< 


13 


COLOR BURST SYNC 


VtRT RESET 


6 


12 


COLOR BURST GATE 


RESET CONTROL — 


6 


" 


VERT DRIVE 


NC 


7 


ID 


— NC 


».,- 


8 


9 


— FIELD INOEX 






TOP VIEW 




Order Nl 


mber MMi 


>320N 




See Package 1£ 





4-6 



absolute maximum ratings 

Voltage at Any Pin 

Operating Temperature 

Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 



V ss + 0.3 to V ss - 22 

0°C to +70°C 

-65 X to H50X 

300 X 



dc electrical characteristics 

T A within operating temperature range V ss = +5.0V ±5%, V GG = 12V ±5%, unless otherwise stated. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Input Levels 












Logical High Level (V IH ) 




Vss -1.5 




Vss * 3 


V 


Logical Low Level (V| L ) 




V ss 18 




Vss "4.2 


V 


Input Leakage 


V, N » 10V, T A - 25"C, 
All Other Pins GND 




001 


5 


uA 


Input Capacitance 


V| N ■ 0V, f - 1.0 MHz, 

All Other Pins GND (Note 1) 




3 5 


6.0 


PF 


Clock Input Leakage 


Vim = 10V. T A - 25°C, 
Ali Other P,ns GND 






5 


yA 


Clock Input Capacitance 


V, N = 0V f = 1 MHz, 

All Other Pins GND (Note 1) 




3 5 


60 


PF 


Output Levels 












Logical High Level (V OH ) 


Isouhce ' 0.5 mA 


2.4 




Vss 


V 


Logical Low Level (V OL } 


Isimk ■= 16 mA 






04 


V 


Logical Low Level (V ou ) 


MOS Load 


V ss 12.5 


Vss n 


Vss 90 


V 


Power Supply Current (Iqg) 


T A ' +25'C, V GG -= 12V 

PW = 235 ns, V S5 -- 15.0V 

Input Clock Frequency = 2.04545 MHz 




24 


36 


mA 



ac electrical characteristics 

T A within operating temperature range V ss = +5.0V ±5%, V GG 



1 2V ±5%, unless otherwise stated. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Input Clock Pulse Width (0 PW ) 


Input Clock Frequency - 2.04545 MHz 

0t r ,*t, = 20 ns 


190 


235 


280 




Input Clock Pulse Width |0 PVV ) 


Input Clock Frequency ^ 1 26 MHz 
r*>t r = «t, = 20 ns (Note 31 


520 


546 


570 




Horizontal Reset Pulse Width 


Within 400 ns after the Falling Edge of 
Master Clock (Figure 5) 
Rise and Fall Time = 20 ns 


500 


600 


800 


ns 


Output Propagation Delay (t pd ) 
Logical High Level (V OH ) 
Logical Low Level (V OL | 


Capacitance at the Output ^ 1 5 pF 
(Figure 5) 




500 
500 


750 
750 


ns 
ns 


Field Index Pulse Width 


Within 400 ns after the Falling Edge of 
Master Clock (Figure 5) (Note 2) 
Rise and Fall Time = 20 ns 


500 


600 


700 


ns 



Note 1: Capacitance is guaranteed by periodic testing. 

Note 2: Field index output available only for master clock of 1.26 MHz. 

Note 3: If field index is not required the clock pulse width is 300 ns < Opw < 570 ns 



4-7 



functional description 



EXTERNAL CONTROL LEVELS 

Horizontal Reset occurs for Logic "0," this resets 
the horizontal counter to a state shown in Figures 
2 and 3. 

Vertical Reset occurs for Logic "0," this resets the 
vertical counter to a state determined by reset 
control input as shown below: 



RESET 
CONTROL INPUT 


PERMITS THE VERTICAL 
COUNTER TO RESET TO THE: 


V,„, (V ss ) 

v IL . iVggI 


th count 
1 1 th count 



Logic "0" : 
Logic "1 " : 



Divide select input = V, L , (V GG > for master clock 
frequency of 1.26 MHz. 

Divide select input = V, H , (V ss ) for master clock 
frequency of 2.04545 MHz. 



serration pulse (eleven 0.5H time intervals from 
leading edge of Vertical Blanking) Refer to the 
reset table above. The horizontal divider will 
always be reset to a position which is 8 input clock 
pulses from the leading edge of the serration gate 
in the horizontal timing scheme (Figure 2 and 3). 
The generator is reset to the odd field {field one). 
The Field Index output pulse occurs once each 
odd field at the leading edge of Vertical Blanking. 
It can be used to reset, or "gen-lock," similar sync 
generator chips by connecting it to their Vertical 
and Horizontal Reset inputs. 



OUTPUTS 

The generator supplies the following standard out- 
put functions: Horizontal Drive Out, Vertical 
Drive Out, Composite Blanking Out, Composite 
Sync Out and the Color Burst Gate. 



INPUTS 

The user may select either of two input clock 
frequencies by properly programming the Divider 
Control pin. In one case the input frequency is 
2.04545 MHz; which is 14.318180 MHz divided 
by seven. The other is eighty times the horizontal 
frequency, or 1 .260 MHz. The divider control will 
be programmed by connecting it to V| H (V ss ) and 
ViL' (V GG ) respectively. 

There are separate Vertical and Horizontal Reset 
inputs which allow directly resetting the appro- 
priate dividerfs) by a control pulse generated by 
external means. Both horizontal and vertical divid- 
ers may be reset simultaneously by connecting 
the Vertical and Horizontal Reset pins together 
and driving them with the same reset signal. Actual 
resetting of the vertical divider is to either of two 
states, depending upon the state of the Reset 
Control input; to zero, or to the fifth vertical 



In addition, Field index and Color Burst Sync 
outputs are provided. The Field Index identifies 
the odd field, or field one, by occurring for two 
clock periods at the leading edge of Vertical Blank- 
ing in that field. Thus, its rate is 30 Hz. As de- 
scribed above, it can also be used to "gen-lock" 
other sync generator chips. 

The Color Burst Sync output signal occurs at half 
the horizontal rate with the same timing as the 
Color Burst Gate output. It may be used to sync 
the color burst as it will have the same delay 
characteristics as the other outputs (including, of 
course, the Color Burst Gate) — the color burst 
sync is present during the vertical interval. 

Differences in phasing between outputs are min- 
imized by the use of identical push-pull output 
buffers clocked by the internal clock. 



typical performance characteristics 



Typical 


'gg vs 


Temperature 






-CLOCK FREQUENCY = Z. 04545 MH* 




\ 








! 






\ ! 












*vv = Z35 ns 


















Vss = 50V 








































































j 










































































































































































































































i 










L_i 








, 







I -25 25 50 75 100 
AMBIENT TEMPERATURE CO 



Typical I(3g vs Power Supply 
Voltage (V S S - VqG> 





:lock frequency = 2.04545 MHz 


Ta ■ Z5 C 


! 










Cm = 235 ns 


1 










V GO • -12V 
















1 








/ 










1 










1 















































1 







































Vss - V GG (VI 



4-8 



switching time waveforms 



2 
2 

01 

w 

Is) 
O 



— 1 



L_U 



4- 



i 



u 



4 



T 



= -*-J 



_x_ i 



E 



switching time waveforms (con't) 



MASTER 
CLOCK 

INPUT 



innnnnnjuinnnnjuuinnfuuinnnfuuifuinfuiruiruuL 

t - ■■ HORIZONTAL RESETS TO THIS POSITION 

1— 9T t '0 0692H -i 



~-| 5 T a - n.03WH|— 



~~ ' f— 10 J A : 0.0774 —T~ 

HORIZONTAL SVNC 
"T- 13 T A - 100H -T~ 



t 



HORIZONTAL DRIVE 

22 T 4 -16MM 



HORIZONTAL BLANKING 



— ST„ ~.03(6H — 



FIGURE 2. Horizontal Timing Master Clock = 2.04545 MHz 



1760 MH i SO 



mniuuuimi[iMMuiiMiiuui]uiMii 



SERRATION GATE 



HORIZONTAL RESETS TO THIS POSITION 



6 T e 0.075H U 

— — FRONT PORCH 2 T B O.OZSH 



3T B 0.0375H 
EQUALIZATION GATE 



A 6T B Q.075H U 
HORIZONTAL SVNC 

h8T B 0.1H J 
' B. 

1 



RIVE 

HI, 0.175H 



— 6T B 0.0J5H — - 



HORIZONTAL BLANKING 



ST B 0.03TW 



' COLOR BURST GATE H [T~ 

FIGURE 3. Horizontal Timing Master Clock = 1.26 MHz 



| VERTICAL BLANKING ^ | 

2IH 

U 3H -4- 3H -4- 3H - ~| 



EQUALIZATION GATE 



SERRATION GATE 



VERTICAL DRIVE & HORIZONTAL SYNC INHIBIT 



¥ MASTER C 
(ONCE EAC 



FIGURE 4. Vertical Timing 

4-10 



switching time waveforms (con't) 




MASTER CLOCK 



* 



RESET PULSE 



I 



typical application 



.,£ 



■£> 



■£> 



■£> 



B MM5320 



-£> 



i — — i 

GNO 



Ik, 

■£>- 



-£> 



TTL Interface 




TV Circuits 



MM5321 TV camera sync generator 



general description 

The MM5321 TV camera sync generate is a MOS, 
P-channel enhancement mode, LSI chip designed to 
supply the basic sync functions for either color or 
monochrome 525 line/60 Hz interlaced camera and 
video recorder applications. Required power supplies 
are +5V and --12V, or any other combination resulting 
in Vss — 17V. All inputs and outputs are TTL compa- 
tible without the use of external components. Military 
and commercial temperature ranges are available. 



features 

■ Multi-function gen lock input provides flexible con- 
trol of multiple camera installations 

■ 16-lead dual-in-line package 

■ Conventional +5V, —12V power supplies 

■ Uses 2.04545 MHz or 1.260 MHz input reference 

■ Field indexing provided for VTR applications 

■ Color burst gate and sync allow stable color operation 



logic and connection diagrams 



T O • ► 



"o * ► 



•O-i 



HIZGNTAL SYIKC 



EQUALIZATION 



HORIZONTAL BLANKING 



VERTICAL BLANKING 



VERTICAL DRIVE 



EQUALIZATION GA1 



SERRATION GATING 



I I 



fc. ^s™- COLOR BURST 

* J>~-V GATE OUT 



» ^S_0 HORIZONTAL 

w >* '-'drive OUT 

> ^S . ^ COLOR 8URST 

> >—o SVNC DUT 



J \ COMPOSITE 

\y^ ° SYNC OUT 



J ^- s. „ COMPOSITE 

H .^ ° BLANK QUI 



J\ ) __ VERTICAL 
*[ jS U DRIVE OUT 



-£>-E 



Dual-ln-Line Package 



*GG — 


\ 


u 


H 


— CDMPSYNCDUTPU1 


DIVIDER CONTROL — 


2 




!5 


— Hr DRIVE 


CLOCK INPUT 


3 




14 


COMP BLANKING 


Hz RESET 


4 




13 


COLOR BURST SVNC 


VERT RESET — 


5 




12 


— COLOR BURST GATE 


VERTICAL RESET 

CONTROL 


6 




.. 


— VERT DRIVE 


HORIZONTAL RESET 
CONTROL 


7 




(0 


— OPEN 


vss — 


a 




9 


VERT INDEX 




TOP VIEW 




Order Number MM5321N 




See 


Package 19 





4-12 



absolute maximum ratings 

Voltage at Any Pin 

Operating Temperature 

Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 



dc electrical characteristics 

T/\ within operating temperature range Vgg = 



Vcs + 0.3 to Vgg- 22 

0°C to +70°C 

-65°Cto+150°C 

300° C 



5V +5%, Vqg = -12V ±5%, unless otherwise stated. 



PARAMETER 


CONDITIONS 


MIN 


MAX 


UNITS 




Input Levels 










V|H 


Logical High Level 




Vgg-1.5 


Vss+0.3 


V 


V|L 


Logical Low Level 




VSS-18 


VsS-4.2 


V 




Input Leakage 


V|N = -10V,Ta = 25°C, 
All Other Pins GND 




0.5 


i"A 




Input Capacitance 


V|N = 0V,f = 1 MHz, 

All Other Pins GND, (Note 1) 




6 


pF 




Clock Input Leakage 


V|M = -10V,T A = 25°C, 
All Other Pins GND 




0.5 


uA 




Clock Input Capacitance 


V|N = 0V, f = 1 MHz, 

AM Other Pins GND, (Note 1) 




6 


pF 




Output Levels 










V H 


Logical High Level 


Source ='-o.5 mA 


2.4 


V S S 


V 


vol 


Logical Low Level 


'SINK = 1.6 mA 




0.4 


V 






MOS Load 


Vss-12.5 


VSS-9 


V 


igg 


Power Supply Current 


T A = 25°C, V G G = -12V, 
PPW = 235 ns, V$S = 5 V, 
Input Clock Frequency = 
2.04545 MHz 




36 


mA 



ac electrical characteristics 

Ta within operating temperature range Vgg = 5V ±5%, Vqg = -12V ±5%, unless otherwise stated. 



PARAMETER 


CONDITIONS 


MIN 


MAX 


UNITS 


0PW 


Input Clock Pulse Width 


Input Clock Frequency = 
2.04545 MHz, 0t r , 0tf = 20 ns 


190 


280 


ns 






Input Clock Frequency = 1 .26 MHz, 


300 


570 


ns 






0t r = 0tf = 20 ns 










Horizontal Reset Pulse Width 


Within 400 ns after the Falling Edge 
of Master Clock, (Figure 5) 
Rise and Fall Time = 20 ns 


500 


800 


ns 


tpd 


Output Propagation Delay 










VOH 


Logical High Level 


Capacitance at the Output = 1 5 pF 




750 


ns 


Vol 


Logical Low Level 


/Figure 5) 




750 


ns 



Note 1 : Capacitance is guaranteed by periodic testing. 



4 13 



functional description 

EXTERNAL CONTROL LEVELS 

Horizontal Reset occurs for Logic "0." This resets the 
horizontal counter to a state shown in Figures 2 and 3. 

Vertical Reset occurs for Logic "0." This resets the 
vertical counter to a state determined by reset control 
input as shown below: 



VERTICAL RESET 
CONTROL INPUT 


PERMITS THE VERTICAL 
COUNTER TO RESET TO THE: 


V|H. (V SS ) 

V|L. IVgg) 


0th count 
1 1th count 




HORIZONTAL RESET 
CONTROL INPUT 


RESETS THE HORIZONTAL 
DIVIDER TO: 




Beginning of line 
Center of line 



Logic "0" = V 1 1_ 

Logic "V = V|H 

Divide select input = V||_, (Vqg) for master clock 
frequency of 1.26 MHz. 

Divide select input = V|H, (Vgs) for master clock 
frequency of 2.04545 MHz. 

INPUTS 

The user may select either of two input clock frequencies 
by properly programming the Divider Control pin. In 
one case the input frequency is 2.04545 MHz, which is 
14.31818 MHz divided by seven. The other is eighty 
times the horizontal frequency, or 1.26 MHz. The 
divider control will be programmed by connecting it to 
V IH ( V SS> and V IL. (Vgg' respectively. 

There are separate Vertical and Horizontal Reset inputs 
which allow directly resetting the appropriate divider(s) 
by a control pulse generated by external means. Both 
horizontal and vertical dividers may be reset simultan- 



eously by connecting the Vertical and Horizontal Reset 
pins together and driving them with the same reset 
signal. Actual resetting of the vertical divider is to 
either of two states, depending upon the state of the 
Vertical Reset Control input; to zero, or to the fifth 
vertical serration pulse (eleven 0.5H time intervals from 
leading edge of Vertical Blanking). Refer to the reset 
table. The horizontal divider will always be reset to a 
position which is 8 input clock pulses from the leading 
edge of the serration gate in the horizontal timing 
scheme (Figures 2 and 3). The generator is reset to the 
odd field (field one). The Field Index output pulse 
occurs once each odd field at the leading edge of Vertical 
Blanking. It can be used to reset, or "gen-lock," similar 
sync generator chips by connecting it to their Vertical 
and Horizontal Reset inputs. The Horizontal Reset 
Control selects Horizontal Reset to the start or center 
of a line. 

OUTPUTS 

The generator supplies the following standard output 
functions: Horizontal Drive Out, Vertical Drive Out, 
Composite Blanking Out, Composite Sync Out and the 
Color Burst Gale. 

In addition, Field Index and Color Burst Sync outputs 
are provided. The Field Index identifies the odd field, 
or field one, by occurring for two clock periods at the 
leading edge of Vertical Blanking in that field. Thus, its 
rate is 30 Hz. As described above, it can also be used to 
"gen-lock" other sync generator chips. 

The Color Burst Sync output signal occurs at half the 
horizontal rate with the same timing as the Color Burst 
Gate output. It may be used to sync the color burst as 
it will have the same delay characteristics as the other 
outputs (including, of course, the Color Burst Gate) — 
the color burst s/nc is present during the vertical interval. 

Differences in ohasing between outputs are minimized 
by the use of identical push-pull output buffers clocked 
by the internal clock. 



typical performance characteristics 



Typical \qq vs Temperature 



li-CLC 


C 


<F 


REQ 


HE 


NC 


Y 


= 2.04545 MHi 




^ 
































PW = 235 ns 


















-- 










i .,"" 
















































1 










































































; 


























































' 
























\ 


i 


' 
















i i 1 




L : 






, p 





-50 -25 25 50 75 

AMBIENT TEMPERATURE ("C) 



Typical \qq vs P° wer Supply 
Voltage (V ss - V GG > 



CLOCK FREQUENCY = 2.04545 Mr 


z 


T A = 25' C 










4-J 


,-ipyu - L jd ns 
— V SS = 5V 
Vrr = -12V 




























































































































1 



















16.15 17 17.85 18 

vss- vgg (v) 



4-14 



switching time waveforms 



HORIZONTAL * 5 " 
DRIVE 



! I I I I I II 



COLOR BURST +s - 
GATE 



VERTICAL t5 - 
DRIVE nw 



c. 



'1L. 



^ 



ir— 



t 



— ■ 3H * 3H 



rT 



3H ' 3H 



jit 






*"" ~~ Tfl = Z.04WSMH* " 130 = QM ^ 

"E MuuiiinnjMiiMiiiMrumjiiiniiiuiMMM^M 



HORIZONTAL RESETS TO THIS POSITION 



t— 9T fl 0.0G29H 


j 






SERRATION GATE 


— FRONT PORCH - 3 Ta 


G.0231M 




H5T A 0.03B6h|— 






EQUALIZATION 
GATE 


- 








1— 10 T A 0.0774 

HORIZONTAL SYNC 
13 T A 0.100H 
















HORIZONTAL DRIVE 

22 J A 0.I694H 






~* 


1 






HORIZONTAL BLANKING 








~ |5T fl 0386HJ— 




COLOR 
BURST GATE 



FIGURE 2. Horizontal Timing Master Clock = 2.04545 MHz 



4-15 



switching time waveforms (Continued) 



inniuuuuinniuuuuinnniuuuuinnnii 

<.r„n* T ,<,., ^» TC L. HORIZONTAL RESETS 1 



SERRATION GATE 
6 Toil O.075H 



HORIZONTAL RESETS TO THIS POSITION 



■-H — FRONT PORCH ZT B • 0.025H 



- 3T B • 0.0375M 



EQUALIZATION GATE 



— j 6T B -0.075H U — 
HORIZONTAL SYNC 



8T B -D.1H - 



HORIZONTAL BLANKING 



i COLOR BURST GATE 



3T B • 0.0375H 



FIGURE 3. Horizontal Timing Master Clock = 1.26 MHz 



"L 



VERTICAL BLANKING 



"L 



EQUALIZATION GATE 



SERRATION GATE 



~l 



VERTICAL DHIVE & HORIZONTAL SYNC WHIBIT 



IF 



FIELD INDEX 



FIGURE 4. Vertical Timing 



s 



K 



Display 



v S s- 
ov — 


- 1 


90% 


j \io% / \ 


/ MASTER CLOCK 


— 


- J 






?PVV 


[»., 




Y (v ss -iv) 
A(vss-av) 


OUTPUT 


vss — 


-»■-- t 

\ RESE 


rf ""H 




T PUtSE / 


SESET PULSE 




V7 = V|| L 




V7 = V, H 








FIGURE5. 


FIGURE 6. Horizontal Reset Characteristics 



4-16 



typical application 



r~ ~1 HORIZ 

RESET 






HGRIZ 
RESET 
CONT 



TTL 

Tgnd 



TZ1 



-T> 



-£> 



I CNO 



TTL Interface 



a 



TV Circuits 



MM5322 color bar generator chip 
general description 

The MM5322 Color Bar Generator Chip is a complete 
dot-bar and color hue generation system in a single 
monolithic P-channel MOS integrated circuit. The chip 
divides an internal oscillator (crystal controlled) fre- 
quency to provide the various timing, synchronization, 
and video information required in the alignment of color 
television receivers. A composite video output is pro- 
vided for complete black and white dot-bar operation. 
It consists of all synchronization, blanking, and video 
information required for a fairly standard set of dot, 
bar, and cross hatch screen patterns. In addition a 
separate output for precise gating of 3.56 MHz color 
bursts is provided. For servicing ease an oscilloscope 
trigger is provided on either the horizontal blanking or 
vertical synchronization time slots. 



features 

■ Battery operation 

■ Oscilloscope trigger 

■ Composite video output signal 

■ Crystal controlled oscillator 

■ Multiple screen patterns 

■ Variable dot size 

applications 

■ Battery or bench powered test instruments 

■ Manufacturing test sets 

■ Built in test capability 



typical application 



Typical Color Bar Generator Circuit 



"POWER" INDICATOR 




« — WW— 15V 





Alternat 


ve Resonator 




r - 







1 

1 


j_ 
T 




1 




1 


LI, C 


1 t 
1 

L _ 




— 


1* ! 

i 

l 




PIN 12 0~ 






— 4 


i 


_L 



Note 1: SW 1 should be "ON" only for color patterns. _ _ 

Note 2: Do not substitute Q2. 

Note 3: Variable cap may be used to trim color crystal to exact frequency. 

Note 4: SW 2 and 10k resistor on pins 16 and 1 are needed only if scope trigger pulse is desired. 
Note 5: SW 2 selects "H" or "V" trigger output pulses. 

Note 6: A 27k resistor in series with a 100k trimpot may be used in place of 82k resistor for variable vertical line width. 
Note 7: Modulation level adjusted for best patterns as viewed on TV screen, 

__ 



absolute maximum ratings 

Voltage at Any Pin 

Operating Temperatures 

Storage Temperature 

Lead Temperatures (Soldering, 10 seconds) 



V SS +0.3V to V SS -25V 

-25°C to + 75°C 

-65° C to+150°C 

300°C 



electrical characteristics t 



A within operating range, V ss = +12 to +19V, V GG = 0V 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Power Supply Voltage (V ss ) 




12 




19 


V 


Clock Input Frequency 


Crystal or External 




378 




kHz 


OSC 1 and 2 


Drive (Note 1) 










Clock Input Levels 


For External Drive (Note 11 










Logical High 




Vss-2 




V ss +0-3 


V 


Logical Low 




Vgg 




Vgg + 2 


V 


Control Inputs 


Internal Resistor 










BCD and Trigger 


To V ss , 1M n Min. 










Logical High 


(Note 2) 


Vss-2 




V ss +0.3 


V 


Logical Low 




v GG 




V GG +2 


V 


Control Output Currents 












Cog and Cog 












Logical High 


V ss - 2.0V 


2.5 






mA 


Logical Low 


Vgg - V GG /2 (Note 3) 


0.25 






mA 


Trigger and Z 












Logical High 


With 10k to V GG , 
V GG + 5.0V (Note 4) 


0.5 






mA 


Logical High 


With 1k to V GG , 
V GG + 1 (Note 4) 


1.0 






mA 


Video Output 












Analog Highs 


With 2k to V GG (Note 5) 




2.0 to 4.0 




mA 


Power Supply Current 


T A = 25°C, Freq = 378kHz, 
V GG =0V, V ss = +19V 






30 


mA 



Note 1: The oscillator may be operated with external components to oscillate at 378 kHz or it may be driven by an external pulse source using 

OSC 2 (Pin 13) as an input. 

Note 2: These inputs are driven by switches. 

Note 3: The color gate outputs are push-pull buffers. 

Note 4: The trigger output and Z output are open drain outputs and require a resistor to Vqq for operation. Two possible resistor values are shown 

with their associated voltage and current levels. 

Note 5: The video output requires a resistor to Vqq for operation. This resistor must be trimmed externally to achieve the desired output levels. 

The minimum voltage swing is 4.0 volts with a 10% change with temperature and from unit To unit. The percentage magnitude change with supply 

voltage can approach one. 



composite video output 



~~r — 400 -75 n: 



25 - 32. 5% 




A 3.6 72% 










» 






U BL 








i 




ANK 


i «.L 


ACK 






00°/, 










1 













FIGURE 1. White Dot Video Information Pulse Width 



FIGURE 2. Composite Video Voltage Percentages 



4-19 



composite video output (con't) 




1.26984^ 

UIN 



S H5.Q7g36 ws - 
>Q.65472«s 



4 



_ — _ , Q H H.42856^sMAX 

Note: Line time equals 63.492^s with oscillator at exactly 37B kHz. 



FIGURE 3. Composite Video Rise and Fall Times 



FIGURE 4. Composite Video Pulse Timing, Horizontal Sync 




255.23784tisMAX 
91.74564ysMIN "* 



XJLX 



-190.476.' 1. 90476^5- 



yJc/u 



Note: Frame frequency equals 60.1 14665 Hz. 



FIGURE 5. Composite Video Pulse Timing, Vertical Sync 



VIDEO OUT 
HORIZONTAL SYNC 



-»-; — HORZTSYNC 





0.2 ( ,s 1 
MIN 1 




COG 


\ 




0.2ns 

MAX "*1 


— 



FIGURE 6. Color Gate Signal Timing 



FIGURE 7. Trigger Output Timing Relationship 



4-20 



video output patterns 



15 Horizontal Lines 
0000 



21 Vertical Lines 
0001 



-~^i: : : ri^Hirl": : rr; 



15 x 21 Cross Hatch 
0010 



Gated Rainbow 
0011 



Dots 15 x 21 
0100 



Purity 
0101 















- 










Dots 7x11 
0110 






Single Dot 
0111 



Gated Rainbow 
1000 



Single Vertical Line 
1001 









■j ! 


j j i ..... j 






I l • - J 

... ;_....; .__.. _ ___ 








I- 


; 


i 





7x11 Cross Hatch 
1010 



Single Crosshair 
1011 



Single Horizontal Line 
1100 



7 Horizontal Lines 
1101 



1 1 Vertical Lines 
1110 



Ungated Rainbow 
1111 



4-21 



connection diagram 



Dual-ln-Line Package 



TRIGGER 1 
OUT 


u 


Vss^ 




3 
BCD 1 




4 
BCD 2 — 




5 
BCD 4 — 




6 
BCD 8 




DIFF2 




8 
DIFF 1 





TRIGGER 
' SELECT 



.0 

COG 



COMP 

■ VIDEO 

OUT 



TOP VIEW 
Note ZquT ' s an ' nterna ' counter test point. 

Order Number MM5322N 
See Package 19 



4-22 




TV Circuits 



MM5840 TV channel number (16 channels) and time display circuit 



general description 

The MM5840 TV Channel Number and Time Display 
Chip is a monolithic metal gate CMOS integrated circuit 
which generates a display of channel numbers (up to 
16 channels) and time readouts on the television screen. 



By external connection, it has the option of displaying 
the channel number only while switching channels with 
a period controlled by the external RC time constant of 
a timeout monostable. 



This chip includes all the logic required to provide two 
modes of operation, namely channel number, or channel 
number and time display. 

In addition, it can have a five (hour tens, hour units, 
colon, minute tens, and minute units) or eight digit 
(hour tens, hour units, colon, minute tens, minute units, 
colon, second tens, and second units) display, depending 
on the digit select input logic level. 



By employing the video gating input together with the 
video output, a symmetrical blanked rectangular frame 
around the display may be generated on the TV screen. 



This chip serves as a display generator with BCD channel 
inputs, as provided from the clock chips MM5318, 
MM53100 or MM53105. The position of the display 
on the TV screen can be controlled by adjusting external 
RC time constants. 



functional description 



The channel number and time readout circuit operates 
with a 2 to 4.5 MHz input clock. Counters are incorpor- 
ated in the chip, operated by the input clock to keep 
track of the time slots of the display. 



The position of the display is controlled by adjusting the 
external RC time constants of the horizontal and vertical 
monostable multivibrators. 

A 7-segment decoder is used to decode either channel 
inputs or time which is stored temporarily in the channel 
number buffers or 4-bit latches, respectively, depending 
on the time slot of the display. Each digit of time is 
stored in a 4-bit latch while it is being decoded and 
displayed, and the next digit enters the latch while the 
horizontal sweep is between digits. 

A time slot decoder is employed to decode the appro- 
priate time slot and the digit to be displayed. It 

generates a video output signal that modulates the sweep 
of the television tube for the display on the screen. 

features 

■ 12 or 24-hour operation (controlled by clock chip) 

■ 5 or 8-digit display 

■ Channel number leading zero blanking 

■ Single power supply 

■ Channel number only or channel number and time 
display 

■ Video gating output for generating a symmetrical 
blanked rectangular frame around the display 

■ Oscillator inhibit output 

■ Channel number display only while switching channels 

■ 4-bit binary plus one code for channel numbers 

functions 

■ 8-digit mode is selected by a logic "1" at digit select 
input 

■ Channel number and time mode is selected by a logic 
"1 " at mode input 

■ Permanent channel number display is selected by a 
logic "1 " at timeout monostable input 



connection diagram 





Dual-ln-Line Package 




CHANNEL UNITS 


TIMEOUT 


(BINARY*!) 






NC STABLE i 


1 (4) 12) (1) "V C V VE 



I 27 | 26 



3 



Order Number MM5840N 
See Package 23 



4-23 



absolute maximum ratings 










Supply Voltage (Vqd - Vss> -0.3V to +15V 










Voltage at Any Pin V ss - 0.3V to V DD + 0.3V 










Operating Temperature 0°C to +70°C 










Storage Temperature -55°C to +1 50°C 










Lead Temperature (Soldering, 10 seconds) 300°C 










electrical Characteristics V D D = 12V, V S S = 0V, unless otherwise speci 


fied. 






PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Power Supply Voltage 












VDD 


vss = o 


11 


12 


14 


V 


Power Supply Current 








800 


"A 


Input Voltage Levels 












Time. Oscillator, Digit 












Select, and Mode Inputs 












Logical Low 




Vss-0.3 


vss 


Vss+O.9 


V 


Logical High 




Vdd-0-5 


VDD 


VoD+03 


V 


Channel Inputs 












Logical Low 




V S S -0.3 


VDD-5 


Vqd-4.5 


V 


Logical High 




Vdd-0-5 


VDD 


VdD+0.3 


V 


Horizontal and Vertical Inputs 












Logical Low 




V S S -0.3 


VDD-5 


Vdd-4.5 


V 


Logical High 




VDD-0.5 


VDD 


Vdd+0.3 


V 


Input Frequency 


Interfacing with MM53100, MM53105 


2 




4.5 


MHz 


Oscillato r 


Interfacing with MM5318 


2 




4.5 


MHz 


Horizontal 


Pulse Width = 14 jus 




15.75 




kHz 


Vertical 


Pulse Width - 1 ms 




60 




Hz 


Output Voltage Levels 












Video Gating, Osc. inhibit 












Digit Address and Video Outputs 












Logical Low 




Vss-0.3 


vss 


VsS+0-9 


V 


Logical High 




V DD -0.5 


VDD 


V DD +0.3 


V 


One-Shot Output Pulse Duration 












Horizontal 




15 




50 


us 


Vertical 




1.5 




13 


ms 


Output Drive 












Video Output 












Logical Low 


V SS +1V 


I- II 






mA 


Logical High 


V DD -1V 


1 






mA 


Video Gating and Osc. 












Inhibit Outputs 












Logical Low 


Output Forced Up to Vqq - 4.5V 


i-2l 






mA 


Logical High 


Vdd-iv 


0.2 






mA 


External RC 












CVERTICAL 






0.1 




U-f 


CHORIZONTAL 






0.001 




MF 


RVERTICAL 






50 




kn 


Rhorizontal 






100 




k« 


Ctimeout 






5 




"F 


r timeout 








1 


MP. 


Propagation Delay 












Video Gating and Osc. 


From Input Clock to Oscillator 






2 


clock 


Inhibit Outputs 


Inhibit or Video Gating Outputs 








pulses 


Input Leakage 








1 


"A 


Input Capacitance 








5 


pF 



4-24 



block diagram 



HORIZONTAL 
PULSE 



HORIZONTAL 
ONE-SHOT 



H.TIME 

SLOT 

COUNTER 



H.TiME 

SLOT 

DECODER 



H. DIGIT 
NUMBER 
COUMTER 



DIGIT 
ADDRESS 
DECODER 



6 

DIGIT ADDRESS 
OUTPUTS 



VERTICAL 
PULSE 



I I 



VERTICAL 
ONE-SHOT 



V. LINE 
NUMBER 
COUNTER 



V. LINE 
NUMBER 
DECODER 



TIMEOUT 
MONOSTABLE 
EXTERNAL RC 
CHANNEL ORTOV DO ] TIME 

Q 9 



CHANNEL 
NUMBER 
BUFFERS 



T 



7SEGMENT 
DECODER 



VIDEO 
GATING 
DECODER 



r~* 



TIT 

VIDEO OSC VIDEO OUT 

GATING INri 

OUTPUT OUTPUT 



j DIGIT 
SELECT 



truth table 



timing diagram 



Digit Address (DX, DY, DZ) Codes 



CODES 


DURING 
RESET 


1 2 


3 


DIGITS 

4 5 


6 


7 


8 


DX 


1 





1 


1 





1 


1 


DY 


1 


1 








1 


1 


1 


DZ 


1 


1 1 


1 











1 



With Video Gating, Output Gated with Video Output 



HORIZ. 
RETRACE 



HORIZ. TIME 
OUT 



-ADJUSTABLE 



4-25 



o 
<* 

00 

in 

2 



typical applications 



Horizontal and Vertical One-Shot Circuit 

PORTION ON CHIP 



v 

J 



ATION 
UHIBIT 

UTPUT 



INPUT J~~l OUTPUT 

^FIGURATION I CONFIGURATI 

FOR CHANNEL — I i •— FOR OSC INHII 

INPUTS AND T VIDEO OUTPU 

NTROL INPUTS j_| OIGITSELECT 

Hi 

"1 



J J I 



Hi 



Hi 



ih 



Hi Hi iH 

1 T 1 



'hi 



"H 



!~U 



TV Channel and Time Display Interfacing MM5318 



0.01 +12V 



JUT 




TO TV VIDEO 

OUTPUT CIRCUIT 



-< + 12V 

fROMTV 
AA/^ < HORIZONTAL 

RETRACE 



_n_n_„ 



HORIZONTAL 

POSITION 

ADJ. 



DIGIT SELECT +12V FOR 8 DIGIT 

GND FOR 5 DIGIT > 

MODE CONTROL +12V FOR CHANNEL AND TIME ^ 

GND FOR CHANNEL ONLY * 



4-26 



typical applications (Continued) 

TV Channel and Time Display Interfacing MM53100 



35 



f 



J,, Jmmhi] 



IT h 



JUL 



MANUAL TV "ON" 

MANUAL TV OFF" 

DISPLAY SELECT 

ENABLE 
STANDBY 



- ' T 50/60 H 

^■y ^ SELEC1 



NORMALLY 

HAROWIREG 

FOR EACH 

APPLICATION 



| v ss 



SCO 2 

Bcoa 
Bcoa 




FROM TV 
AAAf < HORIZONTAL 
RETRACE 




MODE CONTROL -1ZV FOR CHANNf I AND TIWE 



! CHANNf I AND TIWE -^ 
FOR CHAf^NFI Oil Y ^ 

Note. For interfacing with MM53105, refer to MM53105 specifications. 



4-27 




TV Circuits 



MM5841 TV channel number and time readout circuit 



general description 



The MM5841 TV Channel Number and Time Readout 
Circuit is a monolithic metal gate CMOS integrated 
circuit, which generates a display of channel number 
and time readouts on the television screen. 

This chip includes all the logic required to provide two 
modes of operation, namely channel number, or channel 
number and time displays. 

In addition, it can have a five (hour tens, hour units, 
colon, minute tens, and minute units) or eight digit 
(hour tens, hour units, colon, minute tens, minute units, 
colon, second tens, and second units) display, depending 
on the digit select input logic level. 

This chip serves as a display generator between the 
BCD channel inputs, the clock chip (MM5318) and the 
television set. The position of the display on the TV 
screen can be controlled by adjusting the external RC 
time constants. 



functional description 

The channel number and time readout circuit operates 
with a 4 MHz input clock. Counters are incorporated in 
the chip, operated by the input clock to keep track of 
the time slots of the display. 

The position of the display is controlled by adjusting the 
external RC time constants of the horizontal and 
vertical monostable multivibrators. 



A 7-segment decoder is used to decode either channel 
inputs or time which is stored temporarily in the channel 
number buffers or 4 bit latches, respectively, depending 
on the time slot of the display. Each digit of time is 
stored in a 4-bit latch while it is being decoded and 
displayed, and the next digit enters the latch while the 
horizontal sweep is between digits. 

A time slot decoder is employed to decode the appro- 
priate time slot and the digit to be displayed. It 
generates a video output signal that modulates the sweep 
of the television tube for the display on the screen. 



features 

■ 12 or 24 hour operation (controlled by clock chip) 

■ 5 or 8 digit display 

■ Channel number leading zero blanking 

■ Single power supply 

■ Channel number only or channel number and time 
display 



functions 

■ 8 digit mode is selected by a logic "1 " at digit select 
input 

■ Channel number and time mode is selected by a 
logic "1" at mode input 



connection diagram 



CHANNEL TENS 



Dual-ln-Line Package 

CHANNEL UNITS 



.4} (?) (II (8| (A) 12) (1) R v 

128 1 27 26 |2S ] 24 23 22 I?! 



(3) DIGIT DZ OV OX MODE OSC 5 MHz V Di 

'SELECT' y ' INHI6 CLK 

DIGIT ADDRESS 
TOPVIEW 



Order Number MM5841N 
See Package 23 



4-28 



absolute maximum ratings 

Supply Voltage (V DD - V ss ) 

Voltage at Any Pin V £ 

Operating Temperature 

Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 



-0.3V to + 15V 

-0.3V to V DD + 0.3V 

0°Cto+70°C 

-55°Cto+150°C 

300 °C 



electrical characteristics 

V DD = 12V, V ss = 0V, unless otherwise specified. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Power Supply Voltage 












Vdd 


V ss = 


11 


12 


14 


V 


Power Supply Current 








800 


UA 


Input Voltage Levels 












Time, Oscillator, Digit Select, 












and Mode Inputs 












Logical Low 




V ss -0.3 


Vss 


V s s +0.9 


V 


Logical High 




V DD -0.5 


Vdd 


V DD T0.3 


V 


Channel inputs 












Logical Low 




V S s-0.3 


V dd -5 


Vdd-4.5 


V 


Logical High 




V DD -0.5 


Vdd 


Vqd+0.3 


V 


Horizontal and Vertical Inputs 












Logical Low 




V 3s -0.3 


Vdd-5 


Vd D -4.5 


V 


Logical High 




V DD -0.5 


Vdd 


Vdd+0.3 


V 


Input Frequency 












Oscillator 




1 


4 


4.5 


MHz 


Horizontal 


Pulse Width - 14/i.s 




15.75 




kHz 


Vertical 


Pulse Width -= 1 ins 




60 




Hz 


Output Voltage Levels 












Oscillator Inhibit, Digit Address 












and Video Outputs 












Logical Low 




Vss -0.3 


Vss 


Vss-0.9 


V 


Logical High 




V DD -0.5 


Vdd 


Vdd+0.3 


V 


One-Shot Output Pulse Duration 












Horizontal 




15 




50 


JJS 


Vertical 




1.5 




13 


ms 


Output Drive 












Video Output 












Logical Low 


V ss + 1.0V 


i-1 






niA 


Logical High 


V DD -1.0V 


1 






mA 


Oscillator Inhibit Output 












Logical Low 


Output Forced Up to V OD - 4.5V 


•■21 






mA 


Logical High 


V DD - 1.0V 


0.2 






mA 


External RC 












•^VERTICAL 






0.1 




h<F 


^HORIZONTAL 






0.001 




hJF 


^VERTICAL 






50 




kH pot 


^HORIZONTAL 






100 




kf2 pot 


Propagation Delay 












Oscillator Inhibit Output 


From Input Clock to Oscillator 
Inhibit Output 






2 


clock 
pulses 


Input Leakage 








1 


juA 


Input Capacitance 








5 


pF 



00 



4-29 



00 

in 
2 



block diagram 



timing diagram 



HORIZONTAL 
ONE SHOT 



H. TIME 

SLOT 
COUNTER 



H. DIGIT 
NUMBER 
COUNTER 



H.TIME 

SLOT 

DECODER 



DIGIT 
ADDRESS 
DECODER 



o 

DIGIT ADDRESS 
OUTPUTS 



T J I 



V. LINE 
NUMBER 
COUNTER 



V. LINE 
NUMBER 
DECODER 



CHANNEL 
NUMBER 
BUFFERS 



s_? 



OSC INHIBIT 
OUT 



j DIGIT 
SELECT 



OSCILLATOR 






INHIBIT 




DECODER 









,^„ 



I I 



T 



VERTICAL 
TIME OUT 



HORIZ. RETRACE 



IT 



HORIZ. TIME 
OUT 



J= 



nn n n n 



VIDEO 
OUTPUT 



CHARACTER 
DISPLAYED 



typical applications 



rl! 



J 



INPUT 

CONFIGURATION 

FOR CHANNEL - 

INPUTS ANG 

CONTROL INPUTS 



OUTPUT 

CONFIGURATION 
- FOR DSC INHIBIT, 
VIDEO OUTPUT. 
DIGIT SELECT 



Hi 



1 



T^ 



rl! H 



"L, 



CTT 



£ 

Hi Hi iH 

1 T H 



« 1 1 i »- — i ► 



"H -r 



.» — I r 

UT LI 



-^. 



Horizontal and Vertical One-Shot Circuit 



4-30 



typical applications (con't) 

ooj -, 2 „ 



jH 



FAST SET | 

SLOWSET L ■■ 
HOLD • — 



TT 



JUT 



-X- 



Y OFF \ 



CHANNEL 
TENS 



2>" 



MOOE CDMTROL +12V FOR CHANNEL AND TIME .. 

GND FOR CHANNEL ONLY *~ 



2 
00 




JUUL 



FROM TV 
•VW— — < HORIZONTAL 
RETRACE 




"^ li 

-M- 



HI— 1 — y& — n 
' /100k 



ERTICAL 
POSITION 
AOJ 



TV Channel and Time Display 



4-31 




TV Circuits 



MM53100, MM53105 programmable TV timers 



general description 



The MM53100 and MM53105 programmable TV timers 
are monolithic CMOS integrated circuits utilizing P and 
N-channel low threshold enhancement devices. These 
circuits contain all the logic to give a 4 or 6-digit, 24- 
hour display from a 50 or 60 Hz input, and control the 
"ON" time of the TV. The duration of the viewing 
period is 5, 10, 20 or 30 mins, selected by 2 input 
pins. Manual "ON" and "OFF" inputs are also provided. 
The MM53100 and MM53105 have ultra-low power 
dissipation in the stand-by mode and are ideally suited 
to crystal controlled battery-operated systems. The 
MM53100 is designed for an optimum interface in 
TVs with a positive common reference voltage (e.g., 
+ 18V). The MM53105 Is designed for an optimum 
interface for TVs with a 0V reference voltage. Both are 
packaged in a 24-lead dual-in-line epoxy package. 



features 

■ 50 or 60 Hz operation 

■ 24-hour display format 

■ Programmable TV on time 

■ Selectable view time 

■ Ultra-low power dissipation 

■ All counters resettable 

■ Low voltage operation 

■ Elimination of illegal time display at turn-on 

■ Daily repeat or non-repeating operating 

■ Fool-proof safety features 

■ Compatible with MM5840 or MM5841 display circuits 

applications 

■ TV time display 

■ Remote TV "ON'V'OFF" switch 

■ Computer clock 

■ Time data — logging systems 



block diagram 



SO/60 Hi 
SELECT 



SET 
MINUTES 



SET 
HOURS 



PRE-SCALE 
COUNTER 
50 OR SO 



SECONDS 
COUNTER 



50/60 Hz 
DRIVE ' 



SHAPING 
CIRCUIT 



MINUTES 

COUNTER 

60 



DIGIT "V 

DECODER __^ 



o \> 



mrn 



HOURS 
COUNTER 



id 



MINUTES 
COUNTER 



\S \7 



SECS, MINS AND HRS MULTIPLEXER 



DISPLAY 
SELECT " 



ENABLE - 

MAM "ON" - 

MAN "OFF" ■ 

STANDBY - 



HOURS 
COUNTER 



i& 



\Z \7 



COMPARATOR 



"OFF" 
COUNTER 



CONTROL LOGIC 

AND 

0/P BUFFERS 



MULTIPLEXED 
BCD 0/PS 



FIGURE 1. MM53100, MM53105 Block Diagram 



" x PERIOD 
. Y SELECT 



-► AUTO "0N"0/P 
-► VIEW PERIOD 0/P 



4-32 



absolute maximum ratings (MM53100) (VqD common voltage reference) 






Supply Voltage (X/qd - Vss) 6V 






Voltage at 50/60 Hz Select and Period Vss - 0.3V to Vqd + 0.3V 






Select Inputs 






Current Into or Out of Any Other Input 100 ^A max 






electrical Characteristics (MM53100) T A = 25°C, Vqd = 4.5V, V SS = 0V unless otherwise specified. 




PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Supply Voltage 




2.8 




5.0 


V 


Supply Current 


V DD -4.5V 




10 


25 


MA 


Input Logic Levels 












50/60 Hz Input, Digit Select 












Inputs, Display Select, "ON", 












"OFF", Time Setting Control, 












Standby Control 












Logic "1 " 




VDD-0.5 




VDD 


V 


Logic "0" 


(Note 11 






Vss+0.5 


V 


50/60 Hz Select, Period Select 












(X, Y) 












Logic "1 " 




VDD-0.5 




VDD 


V 


Logic "0" 




vss 




VSS+0.5 


V 


Display Select Input Delay 




0.5 




2.0 


us 


Output Logic Levels 












BCD Outputs 


External Resistor, 15 kO to 
V DD - 12V, C L = 15 pF 










Logic "1" 




VDD 0.8 






V 


Logic "0" 








Vdd-H 2 


V 


Note 1: If input voltages go more negative than Vss, tne input current must be limited to a maximum 


of 100 /jA by the use of external series 


resistors. No resistors are required on the Dx, D Y , Dz inputs when interfacing with the MM5840. 






absolute maximum ratings (MM53105) (Vss common voltage reference) 






Supply Voltage (Vqd - Vss) 6V 






Voltage at 50/60 Hz Select and Period Select Inputs Vss + 6V 






Voltage at Any Other Pin Vss + 13V 






electrical characteristics (MM53105) t a = 25°c, v DD = 4.5v, vss = ov uni 


ess otherwise specified. 




PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Supply Voltage 




2.8 




5.0 


V 


Supply Current 


V DD = 4.5V 




10 


25 


HA 


Input Logic Levels 












50/60 Hz Input, Digit Select 












Inputs, "ON", "OFF", Display 












Select, Time Setting Controls, 












Standby Control 












Logic "1 " 




Vqd-0.5 




13 


V 


Logic "0" 




vss 




Vss+0-5 


V 


50/60 Hz Select, Period Select 












(X, Y) 












Logic "1 " 




Vdd-0-5 




VDD 


V 


Logic "0" 




vss 




Vss+0.5 


V 


Display Select Input Delay 




0.5 




2.0 


Us 



4 33 



electrical Characteristics (Continued) (MM53105) Ta = 25°C, Vqd = 4.5V, Vss = OV unless otherwise specified. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Output Logic Levels 












BCD Outputs 


External Resistor 15 kil to 12V, 
C L = 15pF 










Logic "1 " 




11.2 






V 


Logic "0" 








0.8 


V 


TV "ON" Output, Auto 












"ON" Output, View Period 












Output 












Logic "1" 


Loaded 2.7 kS2 to Vss 


0.5 






mA 


Logic "0" 


Loaded 2.7 k<2 to Vqd 


1.0 






mA 



Note 1: Input voltages to go more positive than Vqq. 



functional description 

A block diagram of the MM53100, MM53105 TV timers 
is shown in Figure 1 . A connection diagram is shown in 
Figure 2. Unless otherwise indicated, the following 
discussions are based on Figure 1. Figures 5a and 5b 
illustrate the system configuration for a crystal controlled 
TV display system using both circuits. 

Dual-ln-Line Package, Top View 



Vdd — 

2 



STANDBY 




ENABLE 


7 


TV "ON" 


8 


OUTPUT 




VIEW 


9 


PERIOD 




AUTO "ON" 


10 


PERIOD 


11 


SELECT X 




PERIOD 


12 


SELECT Y 





TJ I* 



22 „ 

— D Z 



50/60 Hi SELECT 

20 

■ 50/60 Hz DRIVE 

• HOLD 

- SEt HRS 

- SETMINS 

— DISPLAY CONTROL 



13 

— vss 



Order Number MM53100N or MM53105N 
See Package 22 

50 or 60 Hz Drive: This input is applied to a Schmitt 
trigger shaping circuit which allows use of a filtered 
sinewave input. A simple RC filter should be used to 
remove possible line voltage transients that could either 
cause the clock to gain time or damage the device. The 
input should swing between Vgs and Vr}r> Tne shaper 
output drives a counter chain which performs the time- 
keeping function. 

Alternatively, in a crystal controlled battery operated 
system, an oscillator and prescaler such as the MM53107 
could be used as a time base. 



50 or 60 Hz Select Input: This input programs the 
prescale counter to divide by either 50 or 60 to obtain a 
1 pps time base. The counter is programmed for 60 Hz 
operation by connecting this input to Vdd- An internal 
1 Mf2 pull-down resistor is common to this pin; simply 
leaving this input unconnected programs the clock for 
50 Hz operation. 

Time Setting Inputs: Inputs to set hours and set minutes 
as well as hold input, are provided. Internal 1 MS' 
pull-down resistors provide the normal timekeeping 
function. Switching any 1 of these inputs (1 at a time) 
to "1" results in the desired time setting function. Set 
Hours advances hours information at 1 hour/second and 
Set Minutes advances minutes information at 1 minute/ 
second, without roll over into the hours counter. Set 
Minutes also resets the seconds counter to 0. The hold 
input stops the clock to the minutes counter and resets 
the seconds counter. Activating Set Minutes and Set 
Hours simultaneously resets the displayed counters 
to all O's. 



Display: This input controls the display and time- 
setting operation. It has an internal 1 MS2 pull-down 
resistor to Vgg. When taken to Logic "0" or in open 
circuit condition, the real time is displayed and the Set 
Hours and Set Minutes inputs operate the real time 
counters. When taken to logic "1", the "ON" time is 
displayed and the time-setting inputs operate on the 
"ON" counters. 

Digital Select Inputs (Dx, Dy, Dz): These 3 inputs are 
used to determine which digit will be displayed. Table IA 
shows the code for each digit. Seconds will be displayed 
as "00" when the "ON" time is being displayed. 

Enable: This input has an internal resistor to Vss. 
When taken to logic "1", this input disables the pro- 
grammed "ON" time for the TV output. 

Period Select Inputs (X, Y): These inputs have pull- 
down resistors to VgS- They determine the view period, 
i.e., 5, 10, 20 or 30 mins. Table IB shows the Period 
Select Code. 



4-34 



functional description (continued) 

Standby Control Input: This input has an internal 
resistor to Vgs^ Its function is to sense when the line 
generated 12V supply is turned off and to then disable 
the outputs. In the TV, this input should be connected 
to the 12V supply. 



period, a signal on the manual "ON" input will prevent 
the automatic switch-off. 

Manual "OFF" input will always reset the output to a 
logic "1 " state. 



Manual "ON" Input: This input has an internal resistor 
to VgS' When taken to logic "1", this input turns the 
TV output to the "0" state. It is designed to have 
typically 0.75 second debounce time to prevent mal- 
operation. 



Manual "OFF" Input: This input has an internal resistor 
to VgS- When taken to logic "1", this input turns the 
TV output to the "1" state. It is designed to have 
typically 0.75 second debounce time to prevent mal- 
operation. 

TV "ON" Output: Figure 3 illustrates the CMOS 
inverter output circuit used. 

In the manual mode of operation, the manual "ON" 
input sets this output to "0", the manual "OFF" input 
resets this output to "1". The manual "ON" input 
inhibits the auto "ON" output. 

In the programmable mode, this output goes to "0" 
when the programmed "ON" time coincides with the 
real time (unless enable = 1). The output will then 
stay at "0" for the selected period of 5, 10, 20 or 30 
minutes before returning to "1" state. During this 



Auto "ON" TV Output: An additional output is pro- 
vided to indicate that the TV is "ON" in the automatic 
mode of operation. This output goes to a logic "0" 
for the duration of the auto "ON" time. Manual "ON" 
switches this output back to a logic "1". 

View Period Indicator: This output normally is a 
logic "1", When the TV switches on at the programmed 
time, this output transmits a 1 Hz waveform for the 
duration of the selected view period. Hence, it can be 
used to indicate that the TV is switched on for a limited 
period only by means of a flashing on-screen and/or 
off-screen display. The output will permanently return 
to "1 " at the end of the viewing period or when a valid 
manual "ON" or "OFF" input signal is received during 
the view period. 

BCD Outputs: Figure 4 illustrates the open drain output 
circuits used, a) MM53100, b) MM53105. 

With the use of the external respective pull-up and pull- 
down resistors, these outputs are designed to be com- 
patible with the MM5840 and MM5841 TV display 
circuits. 

Note. Case (a) for common Vqq, case (b) for common 
V SS when used with the MM584Q, 



TABLE IA. Digit Select Code 



DIGIT SELECT 
LIMES 


DIGIT DISPLAYED 


SI 


S10 


» 


M1 


M10 


* 


HI 


H10 


DX 


1 








1 


1 








1 


D Y 


1 


1 














1 


1 


°Z 














1 


1 


1 


1 



TABLE IB. Period Select Code 



PERIOD SELECT 


VIEW PERIOD 


INPUTS 


PROGRAMMED 


X Y 







5 mins 


1 


10 mins 


1 


20 mins 


1 1 


30 mins 






FIGURE 3. CMOS Output (TV 
"ON", Auto "ON", Indicator) 



FIGURE 4a. BCD Outputs, MM53100 FIGURE 4b. BCD Outputs, MM53105 



4 35 



functional description (Continued) 



Z-CELL T 

IATTERY I 



DISPLAY SELECT 



EIMABLE 

STANDBY 



^ 



J__L 



-" l 



ON" O/P 
— ► AUTO "ON" 0/P 
-+■ VIEW PERIOD O/P 



TT 




■ TV VIUEO Q/P CCT UBV! 




^ POSITION ADJUST 



-W\ HORIZ RETRACE 




-VW VERT RETRACE 



FIGURE 5a. Typical System Diagram, MM53100 



3V_J_ 

2«LL T 
BATTERY 1 



ft 



DISPLAY SElfCT 

ENABLE 

STANDBY - 

PERIOD SELECT 



2 CELL 

Him Hi BATTEHY 
SELECT JV 



2 





-► TV'QN"0/P 
-► AUTO "OftTOP 
-► VIEW PERIOD OP 



If 




- TV VIDEOO/PCCT 



POSITION ADJUST 



-^^\ hORIZ RETRACE 




-^ VERT RETRACE 



FIGURE 5b. Typical System Diagram, MM53105 



4-36 




TV Circuits 



MM57100 TV game circuit 
general description 

The MM57100 TV Game Chip provides all of the logic 
necessary to generate backgrounds, paddles, ball and 
digital scoring for three games: Hockey, Tennis and 
Handball. All games are in color and have sound. The 
MM57100 was designed for low system cost and is 
aimed at the high volume consumer marketplace. It 
generates all the necessary timing (sync, blanking and 
burst) to interface to a standard TV receiver, and inter- 
faces directly to the antenna terminals of a TV with 
the addition of a chroma, audio and RF modulator. 
If mounted directly into a receiver, much of this circuitry 
can be eliminated. The chip requires the true and 
complement clocks of 1.0227 MHz (3.579545 MHz -H 
3.5). Figure 1 shows a block diagram of a complete 
TV Game System. 

The paddles for the games are controlled by two external 
RC networks. R and C provides for full screen movement 
by developing a time delay of about 16.5 ms. For 
Hockey and Tennis, each of the player paddles can be 
made to be either large, medium or small in size, thus 
allowing for handicapping. The size of a player paddle 
is modified by moving the paddle to either the top or 
bottom boundary and depressing the game reset button. 
In Handball, the players can modify the paddles as 
described above, but both players must use the same 
size paddle. 

Single player "practice," can be created by connecting 
the two player paddle input lines on the MM57100 to a 
single external RC network. Single player operation can 
be achieved for all three games. Thus the MM57100 
can actually play six games— three single player games 
and three dual player games. 

The player paddles are divided into nine different areas 
that define eight angles at which the ball will reflect 
upon incidence. The top-most area of the player paddle 
will reflect the ball with the most upward direction, 
the areas towards the bottom will reflect the ball with 
the most downward direction. And the very bottom of 
the paddle will cause the ball to go up at a sharp angle, 
simulating a "wood" or handle shot. The areas in between 
will give reflections with less of an angle. There are two 
areas in the center of the player paddle which will make 
the ball have zero vertical velocity. The player paddles 
are transparent in one direction so that in Hockey the 
ball can rebound off the back wall and pass through the 
defensive player paddle. The machine paddles in Hockey 
are also transparent in one direction. 

The ball is always served by the player who won the 
last point. The serve comes about 1.6 seconds from the 
time of the score and it is served from the paddle. This 
allows for a more realistic situation: the server can 
"place" his shot. After four player paddle hits, the ball 
speeds up to twice the initial velocity. Each time the ball 
strikes an object, a signal is generated at the audio 
output for the duration of the frame and one more full 
frame. When the ball strikes the boundaries or a machine 



Note. SK1115 NTSC kit includes: MM57100N, 
MM53104N and LM1889N. 
Note. SK1120 PAL kit includes: MM57105N, 
MM53104N and LM1889N. 



paddle, it bounces off the object under the rule that the 
angle of incidence is equal to the angle of reflection. 
Regardless of the angle that the ball is traveling as it 
hits the front of the player paddles, it will reflect as a 
function of which segment it hits. 

The score is automatically blanked when the ball is put 
into play. It remains blanked until a miss is recorded 
and it is then properly incremented and displayed. The 
game is completed when one of the players reaches 15 
points. At this time, the score remains on and the serve 
is inhibited until the Game Reset is depressed. Both the 
Game Reset and Game Select inputs are debounced for 
16.5 ms. 

The video output signal contains horizontal and vertical 
blanking, horizontal and vertical sync and the black'and 
white information necessary to generate the picture 
on a TV receiver through the antenna input. The picture 
is not interlaced. Chroma outputs provide the color 
and burst information and are properly timed with the 
video. 

features 

■ Three games: Hockey, Tennis and Handball 

■ All games in full color 

■ Ball speed doubles after fourth hit 

■ Segmented paddles for automatic ball spin 

■ Adjustable paddle size/handicapped play 

■ Automatic digital scoring 

■ Sound 

■ Serve from paddles 

■ Designed to interface with a minimum effort to a 
standard television receiver 



connection diagram (dip Top v 



RIGHTPADOLE — 


\J> 


LEFTPAOQLE — 




TEST — 




Vdd — 




S 

AUDIO 




VI0E0 




Vbiasa — 




CHROMA A 




CHROMA B 




«»,««-!£ 




Nt-H 




Vss-H- 





/iew) 



GAMESELECT 



23_GAME RESET/ 
PADDLE SIZE 



NTSC Order Number MM57100N 

PAL Order Number MM57105N 

see Package 22 



4-37 



300k — ■ — 

I 0.03: 



A if — 

Ok | 



JQ.03: 



|13 |1S 

CLOCK :2 CLOCK ■'.■,} 
CHROMA A 
CHROMA B 
BIAS A 
BIAS 8 

VIDEO 



RIGHT 



F¥j 



MM53104N 
DIVIDE 

BV 3 1/2 



1 



FIGURE 1. Video Game System Diagram 



GAME DESCRIPTION 



Tennis 



Tennis consists of a green court with a blue border, 
a yellow net, orange paddles and a light green ball. 
It is played by two players who, through the use of their 
individual controllers, can vertically raise or lower their 
paddles. Play starts when the machine automatically 
serves the ball cross court. This can be from either the 
left or the right. The player who is served must hit the 
ball back to his opponent, who must then return it. 

As the volley begins, the speed of the ball increases once, 
making it more difficult to return. The speed change 
occurs on the fourth hit. When either player misses the 
ball, a point is scored for his opponent and the next 
serve comes to him after a wait of 1.6 seconds. To 
increase the play value, the ball can bounce off both 
the top and bottom walls. In addition, before the play 
begins, each player can choose a large, medium or small 
paddle, depending on his playing skill. The paddles 
are sectioned, giving a "spin" effect to the ball. 

The score, which is yellow, is automatically displayed in 
large, easy-to-read numerals. The score appears when 
the ball is missed and remains on until the ball is served. 
Play ends when the first player reaches 15 points. At the 
end of the game, the score remains on until the game 
is reset. 



Since each player has four men who can return the 
puck, the play is very fast. To make it even more diffi- 
cult, a point can only be made when the puck slips 
through either player's goal — a small opening located 
directly in the middle of the side walls. Since only a 
small portion of the left and right walls is used for 
scoring, the puck can essentially rebound off all four 
walls. Scoring is the same as in tennis — first player to 
reach 1 5 is the winner. The score is yellow. 

Handball 

Handball consists of a brown court, two paddles — one 
blue and one orange, and a yellow ball. It plays identical 
to tennis except only one player plays at a time and 
both are on the same side of the court, playing against 
the opposite wall. After the ball is served, the serving 
player disappears from the screen and the other player's 
paddle appears. He must hit it, or he loses the point and 
the other player serves again. If he hits it, his paddle 
disappears and the other paddle comes on the screen. 
The other player must return it to the wall. The object 
of the game is to keep the ball in play by continuously 
hitting it to the back court wall. The ball can be reflected 
off three sides - the top, bottom and right wall. The 
first player to score 15 is the winner. The score colors 
match the paddle colors - one blue and one orange. 



Hockey 

Hockey consists of a blue playing field which is sur- 
rounded by yellow walls, two yellow player-controlled 
goalies, six light yellow machine-controlled forwards 
and a light blue hockey puck. 

Hockey, while similar to tennis, is a much faster and 
more exciting game. Each player controls only his 
goalie, who moves in a vertical motion. In addition, 
each player has three forward men who also move 
vertically. These men are not under player control but 
move up and down, as a group, automatically. As in 
tennis, the opening serve comes cross court and can 
come to either player. Further serves are to the player 
who has just lost a point. 



SUMMARY 

Table 1 describes how the game will appear on a standard 
25" TV. The actual appearance will vary somewhat 
from set to set as a function of color control settings, 
fine tuning, overscan, etc. Table 2 and Figure 10 define 
the Chroma Outputs and the approximate color they 
generate. 



SYSTEM CONFIGURATION 

Figure 2 is a detailed schematic of how the MM57100 
TV Game Chip would appear in a completed system, 
including the MM53104 clock generator and the LM1889 
channel modulator. 



4-38 





.►3^, p^4 | — | J — [I 

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lo u £ 



d en <t o o a 
a > - 







H" 




4 39 



dc electrical characteristics o°c<ta<75°c 



PARAMETER 



Operating Supply Voltages 

VSS- V DD 

vss- VGG 
Operating Supply Current 



Idd 




Igg 






Osc. Input Levels, 01, r/>2 




(Figure 3} 


VlH 


Logical High Level 


VlL 


Logical Low Level 




Chroma A Output Levels 




(Figure 41 



\J A ^ A1 =0.465 x (Vcs- V DD> 

Roai Output Impedance 

V A AO = 0.298 x (V S S- v DD ) 

Roao Output Impedance 

V ABURST A B URST = 0.238 x 

(V S S- Vdd) 

RoAguRRT O ut P ut Impedance 

v A 3 A3 = 0.134 x (v S s- v D d) 

R°A3 Output Impedance 

Chroma B Output Levels 

(Figure 4} 



v B i bi =0.465 x (v S s -vdd) 

Rob1 Output Impedance 

v B o bo = 0.298 x (v S s -vdd) 

Robo Output Impedance 

v B3 83 = 0.134 x (v S s -vdd) 

Rob3 Output Impedance 

Chroma A Bias and Chroma B 
Bias Output Levels 



VBIASA. VBIASB = 0298 (V S S - V D D) 
RoBIASA. RoBIASB 

Chroma and Chroma Bias Output 

Offset Voltages 

vos 



CONDITIONS 



14.25 < V S S- Vqg< 15.75 
8.5 < V S S- Vdd < 9-5 

vdd = v S s -9 5V 

VGG = Vss -15.75V 



C|_ = 50pF, l D C = 0, 

8.5 < vss- vdd < 95, 

(Typical values are for 

VSS - V DD = 9V). All voltages 

specified with respect to Vdd 



C L = 50pF, l D C = 0, 
8.5 < Vss - V DD < 9-5. (Typical 
values are for Vss — Vdd = 9V). 
All voltages specified with respect 

to Vdd 



MIN 



C L = 50pF, l D C = 0, 
8-5 < Vss - V DD < 9-5. (Typical 
values are for Vss ~ Vdd ^ 9V). 
All voltages specified with respect 

to Vdd 



C|_ = 50pF, !l D C'<50uA, 
IICHROMA- lBIAS'< 5 MA, 
IICHROMAA - ICHROMAB 1 ^ 5^A 



8.5 
14.25 



VSS-O.5 
VGG 



3.95 
900 
2.53 
790 
1.82 

710.0 

1,13 

520.0 



TYP 



3.95 
900 
2.53 
790 
1.13 
520 



2.53 
790 



9 
15 



35 

15 



4.18 
2.68 
1.93 

1.2 



4.18 
2.68 
1.2 



2.68 



10 



MAX 



9.5 
15.75 



VSS 
VGG+0-5 



4.42 
2060 
2.83 
2060 
2.04 

2030 
1.27 
2100 



4.42 
2060 
2.83 
2060 
1.27 
2100 



2.83 
2060 



50 



4-40 



dc electrical characteristics (con't) o°c<ta<75°c 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 




Video Output Levels (Figure 5} 


C L = 50pF, l D C = 0, 
8.5 = Vjs - Vqd < 9-5. All voltages 
specified with respect to VDD'Typical 
values are for VSS — VdD = 9V) 










VSYNC 


VgYNC = 0.444 x 
(VSS- V DD> 




3.77 


4 


4.22 


V 


R°SYNC 


Output Resistance 




906 




2080 


n 


VBLANK 


VBLANK = 0.333 x 
(VsS- Vdd) = 0.75x 
VSYNC 




2.83 


3 


3.18 


V 


R°BLANK 


Output Resistance 




835 




2080 


a 


VDARK 


VDARK = 0.242 x 

(Vss- vdd) = 0.545 x 

VSYNC 




2.06 


2.18 


2.30 


V 


R °DARK 


Output Resistance 




726 




2030 


a 


VLIGHT 


V L IGHT = 0.148 x 
(VSS- V D D) =0.383 x 
VSYNC 




1.26 


1.33 


1.41 


V 


R°LIGHT 


Output Resistance 
Audio Output Level (Figure 6) 


RLOAD = 100k, C LO AD = 20P F 


556 




2040 


a 


VOUT 


Output Resistance to Vdd 






vdd 




V 


Ro"ON" 


"ON" Resistance 


v ol < v dd +0-5 




1.0 


5 


kn 


Ro-OFF" 


"OFF" Resistance 


VOH>V D D + 3.0 


50 


500 




kn 


COUT 


Reset, Test and Game Select 
Input Levels 






5 




pF 


V|H 


Logical High Level 




V SS -1.5 




vss 


V 


V|L 


Logical Low Level 

Paddle 1 and Paddle 2 
Input Levels (Figure 7) 


8.5<V S S-V D D<9.5 


vdd 




VDD+25 


V 


V P | 


Input Trip Level 




Vdd-0.4 


vdd 


VDD+04 


V 


VOH 


Logical High Output Reset 
Level 

Power "ON" Clear Input 
Levels (Figure 8) See Note 6 


R LOAD = 15 kfi to Vqg. 
CLOAD = 0.1,uF, 10% 


Vss-2.5 




vss 


V 


V CLR 


Input Trip Level 


RLOAD = 180k, 10%, 

Cload = imF, 10% 


v D d -o.5 


vdd 


VDD+0.5 


V 


VOH 


Logical High Output 
Reset Level 




Vss-2.5 




VSS 


V 


«n 


Noise Levels on Chroma A, 
Chroma B, and Video Outputs 


8.5<V SS - V DD <9.5, 
14.25 < Vss- Vqg< 15.75. 
c LOAD = 50 pF, IH<50uA 


200 




200 


mV 



Note 1 : Chroma A, Chroma B and the Chroma bias output levejs are specified for dc current = 0. Typical dc loading conditions are 30mA or less. 

The resistor network in Figure 9(a) can be used to determine the shift and interaction in outputs for dc load conditions. 

Note 2: Video output levels are specified for dc current = 0. Any other loading conditions will influence the output levels and the resistor network 

in Figure 9(b) can be used to calculate output levels. Typical dc currents are 30li A or less. 

Note 3: All diffused resistors have a +30% tolerance, and tracking of tolerance can be assumed. 

Note 4: All MOS switch impedances include all variations, i.e., due to process, and supply variations, tracking of MOS switch impedances can 

be assumed. 

Note 5: Tracking of diffused resistor tolerances and MOS device tolerances cannot be assumed. 

Note 6: Power On Clear input pin is reset by the MM57100to the Vqh leve ' near tne en< ^ °f tne internal Power On Clear cycle, as shown in Figure 8. 

4-41 



2 



aC electrical Characteristics (0°C to +70°C, except where otherwise noted) 


PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 




Osc Inputs, 01 and 02 Input 






1.0227 




MHz 




Frequency (Figure 3) 














Rise and Fall Times 












tr. tf 










40 


ns 


'dl_1 










10 


ns 


t0 








0.9778 




lis 


tpwl 






0.405 






PS 


'pw2 






0.380 






MS 


V0L1 






Vss-1-0 


Vss-0.5 


VSS 


V 


V 0L2 


Chroma A and Chroma B Output 
Timing (Figure 4} 


Cl = 50 pF, IdC<50/uA 


Vss-2.0 


Vss-1.0 


VSS 


V 


f rA 








175 


225 


ns 


tfA 








175 


225 


ns 


VB 








175 


225 


ns 


tfB 








175 


225 


ns 


'SCB 








450 




ns 


trCB 








175 




ns 


tfCB 








175 




ns 


'CL1 













ns 


'CL2 













ns 


'BURST 


Video Output Timing (Figure 5} 


C|_OAD = 50pF, !I DC I<50/jA 




2900 




ns 


trv 








250 


500 


ns 


tfv 








250 


500 


ns 


trS 








250 


500 


ns 


tfS 








250 


500 


ns 


trL 








150 


225 


ns 


tfL 








150 


225 


ns 


tbp 








5 




US 


'SYNC 








4.5 


4.9 


/lis 


<fp 








1 


1.25 


MS 


'VIDEO 








0.97 




MS 


'BLANK 


Audio Output Timing 

(Figure 6) 


01, 02 inputs = 1.0227 MHz, 
CLOAD = 20 pF 


10.5 


11 


11.9 


MS 


fa 


Output Frequency 
Audio Tone Duration 


IDC^SO/jA 




491 




Hz 


'ON 






18.55 




30.25 


ms 


'OFF 








15 




Ms 


'ra.tfa 




C|_OAD = 20pF, 
REXT= 120k to V SS 




10 




MS 


'ha 








1 




ms 


Ipwa 


Player Paddle Timing 

(Figure 7) 


Cload = o^f + 10%, 

RLOAD>15kn (toVQG) 




2.037 




ms 


tPH 


Paddle High (25H) 




1.58 






ms 


tPL 


Paddle Low (215H) 








13.7 


ms 


<RP 


Power "ON" Clear Timing 

(Figure 8) 


RC> 138ms, R = 180k, 10%; 
C= 1/jF, 10% 






1.2 


ms 


'del 






60 






ms 


tPOWER 










30 


ms 



4-42 



V|H" 



-t0 _| f = 1.022727 MHz ±28 Hz 

J T~ 60% | ^ 50% | 



f,,!- 1.022727 MHz ±2! Hz -"-|t pvv il— 






50% - f- -| - 50% 50% \ f 

— ' >pw2 r— 



VOL1 




2 

Ol 

o 

o 



FIGURE 3. Input Clock Waveforms 



HOCKEY BORDERS VIDEO 



V SYNC~ 
V BLANK- 
U BLACK 



V WHITE ' 



V 



7 



7 \. 



CHROMA A A0- 

A BORST- 

A3- 



CHROMAB B0- 



VDD 



~\ 



\ 



'SCB— • | 
'ICB — 



M% - - J- 10% 



'BOBST — 
CHROMA A 





tJ \J~ 




FIGURE 4. Video-Chroma Timing 



4-43 



BOTTOM OF 

PICTURE 



V SYNC 

Vblai 

V BLACI 
V WHITE 



LINE! 
THROUGH LINE 3 



E-ir ^jit -1 ^ 



-LINES4THR0UGHLINE6 — —[-" THROUGH LIKE 20 ~ 



_j- — H — ■— — H -I 4.5^s — | 

Jl— , 



- H *J U- 4.5^s 



- LINE 21 - 
H 



u — u ui ru. 



ijir'inr irLr-Lrir 



H =* 63.557ms 

Note: Interlaced scan and 

equalization pulses are not used. 



FIGURE 5(a). Video Output Waveform 



v syNC 



V BLACK - 

V W HITE 



r— t bp — *j 



+ 90% 10% \ 
10% 90% 4. 



-— • r*- 'VIDEO 



JU 




tfv-nU- — |W-h 



-ifp tfv-— ■ 1 1— - ■ 

ANK H HK t fL 



FIGURE 5(b). Composite Video Timing and Levels 



BOTTOM OF PICTURE 
(FRAME n| 



BOTTOM OF PICTURE 
(FRAMEn + 1) 



j"i t\ , \ n rt_, rt L 



-^nrTjirijmnjiriJuiJLjinJiJULajir^ 



FIGURE 6. Audio Output Timing 



4-44 



LINE 1 

LINE 26? THROUGH LINE 20 



PLAYER PAQQlE 
VIDEO 



J\ t 



A^jUU ti 



PLAYER 

PADDLE 

INPUT 



7 

J m 



t PLAYER 

■ > PAODLE 

T INPUT 

—^ — 0.22kF 

TIMING CIRCUIT 



80TTOMOF_^ START OF LINE 21 

PICTURE [TOPOF PICTURE) 



v S s- 

VOH- 




'LAYER PADDLE INPUT TIMING 



FIGURE 7. Player Paddle Inputs 



vqo.Vgg 





(a) Fast Power Supply Edges (b) Slow Power Supply Edges 

FIGURE 8. Power "ON" Clear Input Timing 



CHROMA 6 , 
OUTPUT 



<0.7 

O ' I— i 1, i_l Lh_o 



HO;) -840- BIAS OUTPUT 



T | 125:. -61i 



140<> -840! 
A BURST 



> 0.37k A BURS 

ltt „ ru 



,_tl_ 




»DD 

(a) 



(b) 



FIGURE 9. Chroma and Video Output Networks (See Notes on Page 4-41 ) 



4-45 



TABLE i. Game Coiors and Size on a 25" TV 




ELEMENT 


CHROMA 
OUTPUT 


VIDEO 
OUTPUT 


APPR. 
COLOR 


APPR. SIZE 


COMMENTS 




Tennis Background 


A1B0 


Light 


Blue 








Tennis Field 


A0B3 


Dark 


Cyan 


13.2 x 16.8 inches 2 








Tennis Ball 


A0B3 


Light 


Cyan 


0.5 x 0.5 inches 2 








Tennis Score 


A3 BO 


Light 


Yellow 


4x5 inches 


Blanked during play 






Tennis Net 


A3B0 


Light 


Yellow 


0.5 x 13.2 inches 2 








Tennis Left Player 


A3B1 


Light 


Orange 


3 sizes 


2.4, 1.2 or 0.6 inches x 0.5 inches 
independent of other paddle 






Tennis Right Player 


A3B1 


Light 


Orange 


3 sizes 


2.4, 1.2 or 0.6 inches x 0.5 inches 
independent of other paddle 






Handball Background 


A3B0 


Light 


Yellow 










Handball Field 


A3B0 


Dark 


Yellow 


13.2 x 16.8 inches 2 








Handball Ball 


A3B0 


Light 


Yellow 


0.5 x 0.5 inches 2 








Handball Left Score 


A3B1 


Light 


Orange 


4x5 inches 


Blanked during play 






Handball Right Score 


A1B0 


Light 


Blue 


4x5 inches 


Blanked during play 






Handball Left Player 


A3B1 


Light 


Orange 


3 sizes 


2.4, 1.2 or 0.6 x 0.5 inches, 
same as other paddle 






Handball Right Player 


A1B0 


Light 


Blue 


3 sizes 


2.4, 1.2 or 0.6 x 0.5 inches, 
same as other paddle 






Hockey Background 


A1B0 


Dark 


Blue 










Hockey Field 


A1B0 


Dark 


Blue 


13.2 x 16.8 inches 2 








Hockey Border 


A3B0 


Light 


Yellow 










Hockey Puck 


A1B0 


Light 


Blue 


0.5 x 0.5 inches 2 








Hockey Score 


A3B0 


Light 


Yellow 


4x5 inches^ 


Blanked during play 






Hockey Left Player 


A3B0 


Light 


Yellow 


3 sizes 


2.4, 1.2 or 0.6 x 0.5 inches 
independent of other paddle 






Hockey Right Player 


A3B0 


Light 


Yellow 


3 sizes 


2.4, 1.2 or 0.6 x 0.5 inches 
independent of other paddle 






Hockey Machine Forwards 


A3B0 


Light 


Yellow 


0.5 x 0.6 inches 








Hockey Goals 


A1B0 


Light 


Blue 


4.6 x 0.5 inches 2 


Hole in the Border 




A3B1 
-ORANGE * i 


B 

AOBt A,B1 
' -RED 7* ~ MAGEN 


TA 




TABLE II. Chroma Outputs vs Approximate Color 




CHROMA A AND 
CHROMA B OUTPUTS 


APPROXIMATE COLOR 




AO, BO 




Light Gray 










AO, B1 




Red 












AO, B3 




Cyan 




-f 




/ 






A1, BO 
A1.B1 
A1, B3 




Blue 
Magenta 
Blue Cyan 






A3B0 / 
-YELLOW / 


\ A1B0 
\ -BLUE 


/ 




A- Bill 
B-Red 
Y = Vid 


- Y 

- Y 



A3, BO 
A3, 81 
A3.B3 




Yellow 
Orange 
Green 




A3B3 *C ' 
-GREEN 


. A0B3 \_ 
-CYAN »A1B3 

-BLUE/C 

B 






aburst.bo 




Color Burst 




YAN 








FIGURE 10. Chroma Outputs/Color Phase D 


agram 









4-46 



DESIGN CONSIDERATION FOR THE PLAYER 
PADDLE INPUTS 

Calculations are based on an input waveform at the 
"PLAYER PADDLE" input: 



V|N = V|H + (1-e' 



-t/RC 



MVGG-V|H> 



A solution for t = RC is done, at the input trip point 
where V|N = Vjrip = Vqd ±0.4V, and t = tj. 



RC = 



-td 



VGG - V D D ±0.4V 



VGG- V|H 



Over the design range of Vqd. Vgg and V|h, the 
denominator has a range 



-1.187 <ln(x)< -0.5864 where x 



vgg-vdd ±Q4 v 

VGG - Vih 



The time delays required vary from a minimum of 
tjjj = 1.58 ms for the player paddle positioned at the 
top of the screen, to a delay of tdB = 13.7 ms for the 
player paddle positioned at the bottom of the screen. 
For these time delays, the ranges of RC are: 



(RCI TMIN ='-33n 



VGG- Vdd*0.4V 
VGG-V|H 



.<(RCIt max = 2.69 ms 



for the upper paddle position and 

<RC)B M | N = 11.54 ms; (RC)b max = 23.36 ms 

for the lower paddle position. 

Thus, the external RC network must guarantee a mini- 
mum RC of 1.33 ms or less and a maximum RC of 
23.36 ms or greater. 

Calculations of potentiometer resistance based on a 
linear pot use the formula: 



Re- 



»xR f 
9fs 



±R n 



where: R$ is the potentiometer tap resistance 
6 is the angle of pot rotation beyond 
8f s is the full scale rotation of the pot, ± 
tolerance 

Rp is the full scale resistance of the pot, ± 
tolerance 
L is the linearity of the pot 

Using RC = tj, values of 8 can be calculated for the 
required extremes using the expression: 



(^ ±Rp . L )e fs 



This expression assumes prior selection of Rp, L, 9f s , 
and C This expression can be modified to calculate 
Rp or C if there is any restriction on the upper limit 
of fl. 

Mechanical variations, either in the potentiometer or 
the control housing which affect pot rotation should 
also be considered. 



TIMING AND LEVEL DEFINITIONS 

t r ,tf Rise and fall times of01 and 02 clock inputs. 

t(jL1 Delay from the Vgs - 1V point of the 02 

positive transition to the Vss — IV point 

of the 01 negative transition. 
t0 Clock cycle time. 

tPWI Time from 50% point on negative edge of 02 

to the 50% point on the negative edge of 01 . 
tpw2 p u!se width of the 02 input, at the 50% 

point. 
VOL1 Crossover point where 01 = 02 and 01 is on 

a negative transition. 
VOL2 Crossover point where 01 = 02 and 01 is on 

a positive transition. 
trA''rB' Ri se and fall times of the chroma A and 
tfA< tfB chroma B outputs. 
tSCB Delay from start of sync pulse trailing edge 

to the start of the chroma A output color 

burst leading edge. 

'rCB. 'fCB R i se and fall times of the chroma A output 

color burst pulse. 
l BURST Chroma A output color burst pulse width. 
t_CL1 Delay from the start of a chroma output 

negative transition to the start of the VIDEO 

output (luminance) transition. 
t CL2 Delay from the start of a chroma output 

positive transition to the start of the VIDEO 

output (luminance) transition. 
t rv ,tf v Rise and fall times of the VIDEO output 

blanking pulse. 

VS' tfS Rise anal fall times of the VIDEO output 

SYNC pulse. 
frL' tf L Rise and fall times of the VIDEO output 

luminance pulses, 
tfp' *bp Duration of the VIDEO output front porch 

and back porch. 
l SYNC Duration of the VIDEO output SYNC pulse. 

tVIDEO Duration of the VIDEO output luminance 

pulses. 
*BLANK Duration of the VIDEO output blanking 

pulse. 
tON Duration of the AUDIO output "HIT" 

tone burst. 
toFF Delay from the end of the AUDIO output 

"HIT" tone burst to the start of the VIDEO 

output blanking pulse, 
'ra^ Ma R' se and fall times of the AUDIO output. 

t na Width of the AUDIO output tone pulse 

positive level. 
t pwa AUDIO output tone cycle time 

(t= 1/fAUDIO* 
tRp Rise time of the PLAYER PADDLE input. 

tpH Delay time from the top of the picture to 

the highest player paddle position. 
tpL Delay time from the top of the picture to 

the lowest player paddle position. 
tcj c | Delay from point where the power supplies 

are within the operating spec to the point 

where the power-on clear input level is less 

than VcLRI- 
'POWER Fall time of the power supply at turn-on, 

to 95% point. 
H One horizontal scan line. 



4-47 



0) 

00 
00 




TV Circuits 

Note. SK1115 kit includes: MM57100N, 
MM53104N and LM1889N 



LM1889 TV video modulator 
general description 

The LM1889 is designed to interface audio, color 
difference, and luminance signals to the antenna termi- 
nals of a TV receiver. It consists of a sound subcarrier 
oscillator, chroma subcarrier oscillator, quadrature 
chroma modulators, and R.F. oscillators and modulators 
for two low-VHF channels. 



The LM1889 allows video information from VTR's, 
games, test equipment, or similar sources to be displayed 
on black and white or color TV receivers. When used 
with the MM57100 and MM53104, a complete TV game 
is formed. 



features 

■ DC channel switching 

■ 12V to 18V supply operation 

■ Excellent oscillator stability 

■ Low intermodulation products 

■ 5 Vp-p chroma reference signal 

■ May be used to encode composite video 



block diagram 



Dual-1n-Line Package 



CHROM/ 
LEA 


* ' 














' 8 CHROMA 


) 




' 










LAG 




' 




♦ 


CHROMA 
OSC 






R- 
INPU 


t 2 


X 




" CHROMA OSC 


r 










OUTPUT 
















CHROMA 3 


■ 










' 6 CHROMA 


BIAS 


' 










SUPPLY 




X 












B 
INPU 


v « 






SOUND 
OSC 




,5 SOUND 


T 






TANK 










6 
GROUND 

, 6 














» RF 












SUPPLY 
13 VIDEO 




7 


CHB 
OSC 










OCREF 






' 


' 1 






TANK 




r 




X 




12 VIDEO 




'■ 




s 








INPUT 






_y\ 














r 8 




UJ 


r^ 




' 1 








11 RH A 


CH A 
TANK 


9 




CHA 
OSC 


L 


X 






OUTPUT 
,0 CH B 


1 


















OUTPUT 



Order Number LM1889N 
See Package 20 



4-48 



tentative electrical characteristics (Applications circuit, v = i5v> 



Supply Voltage Range V14, V16 
Total Supply Current I -j 4 + l-|g 
Common-Mode Input Range 

Chroma Mod. V2, V3, V4 

RF Mod. V12, V13 
Oscillator Levels 

Sound Osc V15 

Chroma Osc V17 

RF Osc V6, V7 or V8, V9 
Chroma Modulator Conversion Gain 

V13 0ut/V4-V3 

V13 0ut/V2 - V3 
Residual Chroma Output, V13 

V2 = V3 = V4 
RF Modulator Conversion Gain 

V10or V11/V12-V13 



TYP 


12-18V DC 


35mAoC 


4-10.5 V DC 


3.5-11 V DC 


3.5 Vp-p 


5 Vp-p 


300 mVp-p 


0.6 Vp-p/V DC 


0.6 Vp-p/V DC 


50 mVp-p 


10 mVrms/Voc 



00 
00 



typical application 



X^L)K 



T 



:> 



240 C H4 6 



f T 



2 1 2T >■ i n,r 



X 



K 



240 CH 3 8 



2 1/2T V I 75 pF 



r 

X 



Hf- 



3 57955 MHj 9-35 pF 






~1T' 



S1 T_ 



I Vl20pF 



"3T 



i». HH 



-O LUMA • SYNC 



1-49 



o 
in 

2 



a 



MM53104 TV game clock generator 



TV Circuits 

Note. SK1115 NTSC kit includes: MM57100N 
MM53104N and LM 1889N. 
Note. SK1120 PAL kit includes MM57105N, 
MMS3114N andLM1889N. 



general description 

The MM53104 is a monolithic CMOS clock generator 
designed to generate the 2-phase non-overlapping clocks, 
01 and 02' f° r tne MM57100 TV game chip. 

The MM53104 contains two independent oscillator 
circuits that can either be driven by an external input 
or be used as a Colpitts-type oscillator (e.g., crystal 
oscillator). The first oscillator (XI, X2) is designed to 
operate at 3.58 MHz and the output (X2) is fed internally 
to a divide-by-3 1 /2 counter to generate the 1 .0227 MHz 
01 and 02 outputs required by the MM57100. The 
second oscillator (Y1, Y2) is a completely independent 
oscillator and is designed for a 4.5 MHz operation. 



All pins are protected against static damages by diode 
clamps to both VrjC ap d ground. 



features 

■ Directly drives MM57100 

■ Two on-chip oscillator circuits 

■ Low power consumption 250 mW typ @ 1 5V 



connection diagram 

Dual-ln-Line Package 

~xj — 



-«cc 



timing diagram 

- nj~Lrun_ji_n_rLJi_r 
» jn_riJiJiJi_JTJi_rL 
* j — i i — i 



i J 



i 



NTSC Order Number MMS3104N 
PAL Order Number MM53114N 



logic diagrams 



«cc 



_L. tM 

i o— vw^-4-^ ">o— i h- 

Vi-r -A- 



i" 



X2 0— VW- 



3 1/2 

COUNTER 



NON 

OVERLAPPING 

CIRCUITRY 



«CC 

i 




i 



V2C— WV- 



4-50 



absolute maximum ratings (NoteD 



Voltage at Any Pin 

VCC 

Recommended Vcc 

Operating Temperature Range 

Storage Temperature Range 

Package Dissipation 

Lead Temperature (Soldering, 10 seconds) 



-0.3V to VCC+03V 

-0.3V to 16V 

15V ±5% 

Cto+70°C 

-65°Cto+150°C 

500 mW 

300° C 



dc electrical characteristics 14 ,25v< vcc< 15.75V 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


ice 


Quiescent Current 


X1 = Y1 = V C C 






600 


MA 




Operating Current 


Y1 = GND 




15 




mA 


VOH 


Output High Level, 01 or 02 


V C C=15V 


14.95 






V 


vol 


Output Low Level, 0i or 02 


VCC= 15V 






0.05 


V 


lOH 


Output Source Current, 01 or 02 


VCC = 15V, Vo= 13.5V 


-7.0 






mA 


lOL 


Output Sink Current, 01 or 02 


Vcc = 15V, V = 1.5V 


11.0 






mA 



ac electrical Characteristics Vcc = 15V, C L = 15 pF, all limits apply across temperature. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


TR 


Rise Time of 01 or 02 






15 


30 


ns 


tf 


Fall Time of 01 or 02 






15 


30 


ns 


1"PW,0i + 


Positive Pulse Width of 0i 




410 


455 


510 


ns 


Tp\W,0!- 


Negative Pulse Width of <j>-[ 




470 


520 


570 


ns 


T PW,02+ 


Positive Pulse Width of 02 




510 


570 


600 


ns 


TPW,02- 


Negative Pulse Width of 02 




380 


410 


470 


ns 


T W,02- 


Effective Negative Pulse Width 
of 02 




405 


440 




ns 


TdL1 


01 Overlapping 02 Time 






-13 


5 


ns 


TdL2 


02 Overlapping 0i Time 






-2 


10 


ns 


VOL1 


01 Cross-Over 02 Voltage 




vcc-10 


vec 




V 


VQL2 


02 Cross-Over 0i Voltage 




VcC-2.0 


VcC-08 




V 



Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating 
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" 
provides conditions for actual device operation. 

ac test circuit 




INPUT FROM PULSE 
GENERATOR 

T1 = 145 ns 

T2 = 135 ns 

t r = tf = 20 ns 

C(_ = 1 5 pF including scope probe and all stray capacitances. 

Note: When the MM53104 is used with the MM5710O 

and LM1889, the 4.5 MHz oscillator in the MM53104 

is not needed and thus pin 3 should be grounded. 



'" 1 

HP 

O.OI^F 



OPEN 



X7 



NTSC MM531D4N 
P«L MM531KN 



—►TO SCOPE 



-► TO SCOPE 
CL 



4-51 



o 

CO 

If) 



switching time waveforms 

135*2ns 



PULSE 50% - 
GENERATOB 

0- 



iO%-,L J r 50% -i -50% \ / \ 

_y v / a- ">» -/ \ 




*2 GND 



" T PW,#1- 
-TPW.42+ 




Note: t r = tf = 20 ns 



~ T PV»,«2- 
- T W,02-" 
- T PW,«1+ 




4-52 



a 



TV Circuits 



s 

w 
oo 

o 



MM58106 digital clock and TV display circuit 



general description 



features 



The MM58106 is a monolithic CMOS integrated circuit 
which generates a display of channel number and time 
on the television screen. The circuit can either display 
channel number (2-83) or program number (1-16). 
Time display can be 4 or 6-digit, in either 12 or 24-hour 
mode. Timekeeping is controlled from a 50 Hz or 
60 Hz input. The position of the display on the TV 
screen is controlled by adjusting the external RC time 
constants. 



Single chip clock and display 

12 or 24-hour operation 

5 or 8-digit time display 

Channel or program number display 

50/60 Hz operation 

Channel and time display on channel change 



The circuit 
package. 



is packaged in a 28-lead dual-in-line epoxy 



block diagram 



connection diagram 



R H 1 HORIZONTAL 

ONE-SHOT 



H DIGIT 
NUMBER 
C0ONTER 



OtGIT 
MULTIPLEX 
DECODER 



V LINE 
NUMBER 
DECODER 



.i^- 



CHANNEL 
NUMBER 
BUFFERS 



HR HOLD Mid 

, 1 + I 



S 



TIME 
KEEPING 
COUNTERS 



Dual-ln-Line Package 



OSCILLATOR 
INHIBIT 
I QEC0DER 



TIME 

SLOT 

OECOBER 



60 60 Hz 
SELECT 



CHANNEL 

- PROGRAM 

SELECT 



CH'PROG SEL- 



VIOE0 0UT - 

vss- 



- VERT 

- DIGIT SEL 

- OSC INHIBIT 

- 4 MHz CLOCK 



■ 50/60 Hz INPUT 

- 50/60 SELECT 

■ SETHR 
. SETMIN 
-1W4HR 
-HOLD 

- EDGE DETECT 



Order Number MM58106N 
See Package 23 



4-53 



absolute maximum ratings 














Supply Voltage (Vdd - V SS) 


5.5V 












Voltage at Any Pin 


Vss - 03V t0 +5-5V 












Operating Temperature 


0°Cto+70°C 












Storage Temperature 


-55° C to+150°C 












Lead Temperature (Soldering, 10 seconds) 


300°C 












electrical Characteristics VqD = 5V, Vss = 0V. unless otherwise specified 








- 


PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Power Supply Voltage, Vqd 


v S s=o 


4.75 


5 


5.25 


V 


Power Supply Current 








800 


uA 




Input Voltage Levels 














Channel Inputs 














Logical Low 




Vss-0-3 


VDD-5 


Vqd-4.5 


V 




Logical High 




Vdd-0-3 


VDD 


VqD+0.3 


V 




Horizontal and Vertical Inputs 














Logical Low 




Vss-0.3 


VdD-5 


VDD-4.5 


V 




Logical High 




Vdd-0-3 


VDD 


VDD+03 


V 




Set Mms. Set Hours. Hold. 12/24-Hour 


Internal Pull-Up Resistor to 












Select, 50/60 Hz Select, Channel/ 


V DD I600k Mini 












Program Select 














Logical Low 




Vss-0-3 


vss 


VsS+0.3 


V 




Logical High 






Open 








All Others 














Logical Low 




V S S "0.3 


vss 


VSS+O.3 


V 




Logical High 




VdD-03 


VDD 


Vod+0.3 


V 




Input Frequency 














4 MHz Clock 




1 


4 


4.5 


MHz 




Horizontal 


Pulse Width = 14 us 




15.75 




kHz 




Vertical 


Pulse Width = 1 ms 




60 




Hz 




Output Voltage Levels 














Oscillator Inhibit and Video Output 














Logical Low 




Vss-03 


vss 


VSS+0.9 


V 




Logical High 




VdD-05 


VDD 


VDD+03 


V 




One Shot Output Pulse Duration 














Horizontal 






50 




MS 




Vertical 






13 




ms 




Output Drive 














Video Output 














Logical Low 


V SS +1V 


(-1) 






mA 




Logical High 


V DD -1V 


1 






mA 




Oscillator Inhibit Output 














Logical Low 


Output Forced Up to VpQ-4.5V 


(-2) 






mA 




Logical High 


VDD-1V 


0.2 






mA 




External RC 














CVERTICAL 






0.1 




u-f 




CHORIZONTAL 






0.001 




MF 




^VERTICAL 






100 




ki'l pot 




R HORIZONTAL 






100 




k£2 pot 




Propagation Delay Oscillator Inhibit 


From Input Clock to Oscillator 






2 


clock pulses 




Output 


Inhibit Output 












Input Leakage 








1 


M A 




Input Capacitance 








5 


pF 




Edge Detect Pulse Duration 


C= 2/uF, R = 1 Mil 




2 




sec 





4. 54 



functional description 



A block diagram of the MM58106 TV timer is shown in 
Figure 1, A connection diagram is shown in Figure 2. 
Unless otherwise indicated, the following discussions are 
based on Figure 1. 

50 or 60 Hz Input: This input has a shaping circuit 
which allows using a filtered sinewave input. A simple 
RC filter such as shown in Figure 4 should be used to 
remove possible line voltage transients that could either 
cause the clock to gain time or damage the device. 
The input should swing between Vcjg and Vfjo. The 
shaper output drives a counter chain which performs 
the timekeeping function. 

Alternatively, in a crystal controlled battery operated 
system, an oscillator and prescaler circuit such as the 
MM5369 could be used as a timebase. 

50 or 60 Hz Select Input: This input programs the 

prescale counter to divide by either 50 or 60 to obtain 
a 1 pps timebase. The counter is programmed for 60 Hz 
operation by connecting this input to V^g. An internal 
1 N\£l pull-up resistor is common to this pin; simply 
leaving this input unconnected programs the clock for 
50 Hz operation. 

Time Setting Inputs: Inputs to set hours and set minutes 
as wed as a hold input, are provided. Internal 1 MU 
pull-up resistors provide the normal timekeeping func- 
tion. Switching any one of these inputs (one at a time) 
to "0" results in the desired time setting function. 
Set Hours advances hours information at 1 hour per 
second, and Set Minutes advances minutes information 
at one minute per second, without roll over into the 
hours counter. The hold input stops the clock to the 
minutes counter and resets the seconds counter. 



Display Control: The channel number and time display 
circuits operate from the 4 MHz input clock frequency. 
The horizontal and vertical position of the display is 
controlled by adjusting the external RC time constants 
<R|H, C|-|, By.Cy). 



These monostables are triggered by the horizontal and 
vertical retrace signals as shown in the timing diagram in 
Figure 3. 



A 7-segment decoder is used to decode either channel 
inputs or time. Also a time slot decoder is employed to 
decode the appropriate time slot and the digit to be 
displayed. It generates a video output signal that can 
modulate the sweep of the television tube for the on- 
screen display. 

Channel/Program Number Select: This control pin has 
a pull-up resistor to VqD ar, d, w ' tn tne ' nput open, 
the chip will accept a binary plus 1 code on the CU1 to 
CU8 inputs and display the program number. For 
example, an input code of 0000 will indicate channel 1 
and 1111 will indicate channel 16. 



With thss input at "0", inputs CU1 to CU8 and CT1 to 
CT8 will accept BCD inputs for channel units and 
channel tens respectively, and display channels 2—83. 



Edge Detect: On program change, the time and number 
will be displayed for a period depending on the external 
capacitor and resistor connected to the Edge Detect pin 
(Figure 4). 



VERTICAL 
RETRACE 



h- 



HORIZONTAL " 
RETRACE 



HORIZONTAL" 
TIMEOUT 



"i r 



OSCILLATOR 
INHIBIT. 



CLOCK 

4 MHz- 



J 



1 



j-- 1 6 jis — H 

nn n n n 



VIDEO OUTPUT 
CHARACTER 
DISPLAYEO * 



JUUL 



FIGURE 3. Timing Diagram 



4-55 



CO 

o 

00 

in 

2 



typical applications 



-rlh 



50/60 Hi 5 Vims— ^- 



i 

100k | 

S/SAr-A *— 



\ » 

r 



r 3- 



5V-24 Hfl, GND-12 HR — — i 
OSC INHIBIT 




X 




PROGRAM/CHANNEL SELECT 

5V-PRQGRAMS (EUROPEAN) 

GND-CHANNELS 



J 



L 



TO TV 

VIDEO DUTPUT 
CIRCUIT 




FROM TV 
+SA, — HORIZONTAL 
RETRACE 



FROM TV 

■A^At— VERTICAL 

RETRACE 



-w- 



-H- 



DIGIT SELECT 
5V-8 DIGITS 

GNO -5 DIGITS 



J 



INPUT I 1 OUTPUT 

IGURATION I CONFIGUf 

R CHANNEL — < ( •— FOR OSC II 

INPUTS AND T VIDEO OU 

ROL INPUTS j_| DIGIT SEL 

H! 



GURATION 

NHIBIT 

OUTPUT, 



"1 



J J I 



H 1 Hi 



H 



ih 



Hi iH 

1 T 



'H 



IETRACE I ["" 

INPUT [_| 



FIGURE 5. Horizontal and Vertical One-Shot Circuit 



4-56 




en 
oo 

03 



MM 5878N REMOTE CONTROL POTENTIOMETER 



General Description 

The MM5878 Potentiometer is a monolithic MOS integrated 
circuit utilizing P channel low threshold, enhancement 
mode and ion implanted depletion mode devices. The cir- 
cuit is intended to function as a potentiometer in remote 
control systems, particulary in colour television. Each inte- 
grated circuit contains the logic to control three functions 
e.g. volume, brightness and saturation. All three functions 
are set at mid-level at switch on or by an external preset 
input. The output of each function is a fixed frequency, vari- 
able duty-cycle pulse train which is readily integrated with 
an RC network to produce a DC. voltage in the range of Vss 
to Vdd (0-1 2V). This DC. voltage is used to control the 
volume etc. in a colour TV receiver. Each function controlled 
has two inputs, one to increase the output level, the other to 
decrease it. An additional and completely seperate feature 
of the device is the fast mute latch which can be set and 
reset by a single input. The MM5878N provides the equip- 
ment designer greater freedom when planning control 
panels. 
The part is similar to the ERC 3064 and ERC 31 64. 



Features 

3 function capability 

cascadable 

all outputs variable within 62 steps 

fast mute sound facility 

high impedance inputs 

low power dissipation 

Applications 

Tv remote control potentiometer 

Hi Fi Radio 

Radio control models 

Digital to analogue conversion 

Servos 

Domestic cooker hot-plates 

Light dimmers 

Mixer, sound/light 





























! 






MEMORY B 








B 






I 
























C 



JOB O— \<~ 



DETECT AND CONTROL LOGC 



—I I— O OownB 



MASTER DIVIDER 



Fig.1 BLOCK DIAGRAM 
MM 5878 



4-57 



FUNCTIONAL DESCRIPTION 

A block diagram of the MM5878 Potentiometer is shown in 
Figure 1 . A connection diagram is shown in Figure 7. Unless 
otherwise indicated, the following discussions are based on 
Figure 7. 



Clock Timing Input : (13) 

This input requires a resistor to v dd and a capacitor to v ss 
The frequency of the clock determines the output fre- 
quency, the control rate and hence the time takento go from 
full-up (62: 1 duty cycle) to full-down (1 :62 duty cycle). 

For example, with the RC network such that the frequency 
of oscillation is 1 00 KHz, (R = 300K, C = 39pF), then 

Output frequency = 1 00/63 = 1 .59 KHz 

control rate (with 

internal 127 = 159 KHz/127 = 12.5 Hz 

counter) 

time full-up to full-down (i.e. 62 steps) = 62/1 2.5 = 4.95 
seconds. 

Hence the control rate can be varied by changing theclock 
resistor and capacitor. 

Function Inputs : (7. 8, 9, 10, 11, 12) 

These inputs are inactive when taken to V ss ( + 12V). If for 
example, the UP input of function 1 is taken to V dd (OV) then 
the output of function 1 will increase at the rate specified 
above. When the output level reaches the full-up state, 
internal logic holds the output at the maximum irrespective 
of the voltage applied to the UP input. 

The UP and DOWN inputs should not be activated simul- 
taneously. 



Function Outputs : (6, 5. 4) 

Each output consists of a push-pull stage as shown in Fi- 
gure 3. An external RC filter integrates the variable mark- 
space output leaving a DC. control voltage . If, for example, 
the volume level is to be controlled, this DC. control voltage 
is fed directly into the control pin of the sound IF. to vary that 
level. 

Typical output wave forms are shown in Figure 3. 

Fast Mute Facility : (15, 16) 

The output of the fast mute latch is at OV after switch-on or 
after application of the external preset input. To activate the 
mute latch, a short positive pulse is applied to the mute 
input. The output changes state to + 12V on the trailing 
edge, and it can be reset to OV by applying another positive 
pulse to the input. 

Vgg Supply: (2) 

This low current supply rail is required for the push-pull 
output stages. If a negative supply (-5V to -12V) is not 
available in the system, it can by generated simply by an 
external network of 2 diodes and 2 capacitors driven from 
any one of the function outputs. 

By connecting the number 2 pin on each I.e. together more 
than one MM5878N may have its v gg supply generated by 
only one network. However, the full range (62 : 1 / 1 : 62) of 
that particular function output may be limited if more than 
one I.C. is supplied. 

Figure 4 illustrates a typical application of the Potentiometer 
in a remote control colour TV receiver. 

The negative supply Vgg is required to give a full voltage 
swing on the outputs Alternatively a pull up resistor could 
be used. 



For testing purposes, it is possible to activate all three func- 
tions simultaneously in either the UP or DOWN mode. 

Preset Input: (14) 

This input sets all three functions to mid-range i.e. the duty 
cycle of each output is 31 :32. It has an internal pull-down 
resistor to V dd (OV) and is activated when taken to V ss 
( + 12V). 



4-58 




3 
3 

01 
00 

-J 

00 



DC 
Voltage With a Vgg supply the 
output impedances to 
q Vss and to Vdd are 

equal. 



V G G" ; (V D D-5V) 



Fig. 2 (A) 



v D d 




V GG " V DD 



With a pull up resistor, the output impedances to Vss and 
Vdd are unequal, giving an error in the DC. voltage genera- 
ted, due to unequal charge and discharge times. However, 
this error can be minimised by making Ra>>Rb. 



Fig. 2(B) 



Output 
mid way 



jut I 

/ay L. 



-31 -f- 32- 



r 



Full-up 



IT 



1 



II 



Fig. 3 Output Waveforms 



4-59 



ABSOLUTE MAXIMUM RATINGS 

Supply voltage 17V 

Voltage at any pin other than outputs Vss + 0.3V to Vss - 25V 

Voltage at output pins Vss + 0.3V to Vss - 1 8V 

Voltage at pin 2 (V) -5 to -12V 

Operating temperature O'C to 70C 

Storage temperature -65'C to + 1 50'C 

Lead temperature 300'C 
(soldering 10 seconds) 

ELECTRICAL CHARACTERISTICS 

measured at T A = 25°C, V ss = + 12V 



parameter 


conditions 


min. 


typ 


max 


units 


supply voltage (V ss ) 




9 




17 


volts 


supply current 

'dd 

l qq Into pin 2 






5 


10 
100 


mA 
yUA 


inactive input voltages 
up/down inputs 
mute, preset inputs 




+ 8.5 





-r12 
+ 3.5 


volts 
volts 


active input voltages 
up/down inputs 
mute, preset inputs 





+ 10.5 




+ 3.5 
+ 12 


volts 
volts 


input currents 

up/down, mute inputs 
preset input 


V |n = Ov 
V |n = +12v 






5 
25 


/uA 


output impedance 


v gg = - 10v 
'out = ±/1mA 






1 


k ohm 


clock frequency 




DC 




400 


kHz 



4-60 



Application: 1 MM 5878 N 

Remote Control Potentiometer 



Clock 

time constant 



Preset )- 
Mute m ± 



From 

Remote Control 

function 

decoder 

and front 

panel 



Down T 



DC Output 

C 

(soundcontrol) 




DC Output 

"A" 

(brightness control) 



Negative iVgg) 
supply generate 



Fig. 4 



4-61 



CO 

oo 
in 



Q 
O 
> 



00 
f- 
00 
LO 



c 
o 

(0 

o 

a. 
a 
< 



o 
<o 

c 

CO 
CO 



# «^i <f 



Q 
Q 




■#■ -HHi* ■*" 



CD (O 



CJ C\J -- OCT) Q 



If) 

CM ^ 
O 

< <" 
< 

CO a> 



8 

CO 



I 



z 

s 



c t i9 I' 



N k 



00 O o o 





1 — — 1 


•* - 


— 1 1 


eg 


1 "° 1 


o 


1 (13 X 1 




19-1 


< 

< 


1 -D It! ' 
ll 5 1 


CO -. 


H 1 




L J 



w 



U- u. 



a ■-. _ 

^ ^ c i 

8 8 o °p o> 

t- co v- (o n 

II II II II II 

cc cr cr 6 (3 



4-62 



Application: 3 

MM 5878 N 
HiFi Radio 



Up 



Treble 



{^ 



Balance 
Front-back 



Balance 
Left- Right 



Loudness 



~u -r 



~u «r 






_r "i_ 



| y r-i_ 

I 5 ki-r 



_r -t_ 



ov 



MM 5878 




OV. 



12V 



Fig. 6 



-^v^- 



R, 



R, 



IP. 



R. 



^^V- 



R, 









Balance 
Front-Back 



Balance 
Left-Right 



Loudness 



5 2 Ktt. 
300 Kfl 

39 pF 

27 nF 
100 nF 



Diode IN 4148 



4-63 



Connection Diagram 



Vss . 

Vgg- 

Vdd - 

Output C ■ 

Output B • 

Output A 

UpC 

Down C ■ 



092 DIA NOM 
PIN NO 1 IDENT 




E 
E 
E 

E 
E 
E 
E 



O 



iU 



Top View 
Fig. 7 



Mute In 
Mute Out 
Preset 
Clock 
Down A 
Up A 
Down B 
UpB 



090 

FSl FT) FH Fil R R [91 




LIUJLsJUJkJEIizJlsJ 



■0 870- 
MAX 



325 025 075 . 
™ oT5^ - o 01 5 



MMMM 



040_^ 
TYP 

Physical Dimensions. 
Fig. 8 



Plastic Dual in Line package 
Order no. MM 5878 N 



n 



a 



. 1 30 i 
3. 065 .005 T 



0018 

-0 003 - *" 



) '25 WIN 



rn= 



020 
MIN 



4-64 




SECTION 5 

ANALOG TO DIGITAL 
(A/D) CONVERTERS 



CO 
CO 



a 



Analog to Digital (A/D) Converters 




LF13300 integrating A/D analog building block 



general description 



The LF 13300 is the analog section of a precision 
integrating analog to digital (A/D) system. JFET and 
bipolar transistors (BI-FET) are combined on the same 
chip to provide a high input impedance unity gain 
buffer, comparator and integrator, along with 9 JFET 
analog switches. The LF 13300 has sufficient accuracy 
to construct up to a 4 1/2-digit Digital Panel Meter 
(DPM) or up to 14-bit (plus sign) Data Acquisition 
System and is specifically designed for use with either 
the MM5330 BCD digital building block or the MM5863 
12-bit binary building block. 



features 

■ Rugged JFETs allow blow-out free handling 

■ High input impedance > 1000 Mfi 

■ Automatic offset correction 

■ Analog circuitry can be physically and electrically 
isolated from high noise digital circuits 

■ Analog input range of ±1 IV with + 15V supplies 

■ Wide power supply voltage range ±5V to ±18V 

■ TTL and CMOS compatible logic 

■ Can interface directly with microprocessors 

■ Versatile: can be used as a 12-bit plus sign binary 
A/D, 4 1/2-digit, 3 3/4-digit and 3 1/2-digit Digital 
Panel Meter (DPM) 

■ Low cost 



block and connection diagrams 



OFFSET CORRECTION 



ANALOG UNKNOWN 

GND INPUT REFERENCE 

!V X ) INPUT (V R ) 




POWER SUPPLY V OPEN COLLECTOR 

GND !PSG) COMPARATOR OUT 

(COMP) 



NEGATIVE RAMP POLARITY OFFSET RAMP DIGITAL 

UNKNOWN IRU-I DET/P0S CORRECT REFERENCE GN0 I0GI 

RAMP UNKNOWN (0C) <RR! 



Dual-ln-Line Package 




Order Number LF13300N 
See Package 20 



5-2 



absolute maximum ratings 

Supply Voltage ±18V 

Power Dissipation (Note 1) 570 mW 

Operating Temperature Range 0°C to +70°C 

Junction Temperature 110°C 

Storage Temperature Range -65° C to +150°C 

Lead Temperature (Soldering, 10 seconds) 300°C 



electrical Characteristics (Vs = ±15V, Ta = 25°C, unless otherwise noted) 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Analog Input Current, l|f\j 


Vx = 0, Currents into Pins 17 and 18, 
Test Circuits 1 and 2 




50 


500 


PA 


Analog Input Voltage Range 


Vx adjusted until l|f\|| > 10 nA, 
Test Circuits 1 and 2 


±11 


±12 




V 


Analog Input Resistance 


Vx = 0V, Test Circuits 1 and 2 




1000 




MH 


Reference Input Currents, Ir 


Vr = 10V, Current into Pin 16, 
Test Circuit 3 




100 


1000 


PA 


Reference Input Voltage Range 


Vr Adjusted until |Ir| > 10 nA, 
Test Circuit 3 







11 


V 


Reference Input Resistance 


Vr = 10V, Test Circuit 3 




500 




Mil 


Offset Correction Voltage, — Vg 


Test Circuit 4 




-12 




V 


Offset Correction Input Current, IOC 


Test Circuit 5 




200 


2000 


PA 


Op Amp Slew Rate 


Test Circuit 6 




10 




V/us 


Op Amp Bandwidth 


Test Circuit 7 




3 




MHz 


Buffer Slew Rate 


Test Circuit 9 




25 




V/us 


Comparator Response Time 


200 uV Input Step, 100uV 
Overdrive, Test Circuit 1 1 




2.5 




MS 


Comparator Output Saturation 


Vcc = 5V . R L = 2k, 




0.2 


0.4 


V 


Voltage 


0°C < Ta < +70°C, Test Circuit 1 1 










Logic "1" Input Voltage 




2.0 




6 


V 


Logic "0" Input Voltage 


All Switching Input Pins 5, 6, 7 and 8, 
0<Ta<+70°C 


-5 




0.8 


V 


Logic Input Current 






2 


20 


MA 


Power Supply Voltage Range, ±Vs 


Vr < V + - 3V, V| N = 0V 
±Vs is Variable 


±4.75 




±18 


V 


Power Supply Currents, ±lc; 






±4 


±11 


mA 



Note 1: For operating at elevated temperatures, the LF13300 in the DIP package must be derated based on the thermal resistance of 100° C/W 
junction to ambient. 



5 3 



electrical characteristics 

12-bit plus sign A/D converter system characteristics. (LF13300 with MM5863). (Circuit 
10.000V, 0°C < Ta< +70°C unless otherwise noted.) 



configured as in Figure 1, Vr 



PARAMETER 



Resolution 

Nonlinearity 

Differential Nonlinearity 

Ratiometric Gain Error 

Gain Error Drift 

Zero Reading Drift 

Analog Input Voltage Range 

Analog Input Leakage Current 

Analog Input Resistance 

Reference Input Voltage Range 

Reference Input Leakage Current 

Reference Input Resistance 

Conversion Time 

15V Supply Currents 

— 15V Supply Currents 



CONDITIONS 



5V Supply Currents 



Vr = 5.000V, -10V < Vx < +10V 



Vx = ±10.000V, Ta = 25 C 
Vx = 10.000V 
V X = 0V 

T A = 25°C, V X = 0V 
T A = 25°C, Vx = 0V 
T A = 25°C, Vr Varied 

T A = 25°C, Vr = 10.000V 
V|N= 10.000V, F c = 250kHz 
LF13300, V + Current 
LF13300, V - Current, 
MM5863 Vqg Current 
V|N = 0V, MM5863, VsS Current 



MIN 



14 



TYP 



MAX 



H/8 


±1/2 


±1/8 


±1/2 


±1/2 


±2 


±1 




±0.5 




±12 




50 


500 


1000 






12 


100 


1000 


500 






36 


4 


11 


27 


44.8 



23 



UNITS 



38.5 



Bits 

LSB 

LSB 

LSB 

ppm/°C 

ppm/ C 

V 

pA 

Mil 

V 

pA 

Mfi 

ms 

mA 

mA 

mA 



ac test circuits 



Test Circuit 12 
12-Bit A/D Converter 



POWER GND | 
-15V O— 



ANALOG INPUT I 
VOLTAGE * 



ANALOG GND 



ENE I 
TOR 1 



MYLAR 
CAPACITORS 



HP 

0.1 U F 



LF 13300 RR 



C 0C2 
C 0C1 
C 0C3 



"J - 

DIGITAL 
GND 



► POL/SEROUT 

► 0VERRANGE 

► 2 11 MSB 



MBIT BINARY 
OUTPUTS 



17 a cui 

CLK ♦ 27 ?"z"i> 0l f 

SERIAL 250 kHz PARALLEL OUTPUT 

CLK CLK /SERIAL ENABLE 



" fc END OF 
~~* CONVERSION 



START 

conversiom 



5-4 



typical performance characteristics 



Integrator Capacitance, 
C vs fci_K f° r Different 
Integrator Resistances, R 





z ^ 




S^"M=mf v 




^15vf 




v~ 


-hi 












l! " m 'III 










i 










>Jj\iH= 1M, Vr - 10V 




F^ 


















— 










4*- 














: 1 




0.01 


R = 2M, V R 


= iov-^vJ 


fs 






-=p 


R = 10M, V R = 10 


















— 




,. ~ 




r 


0001 


', ■Hill 1 1 -Hli : i>L 


nil 



Integration Time Constant 
tRC) vs fcLK f ° r Different 
Reference Voltages, Vr 



V f ~f-f^ti 








Lv«- 


■15V 
































ft Tv 










Njli 




sL |! l 












^"Fr^Hirfvt' ffH& 


























































-^^-tTtt: 








































■■ 


ij : . pi 




St 




"\\d \\\m 




sink 





f CLK ikH!) 



f CLK (kHz) 



functional description 



The LF13300 goes through the following 5 states during 
normal cycle: 1) Offset Correction; 2) Polarity Determina- 
tion; 3) Initialization; 4) Ramp Unknown; 5) Ramp 
Reference. 

Offset Correction Description (Figure 1) 

The Offset Correction scheme will drive the input of 
the comparator to its switching threshold when the 
analog input is zero and the timing components, RC, 
are bypassed. 

The Offset Correction input (OC) is driven high, closing 
switches S4— S9. 

The offset voltages are assigned as follows: Vosi — the 
input offset voltage of the buffer; VoS2 ~ tne input 
offset voltage of A1 ; Vqs3 — the input offset voltage of 
A2; VoS4 — tne input offset voltage of the comparator. 

S5 grounds the input of the buffer so that its output 
voltage is simply Vqsi. S6 bypasses R to keep the 
integration time constant, RC, from affecting the 
circuit operation. S4 makes the total equivalent input 
voltage to A1 be — Vosi — VOS2' S7 puts the op amp 
in a unity gain configuration with respect to the input 
of A2. S8 keeps the output voltage of the op amp at 
— Vb + VoS4 = ~ Vb' ' tne Off set Correction potential) 
since the comparator is placed inside the loop. C3 
samples the output of the — Vb generator. The voltage 
at the non-inverting input of A2 is — Vb + Vosi + 
VOS2 + VoS3 + VoS4 = VI. Thus, the sum of the 
offsets is stored on CI, and the differential voltage 
across the comparator is zero. 



Polarity Determination {Figure 2) 

The simplified diagram of the LF13300 in the Polarity 
Determination state is shown in Figure 3. S5 and S3 are 
closed during this period. S5 grounds the buffer input 
and Vx (the unknown voltage) is applied through S3 
to the non-inverting input of A1. The equation that 
describes the op amp output voltage is given in Figure 3. 
When Vx is applied to A1 at t], the output of the 
op amp slews to Vx and is integrated until t2, when 
S3 opens and S4 closes. This causes Vquj to slew down 

1 P2 
by — Vx leaving — - I Vxdt — Vb' on the output 
RC J t1 

of the op amp. The comparator output goes high if 
Vx > and remains low if Vx < 0- 



Initialization (Figure 7) 

During initialization, the LF13300 is configured the 
same way as it is in the Offset Correction state and the 
op amp output is brought back to the Offset Correction 
potential — Vb'. 

Ramp Unknown (Figures 2 and 3) 

In the Ramp Unknown state, if Vx > 0, S3 and S5 are 
closed, as shown in Figure 2, and Vx is applied to the 
+ input of the integrator. If Vx < and the LF13300 is 
connected as in Figure 3 with S2 and S4 closed. Vx is 
now applied through the buffer to the — input of the 
integrator. In either Ramp Unknown case, the op amp 
output ramps in the positive direction and Vx is applied 
to a high impedance JFET input. 



5 5 



functional description (Continued) 



Ramp Reference (Figure 4) 

In this state, the LF 13300 is configured with switches 
S1 and S4 closed. The reference voltage, Vr, a positive 
voltage, is applied to the buffer input and the op amp 
output ramps down until VrjUT = — Vb' where the 
comparator will trip. 

If Vx and Vr are assumed to be constant over their 
respective integration periods, the integrals of Figure 7 
are reduced to, 

Vx(t4-*3> V R (t 5 -t4) 



VX = t5-t4 
Vr t 4 -t 3 ' 

Since t4-t3 = 4096 clock periods and t5-t4 can be 
measured in clock periods, Vx/Vr = X/2^2, where X is 
a digital binary output representing an analog input 
VX with respect to Vr. 



RC 



RC 



8UF0UT R OP AMP IN 



OP AMP OUT 

-V B ' = -V B + V S4 



L ? 6 F 

Vr v x 




IP OUT 



54 S5 S6 S7 S8 S9 



ANALOG GND 



± oci =F _L v 

C0C2__ C0C3__ s 






v 



-V S RU- PD/RU+ OC RR 



POWER 
GND 



DIGITAL 
GNO 



FIGURE 1. Offset Correction Circuit 



5-6 



functional description (Continued) 



1 r<4 

-Vg + Vx + -^- / V x dt: Ramp Unknown for V|m > 



1 f'2 

B + v x + / Vx dt: Polarity Determination 

RC J ti 



(a) 
00 
O 

o 




®s 



L r 



ANALOG GND 



~ X 1 I s. v US4 

u X + | . COMPARATOR 

VQS3 A3N | + | N. 



— C — -Q- — 6— —6 — -o- — 



r Jtl-T- 

C 0C2_^ U oc 



T-' 



DG I 

o o- — A-l 

6 r r " 

V S RU- PD/RU+ OC RR 



v 



POWER 
GND 



DIGITAL 
GND 



FIGURE 2. Polarity Determination Circuit or Ramp Unknown Circuit for Vx > 



1 f *4 
V0UT= -V B '+ — / V X dt 



: J t 3 



BUFOUT R OP AMP IN 




tl 



±Ji_JX C0MPARAT0R 



TTTi^TrrrtTrT 

,„< I i — 



DG | 

r"2i-W 

V S RU- PD/RU+ OC RR 



POWER 

GND 



DIGITAL 

GND 



FIGURE 3. Ramp Unknown for V x < 



5 7 



o 
o 

CO 
CO 



functional description (Continued) 



vqut* = - v b' h 



/ 4 v x dt- / V R dt j 




More accurately 



v = -v B ' + 



RC 



tS+A f*4 \ 

VRdt+l V x dt 

14 J <3 / 



+ 6 



Where 6 is the incremental voltage overdrive needed to fully switch the comparator 
and A is the sum of the additional time required to develop 6 and the comparator 
propagation delay. 

FIGURE 4. Ramp Reference Circuit 





INITIALIZATION 


~ 




POLARITY 




DET 


RMINATION 




COR 


OFFSET I 

SECTION ""1 





- RAMPUNKNOWN V x ..-0. 







— 




POLARITY 
DETERMINATION 


OFFSfiT 
CORRECTION 










STAND BY -*-! 




rr 


I— INITIALIZATION 


RAMP J 








L — - RAMPUNKNOWN 




'4 '5 '6 i'o '1 1 '2 '3 

FIGURE 5. Timing Diagram 



4 '5 '6 



application hints 

Increasing the Input Impedance 
MM5863 12-Bit A/D Converter 



of the LF 13300, 



The input impedance of the LF 13300, MM5863 A/D 
converter can be increased 1 to 2 orders of magnitude 
over the typical 1000 Mil cited in the specifications by 
insuring that the signals that switch the LF 1 3300 do not 
overlap. A circuit that eliminates switching overlap by 
introducing a Delay ltd) * 3.3k x 100 pF = 300 ns to 
the rising edge of the signals from the MM5863A is 
shown in Figure 6. Figure 8 shows the operation of this 
circuit. The total delay time t r ' of the output will be 
equal to the inherent gate rise time, t r , plus the RC 
delay, td. The fall time, tf will be the basic gate delay. 

Nulling the Residual Offset in the LF13300 

The residual offset of the LF 13300 is < 200 /jV which 
is negligible for most applications. This can be reduced 
to < 40 ,uV by lowering the dock frequency from 
250 kHz to about 75 kHz. If a residua! offset of 
< 40 ,uV is required, we may trim out the remainder 
as shown in Figure 9. This circuit applies a negative 
step to the Offset Correction capacitor, C(5C2' ^V means 
of a variable capacitor which is adjusted until charge 
injection imbalance of the Offset Correction switches 
are cancelled. 




^-f-».oc 



Eliminating Errors Due to Power Supply Noise 

For many applications, power supply noise (f > 10 Hz} 
causes errors which reduces the accuracy of the system. 
In most applications, noise can be adequately eliminated 
by putting a series resistor (100^2) in the power supply 
line with a 10 yF tantalum capacitor connected at the 
power supply pins {Figure 8). The 10 /iF capacitor is, 
in addition to the normal 0.1 (jF ceramic disc capacitors, 
used as supply bypass capacitors. 

Errors caused by noise on the negative supply, — Vs, 
can be further reduced by replacing, CoC3 with a 
10 /jF low leakage tantalum capacitor. Since — Vg is 
3V above -Vs, any noise appearing at -Vs appears at 
— Vg; the 10 /laF capacitor eliminates the noise at — Vg. 

Miscellaneous 

Since none of the output pins of the LF 13300 employ 
short-circuit protection, extreme care should be taken 
when breadboarding or troubleshooting with the power 
"ON". 




> K " 



J O. 



FIGURE 7. Rise Time Delay Circuit 



FIGURE 6. Overlap Elimination Circuit 



OFFSET DC 7 

CUHHECTIQN Q . " ^ » 
SIGNAL 



#" 



h 



Ey 2pF-20oF VARIABLE CAPACITOR 

FIGURE 8 



-v s O — WV 




FIGURE 9. Residual Offset Nulling Circuit 



5-9 



typical applications 



15V O- 
5VO- 



POWER . 

GNO | 



-15V O- 



V + 4 



Vo = 10.000V O- 



VxO- 



ANALOG 
GI\ID 



G | 1 



POLYPROPYLENE 
CAPACITOR 



LOW LEAKAGE 
MYLAR ' 
CAPACITORS 



0.01 uF 

p. 



PG COMP 

OOT 



Vx 



LF13300 RR 



OP AMP 
OOT 



c OC2 



c OC1 



COC3 



VqG 
26 



-r 

DIGITAL 
GND 



^25 | 28 \2 V SS 24 



P/S SAD 

COMP POL/SER 



RR MM5863 



250 kHz 
CLOCK 



SERIAL 
CLOCK 



->. SERIAL OUT 



•— ► 



v OUT 



OP AMP 
OUTPUT 



_TLT 




COMPARATOR 5V I i i 

OUTPUT I I 1 

nv ■ 1 ' 



i n 



w~i 



ENOOF 5V 
CONVERSION 



1 



SERIAL CLOCK ,„ 
INPUT I 

0V I 



SERIAL OUT 5V I 
0V 1 



Rjuinjuuuuuuuum 



IttlMt 

(+) OR | 2SB ] 4SB | 6SB | 8SB | 10SB j LSB 
POL MSB 3SB 5SB 7SB 9SB 11SB 



t i | t | 
(+) OR | 2SB ] 



FIGURE 10. 12-Bit Plus Sign Serial Output A/D Using the LF13300 and the MM5863 



5-10 



typical applications (Continued) 



15V O- 
5V O- 

POWER , 



WER.— 4- 

gndJ_ 



15V O- 



VrO- 



v x O- 



ANALOG 
GND 



b | » 



POLYPROPYLENE . 
CAPACITOR 



LOW LEAKAGE 

MYLARS 

CAPACITORS 



HP 

0.1 jjF 
0.1 uF 



«n 



vx 



LF13300 RR 



OP AMP 
OUT 



C 0C2 
COCI 
COCI 



V GG | 25 
261 



DIGITAL 
GND 



V SS 



w 
w 
o 
o 



POL 

OR 

MSB 

2SS 



RR MM5863 



LS8 
BE 

sadeoc 



12 BIT 

BINARY 



TRI STATE 
DATA OUTPUT 



250 kHi SELECT A/D 

CLOCK 



*-► 



a 



OUTPUT 
DATA 



< 



DATA FROM PREVIOUS CONVERSION 



^ TRI SI 



END OF 5V 
CONVERSION 
(OUTPUT ENAB 

0V 



OF 5V 1 1 

ION / \ 

LEI I \_ 



START CONVERSION 



— -] |->- 5 CLOCK PERIODS 



MAXIMUM OF 4864 CLOCK PERIODS TO 
" READ VALID DATA FROM PREVIOUS CONVERSION 



FIGURE 11. 12-Bit Plus Sign A/D in Intermittent Conversion Mode 



4-Channel Differential Multiplexer with Autozeroed 
Instrumentation Amplifier and 12-Bit A/D Converter 

Figure 12 shows a low speed, high accuracy, data acqui- 
sition unit where the analog input signal is acquired 
differentially and preconditioned through an LF352 
monolithic instrumentation amplifier. To eliminate 
amplifier offset errors, autozeroing circuitry is added 
around the L.F352 and is timed through the MM5863 
and flip-flop C. Flip-flops A and B form a 2-bit up 
counter for channel select. 

The instrumentation amplifier is zeroed at power-up and 
after each conversion as shown in the timing diagram; 



during this cycle the multiplexer is disabled. When the 
system does polarity detection and then A/D conver- 
sion, the LF352 is active and the multiplexer is enabled. 
The zeroing cycle for the LF 13300 and the LF352 
lasts for 256 clock periods, so the maximum clock 
frequency will depend upon the required accuracy and 
the minimum zeroing time of the instrumentation 
amplifier. Notice here that the system accuracy will be 
less than 12 bits since it will be affected by the gain 
linearity of the instrumentation amplifier. 

For more details concerning data acquisition, see 
AN-156and LF11508, LF1 1509 data sheet. For details 
on the instrumentation amplifier, see LF352 data sheet. 



5-11 



typical applications (Continued) 

15V -15V 



si o— 




ANALOG 
GND 



-vw- 



-vw- 



iVO— \ 



I 10V 15V -15V 
LB0070 I 1 o o 

■i lis U |4 F 



2.2 ;jF 
0.1 jF* 



Hh 



Li" |» 



Low leakage mylar 
Polypropylene 



23 

C3 



_ 15V 5V ZERO PULSE 

O POLARITY 27 



°CL0CK T 

■\ 2QQ kHz y 



DOVERRANGE 
^ MSB 




d 



►20k A0 

0.1 uF > Q 



) 1 



CLR 
CLK Q 

1/2MM74C74 

Q 



Bz 



j)'3 



PS PS 



CLR 
CLK < 

1/2MM74C74 



Ft^ 



DIGITAL 
OUT 



F 

T 



1 



CLK 1 

1/2MM74C74 



3 p S o- — •— *wv — 05 

CLR I 

^ 0.1 „F 

4 V 

MM74C09 A 



'CLOCK MAX = 200 kHz 



FIGURE 12. 4-Channel Differential Multiplexer with Autozeroed Instrumentation Amplifier and 12-Bit A/D Converter 



~LTL 



nn 



n_n 



_r 



-rLTZpTn TLT 



"L_nj 



ZERO 

PULSE 



~L 



n 



n 



_TL 

_r 



ENABLE | 



LF352 In 



u . u _ 

A« (St-S,l Av(S2-S;> 

u wr 

FIGURE 13. Timing Oiagram for Figure 12 



A V (S3-S 3 ) 



\ 



5-12 



typical applications (Continued) 




I 130 

6— wv 



-L...-L 



10 uF 1,.F 



IF X 



■ LUM I I 1U 

G.I -F* 

0.1 ;;F* 



100l,^ < 4 'y V " V REF IE 



NALQG O— 
INPUT O 



HK 



ii ,j i 



Hh 



1 ^F TO.^F 



T T 



FEE 



| 7 1 0.0047 ,.F '—4 V- ♦ WV-I 



IT- 



K3t 



iJ OVERRANGE 

6 CS8871 ^ 



Tr L^>>^@ 



J_ 



NSB3S81 DISPLAY 



Low leakage mylar 
Polypropylene 



MSD SSD 



□ □ III III 

U.U.U.U. 






^ 



>" 




C. P. POSITIONING FOR 



Note 1; All diodes, 1N914. 

Note 2: All resistors 1/4W, 5% tolerance. 

Note 3: Circuit drawn for 8V full scale operation input scaling not shown. 

FIGURE 14. 3 3/4 and 3 1/2-Digit DPM Schematic Diagram 



5-13 



typical applications (Continued) 

3 3/4-Digit (±8191 Counts)/3 1/2-Digit (±1999 Counts) 
DPM 

In this circuit of Figure 14, the LF13300 and MM5863 
interact as previously described. The CMOS counter 
(MM74C926, MM74C928) is connected to count clock 
pulses during the ramp reference cycle of the LF 13300. 
The counts are latched into the display when the com- 
parator output trips, (goes low), as shown in the timing 
diagram Figure 15. 

The RC network consisting of R1 and C1 is a low pass 
filter that prohibits the fast transients that occur on the 
comparator output during Offset Correction from 
loading any erroneous counts into the counter. 

RAMP UNKNOWN FOR V| N > 



OP AMP OUTPUT 
PIN 13ILF13300I 



COMP0UTP0T . 
PIN3{LF13300) < 



The DPM is able to operate from a single 15V power 
supply with the aid of a dc-dc converter. The LM555 
generates the negative voltages required in the circuit 
and also doubles as the clock. The combination of 
Q1, R2, R3 and R4 forms a level shift to convert the 
output swing of the LM555 to a 0V— 5V swing that is 
compatible with the logic. The LM340— 5 drops the 
incoming 15V to 5V for use by the logic circuits and 
the LED display. 

This circuit can be a 3 3/4-digit DPM if the MM74C926 
is used or a 3 1/2-digit DPM if the MM74C928 is used. 
These counters are pin compatible and physically inter- 
changeable. 



RAMP UNKNOWN FOR V [N < 




mr 



>u 



(OE)EOC I 
PINS 3, 23 (MM5863I I 



RESET 
PIN 13 \f 
narq7fil ' 



CLOCK . 
PIN 12 
IMM74C926) 



"uuuuuir 



MM58G3 CLOCK 



miuuir 



LATCH ENABLE " 
PIN5(MM74C326I 



I DISPLAYS NO. OF CLOCK PULSES 

COUNTED WHEN CLOCK WAS 

ENABLED 



FIGURE 15. Timing Diagram for 3 3/4-Digit DVM 



electrical characteristics 

3 3/4-digits plus sign (±8191 counts) DPM system characteristics. 

(Circuit as in Figure 18, Vg = ±15V, Vr = 4.096V, Ta = 25°C, unless otherwise noted). 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Resolution 


-8.2V < Vx<+8.2V 


16,382 






Counts 


Nonlinearity 


V|N = 4.000V 




±1/8 


±1/2 


Counts 


Ratiometric Gain Error 


V|N = 4.000V 




±1/2 


±2 


Counts 


Gain Error Drift 


V|N = 4.000V, 0°C < Ta < +70°C 




±1 




ppm/°C 


Zero Reading Drift 


V||M = 0V 




±1 




ppm/°C 


Analog Input Voltage Range 




±11 


±12 




V 


Reference Input Voltage Range 


Reference Varied 







+12 


V 


Analog Input Leakage Current 


V|M = 0V 




50 


500 


pA 


Reference Input Leakage Current 






100 


1000 


pA 


Analog Input Resistance 


V| N = 0V 




1000 




MJ1 


Conversion Time 


V| N = 4.000V, fc= 125 kHz 






74 


ms 



5-14 



typical applications (Continued) 



Component Side Foil 




FIGURE 16. PC Board for 3 3/4 and 3 1/2-Digit DPM (Shown 1/2 Size) 



jmwr 



T . % 







\ » 


%MMftC0fe. 


' 1 
1 * 




1 

1 

t 

t 




* — vvv — ^timfc' 



Pi 



FIGURE 17. Stuffing Diagram for 3 3/4 and 3 1/2-Digit DPM (Shown 1/2 Size) 



5-15 



typical applications (Continued) 

4 1/2-Digit (±19,999 Counts) DPM 

The following circuit illustrates how a 4 1/2-digit DPM 
can be realized using the LF13300 and the MM5330. 
The MM5330 is the display and control for this inte- 
grating system. 

It contains the counters and latches together with a 
multiplexing system to provide 4 digits of display with 
one decoder/driver. It also provides a sign bit that is 
valid during overrange and a ten thousand count digit 
for a full display of ±19,999 counts. By eliminating 
the rightmost digits it may also be used as a 2 1/2 or 
3 1/2-digit DPM. 

The LF 13300 features automatic zeroing of all offset 
voltages in its integrator, comparator and buffer ampli- 
fiers and, unlike conventional dual slope techniques, 
provides an input impedance > 1000 Mil. 

The waveform at the integrator output is shown in 
Figure 18. At the rising edge of the reset pulse the 
unknown input voltage is applied to the integrator for 
a reference period of 18,000 clock periods. After this 
reference period, the 4.0000V reference is applied to the 
integrator and the counter is started. The reference 
voltage is integrated until the comparator switches. 

At this point, the accumulated counts are transferred 
from the counters to the latches and zeroing begins 
until the next reset pulse. 



It may be obvious, however, that while we have 
eliminated several of the basic dual slope circuits 
disadvantages, we have created another— the number 
of counts are no longer proportional to V|[\j but rather 
to (V|viAX — V|l\|)' ' n f act ' wnen we short V|pg to ground 
we are actually measuring our own 2.2000 V|\/]AX- 

What is done in the MM5330 is to code convert the 
number of counts as shown in the count diagram. This 
chart shows a code conversion starting at the time of a 
reset. The first 18,000 counts are the reference period 
after which time the integrator changes slope. If a com- 
parator crossing is detected within the next 2000 counts, 
a plus overrange condition will occur at the display. 
This condition results in a lit "+" sign, a lit "1" and 4 
blanked right most digits. A transfer at 20,000, however, 
will create a reading of +1.9999, at 20,001 a reading of 
19.998 and so on, until at 39,999 a reading of +0000 
would be displayed. A transfer occuring at 40,000 
would cause a -0000 display and so on until 60,000 
counts were entered, at which time a —1 with 4 blanked 
digits would be displayed, indicating a minus overrange 
condition. 

The display interface used is a TTL, 7-segment decoder/ 
driver and 4 2N4403 transistors. The ±1 digit is driven 
directly by TTL. The clock-synchronous reset and 
transfer functions prevent any cyclic digit variations 
and present a blink-free, flicker-free display. 



COMPARATOR 
OUTPUT 



INDETERMINATE 



RESET 
PULSE 



JL 



_n 



INTEGRATOR 
OUTPUT 




RAMP 
REFERENCE 



Note. Here the LF13300 always operates as an autozeroed, high input impedance inverting integrator; 
bipolar input voltages are handled by offsetting the analog ground by 2.2V. 

FIGURE 18. Timing Diagram for 4 1/2 Digit DPM 



5-16 



typical applications (Continued) 




0.01 ,;F POLVPfiOmtNt 



OPTIONAL SWITC 
FORMOVIN 
DP. FO 
VARIOUS RANGES | 



_=_o-pG> !j 

no GROUND I 



CONNEC 

FfiRZV FULL SCALE 
DECIMAL POINT (FIXED) 



sv Inverters^ MM74C14 Hex Schmitt Trigger (MOS) 

Two letters (AA, BB. . .) NAND gates ■* MM74C00 CMOS quad NAND gates 
One letter (A, B. . .) NAND gates -* DM7400 TTL quad NAND gates 
All resistors 1/4W, 5% unless otherwise noted. 
All capacitor values in ^F unless otherwise noted. 



w 
w 

o 
o 



INDUCTIVE COMPONENTS U5X0Z! 

MICH0TRANPCT6931 

TRANSFORMER 



±1 □ □ II 
T I. U. U. L 



|, \, |] |. |i |. |, |. |. |,.|„|, ! |,3|..|.!|,.|l.|.l|..p.|ll|Hp| 




FOR LOWNOiSE 



NSB5917 Display (Front View) 



First letter code: 




(Second letter code) 


A --> anode 
C -* cathode 


MSD- digit 2 
SSD- digit 3 


III; 
LLI 




TSD- digit 4 
LSD^ digit 5 







FIGURE 19. Schematic Diagram for 4 1/2 Digit DVM 

5 17 



o 
o 

CO 
CO 

E 



typical applications (continued) 



Component Side Foil 




Bottom Side Foil 




FIGURE 20. PC Board for 4 1/2-Digit DVM (Shown 1/2 Size) 



5-18 



typical applications (Continued) 



1.^ — v*EJ 



AT 

m _ l tm,t 



^44 



| „ F L I O.M7»f J..J |, J II U ,,| „U , I |,I, f J^lo* 



... i„ 



CSS.. , 



NSB5;J$^PL|pgf 



§M 



GO Q - 

1 § 

"Tr" 



SiBBl 
» -tJ ; 






SV PW 



FIGURE 21. Stuffing Diagram for 4 1/2-Digit DVM (Shown 1/2 Size) 



ac test Circuits (Continued) 



Test Circuit 1 
Analog Input Characteristics Test with RU — High 



v s O 



NCO- 



-v s o- 



5V O- 





O^x 



-O NC 



-O -12V 



Analog Inpu 
1 



Test Circuit 2 
t Characteristics Test with PD/RU+ High 



V s O 



NCO- 



-v s O- 



5VO- 



r& 





-OV x 



-O NC 



-0-12V 



5-19 



aC test Circuits {Continued} 

Test Circuit 3 
Reference Input Characteristic Test with RR High 



v s O- 



NC O- 

-v s O- 



H> 



m 



O NC 

One 



v s o- 



v s o- 



Test Circuit 4 
— VB Voltage Measurement Test 



to' 



ra 



-0-«» 



Test Circuit 5 
Offset Correction Input Current, Iql Test 



v s O- 



-v s O- 




± 



+ —" <4 O 12V 



-v s ID- 



Test Circuit 6 
Op Amp Slew Rate Test 




ZTL 



^T 



v s O- 

NCO— 



-v s O- 



5VQ- 



Test Circuit 7 
Frequency Response Test 



r-Hgh 




1 



) SIGNAL 
'GENERATOR 



-O vqu 



-, T 



v s O- 

NCO- 

-v s O- 



Test Circuit 8 
Open Loop Gain Test 



!-«- 




1 



1WI INPUT 

-WV-0% 



^-j-— l 



1 ^F "=" 

A VOL "- 
V O UT x 10 5 



V|N 



-Ov„ 



5-20 



aC test Circuits (Continued) 



v s O 



NCO 



-v s O 



5VO- 



tt 



Test Circuit 9 
Buffer Slew Rate Test 



H> 



n. 



-O INPUT 



— P^ 

< 20 pF 

>NC SlOOk 






u 0UT 



-0-12V 



w 
w 
o 
o 



v s O- 



NCO 



-v s O- 



5VO- 



4> 



Test Circuit 10 
Buffer Voltage Gain Test 




1 v 0UT 



A V = 1 



VQUT 
1000 V||\i 



-0-12V 



5 21 



o 
o 

CO 
CO 

c 



ac test Circuits (Continued) 



Test Circuit 11 
Comparator Response Time Test 



v s O- 



C0MPARAT0R-. 
OUT^" 

-V s O 



5VO 



LF13300 





SYSTEM OFFSET 
ADJUSTMENT 



17 - 



I NC 



10ky 



100 



-0-12V 




-12 + 100nV 

-bE- ,2V 

-12-100/iV 



100 mV 
-100 mV 



3^ 



522 




Analog to Digital (A/D) Converters 



For additional application information, see 
AN -155 at the end of this section. 



2 
en 

W 

w 
o 



MM5330 4 1/2 -digit panel meter logic block 



general description 



The MM5330 is a monolithic integrated circuit which 
provides the logic circuitry to implement a 4-1/2 digit 
panel meter. The MM5330 utilizes P-channel low thres- 
hold enhancement mode devices and ion-implanted 
depletion mode devices. All inputs and outputs are TTL 
compatible with BCD output for direct interface with 
various display drivers. 



features 

■ dc to 400 kHz operation 

■ TTL compatible inputs and outputs 

■ BCD output code 

■ Overrange blanking 

■ Valid sign bit during overrange 

■ Standard supply voltages; +5, — 1 5V 



connection and block diagrams 

Dual-ln-Line Package 

SSO TSO ISD RESET THANSFER CLOCK 





16 




15 


14 


13 


12 


,, 


10 




9 
















































1 




2 


3 


d 


5 


G 


J 




8 



Order Number MM5330N 
See Package 19 



MSO BCD BCD BCD SGN BCD 

"i" "2" "4" ■■%■■ 

TOP VIEW 




5-23 



absolute maximum ratings 



Voltage at Any Pin 

Operating Temperature 

Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 



V ss +0.3V to V SS -25V 

0°C to +75°C 

-40°Cto+125°C 

300°C 



electrical characteristics 

T A within operating range, V ss = 4.75V to 



5.25V, V DD = -16.5V to -13.5V unless otherwise specified. 



PARAMETER 



Power Supply Voltage (V ss ) 

Power Supply Voltage (V DD ) 

Power Supply Current (l ss ) 

Input Frequency 

Reset or Transfer Pulse Width 

Input Voltage Levels 
Logic "1 " 
Logic "0" 

Clock Input Voltage Levels 
Logic "1 " 
Logic "0" 

Output Current Levels 
Digit Output State 
Logic "1" 
Logic "0" 

All Other Outputs 
Logic "1 " 
Logic "0" 

Delay From Digit Output to BCD Output 



CONDITIONS 



V ss = 5V, V DD =-15V 

Inputs Driven by TTL or Square Waves 

Inputs Driven by TTL or Square Waves 

Driven by Sinewave 
Driven by Sinewave 

V ss = 5V, V DD =-15V 

V Forced To 4.75V 
V Forced To 4.5V 

V Forced To 3V 
V n Forced To 0.4V 



4.75 
-16.5 



dc 
200 

3 
-15 

V ss -0.5 
V--25 



100 
-5 



100 
-2 



5 
-15 



MAX 



5.25 

-13.5 
30 
400 



5 
0.8 



Vss+0.3 
V«-4.5 



UNITS 



V 

V 

mA 

kHz 

ns 

V 
V 

V 
V 



M A 
mA 



MA 
mA 



FUNCTIONAL DESCRIPTION 

Counters: The MM5330 has four -M0 counters, one 
-H counter, and one H-2 for a count of 80,000 clock 
pulses. A ripple carry is provided and all counter flip- 
flops are synchronous with the negative transition of 
the input clock. The last flip-flop in the divider chain 
(-^2 in the block diagram) triggers with the "0" to "1" 
transition of the previous flip-flop. The count sequence 
is shown in the first column of the count diagram. 

Reset: All counter stages are reset to "0" and the INT 
flip-flop (driving the INT output) is set to "1" on the 
first negative clock transition after a "0" is applied to 
the Reset input. The internal reset is removed on the 
first negative clock transition after the internal reset 
has occured and a "1" has been applied to the Reset 
input. This timing provides an on-chip reset at least one 
clock cycle wide and a one cycle delay to remove reset 
before counting begins. 

Transfer: Data in the counters is transferred to the 
latches when the Transfer input is at "0." If the 
Transfer input is held low the state of the counters is 
continuously displayed (see count diagram). Data will 
cease to transfer to the latches on the first positive clock 



transition after the first negative clock transition after a 
"1" is applied to the Transfer input. This provides a 
transfer pulse at least one half clock cycle wide and a 
half clock cycle delay to remove the transfer signal 
before the counters change state. 

INT: The integrate output is used to set the charge time 
on a dual slope integrator. INT is "1" from reset to the 
18,000th clock pulse, then "0" until the next reset. The 
dual slope integrator is the voltage monitoring part of 
the external circuitry needed for a DPM. It charges a 
capacitor at a rate proportional to the measured voltage 
while INT is "1," then discharges at a rate proportional 
to a fixed reference as shown in the dual slope diagram. 
When the output of the integrator reaches 0V a pulse is 
generated and fed into the Transfer input of the chip. 
As the dual slope diagram indicates, the number in the 
latches is proportional to the measured voltage. 

Multiplexing: The modulo 4 multiplex counter is 
triggered by the carry from the second decade counter, 
making the multiplex rate one hundredth the counting 
rate (4 kHz for a 400 kHz clock). The LSD, TSD, SSD 
and MSD (least significant, third significant, second 
significant and most significant digits) outputs indicate 
by a low level which decade latch is displayed at the 
BCD outputs. 



5-24 



FUNCTIONAL DESCRIPTION (Continued) 

Overrange Blanking and Sign: The data in the latch for 
the +2 counter is used to detect an out-of-range voltage. 
If this latch is "0" the BCD and 10k outputs are forced 
to all "1's" and the SGIM output is inverted. When the 
data in the overrange latch and the sign bit latch are "1" 
the sign bit generates the 9's complement of the decade 
latches and the complement of the 10k latch at the 
respective outputs. When the overrange bit is "1" and 
the sign bit is "0" true BCD of the decade latches and 
the uncomplemented 10k latch appear at the outputs. 

APPLICATIONS INFORMATION 

The MM5330 is the display and control for a modified 
dual slope system. It contains the counters and latches, 
together with a multiplexing system to provide 4 digits 
of display with one decoder driver. It also provides a 



sign digit, either plus or minus, and a ten-thousand 
counts digit for full display of ±19999. By eliminating 
the right-most digits it may also be used as a 2-1/2 or 
3-1/2 digit DVM chip. 

The basic modified dual slope system for which the 
MM5330 is designed, is shown in Figure 1. The integrator 
is now used in a non-inverting mode and is biased to 
integrate negatively for all voltages below V MAX . Thus 
if the maximum positive voltage at V lN is 1 .9999V, then 
v max would be set at 2.200V. In this way, all voltages 
measured are below V MAX . This eliminates the need for 
reference switching and provides automatic polarity with 
no additional components. Also, it can be shown that 
the amplifier input bias currents which cause errors in 
conventional dual slope systems are eliminated by merely 
zeroing the display. Thus low bias current op amps are 
not necessarily required unless a high input impedance is 
desired at V, N . 



count diagram 



INTERNAL STATES 



OUTPUTS WITH TRANSFER LOW 



x a. 

>! 

O U 


7? 


CO 


DECADE 


CO 


O 


COUNTERS 











LANKING 





U 


ZONE 























COMPLEMENT 

OUTPUT 

INTERVAL 



TRUE 
OUTPUT . 
INTERVAL 



3LANKING 

ZONE \ 









9 9 9 




9 9 9 




POSITIVE 
OVERRANGE 



POSITIVE 
VALUE 



DISPLAY 
ZONE 



NEGATIVE 
VALUE 



9 J 
J 



NEGATIVE 
OVERRANGE 



L 1 
1 



BCD 
DECADE 
OUTPUTS 



OUTPUT 
BLANKED 



9 9 9 




9 9 9 








9 9 9 




CONTINUOUS 
COUNT 



525 



APPLICATIONS INFORMATION (Continued) 

Secondly, the use of a conventional op amp for a 
comparator allows zeroing of all voltage offsets in both 
the op amp and comparator. This is achieved by zeroing 
the voltage on the capacitor through the use of the 
comparator as part of a negative feedback loop. During 
the zeroing period, the non-inverting input of the 
integrator is at V REF . As this voltage is within the active 
common-mode range of the integrator the loop will 
respond by placing the integrator and comparator in the 
active region. The voltage on the capacitor is no longer 
equal to zero, but rather to a voltage which is the sum 
of both the op amp and comparator offset voltages. 
Because of the intrinsic nature of an integrator, this 
constant voltage remains throughout the integrating 
cycle and serves to eliminate even large offset voltages. 

The waveforms at the output of the integrator are as 
shown. The voltage at A is the comparator threshold just 
discussed. Simultaneously, with the opening of switch A, 
V, N is connected to the input of the integrator via 
switch B. The output then slews to V IN . Integration then 
begins for the reference period, after which time the 
reference voltage is again applied to the input. The 
output again slews the difference between V REF and 
V, N and integrates for the unknown period until the 
comparator threshold is crossed. At this point, the 
accumulated counts are transferred from the counters 
to the latches and zeroing begins until the next 
conversion interval. 

It may be obvious, however, that while we have 
eliminated several of the basic dual slope circuits 
disadvantages, we have created another— the number 
of counts are no longer proportional to V, N but rather 
to (V MAX -V| N ). In fact, when we short V, N to ground 
we are actually measuring our own 2.2000 V MAX - 

What is done in the MM5330 is to code convert the 
number of counts as shown in the count diagram. This 
chart shows a code conversion starting at the time of a 
reset. The first 18,000 counts are the reference period 
after which time the integrator changes slope. If a com- 



parator crossing is detected within the next 2000 
counts, a plus overrange condition will occur at the 
display. This condition results in a lit "+" sign, a lit "1" 
and four blanked rightmost digits. A transfer at 20,000 
however, will create a reading of +1.9999, at 20,001 a 
reading of 19.998 and so on, until at 39,999 a reading 
of +0000 would be displayed. A transfer occuring at 
40,000 would cause a -0000 display and so on until 
60,000 counts were entered at which time a -1 with 
four blanked digits would be displayed indicating a 
minus overrange condition. 

A typical circuit for a low cost 4 1/2 digit DPM is 
shown in Figure 2. The display interface used is a TTL, 
7-segment decoder driver and four P-type transistors. 
The ±1 digit is driven directly by CMOS. The clock- 
synchronous reset and transfer functions prevent any 
cyclic digit variations and present a blink-free, flicker- 
free display. CMOS analog switches are used as reference, 
zero, and input switches and used also in the comparator 
slew rate circuit. 

A problem with all dual slope systems occurs when short 
integrating times and high cIock frequencies are used. 
Because of the very slow rise time of the ramp into the 
comparator, the output of the comparator will normally 
ramp at approximately 1/10 of its actual slew rate. 
Thus, a significant number of extra counts are displayed 
due to the slow rate of rise of the comparator. A 
technique to improve this consists of capacitor C s and 
analog switch four. An unstable positive loop is created 
by this capacitor when the comparator comes out of 
saturation. This causes the output to rise at its slew rate 
to the comparator threshold. As soon as this threshold 
is reached the analog switch opens and zeroing is initiated 
as previously discussed. 

A simplified approach to performing the modified dual 
slope function combines the MM5330 and the LF1 1300 
dual slope analog block as in Figure 3. The LF11300 
provides the front analog circuitry required. This 
includes a FET input amplifier, analog switches, inte- 
grator and comparator. The LF 11300 provides auto 
zero, > 1000 Mfi input impedance, and a ±10V analog 
range. 



dual slope diagram 




526 



■^ 




H 




h T -H 



FIGURE 1. Modified Dual Slope 




> 200k -1- 



0HMSO 14MM5616 

VOLTS C 



"p-£ 



+1. 9999V 

ru 

1 9999V 



_n — II 



r^<l- 




rti 




-o- 



1 — vw- 



■:^ST 



^ 



10GpF | -WV 1 



37 



Jl 



FIGURE 2. Typical Application Low Cost 4 1/2 Digit Volt-Ohm Meter 



5-27 



typical applications (Continued) 




01 „.-f POLYSTYRENE 



U SWITCH f I [" 

JS RANGES | ' U *FS I 1 J 

CONNECT TO GROUND I 

FOR 2V FULL SCALE 

DECIMAL POINT (FIXED/ 



Inverters - MM74C14 Hex Schmitt Trigger (MOS) 
Two letters (AA, BB. . .) NAND gates -> MM74C00 CMOS quad NAND gates 
One letter (A, B. . .) NAND gates -> DM7400 TTL quad NAND gates 
!--* analog ground 
■>■ digital ground 
All resistors 1/4W, 5% unless otherwise noted. 
AH capacitor values in yF unless otherwise noted. 



INDUCTIVE COMPONENTS 

U5X021 MICROTRAN 
PCT6931 TRANSFORMER 



w 



r-CJ\p-0-«. 

I 0.001 ..F 

— Q001 ,.E 



(Second letter code) 




a 



-nr^l 



<>- 



II □ D D □ 
T I. U. U. U. U. 



1' M>M s M<M>hl"M»M4'l"M"M ! 'l"M" 



0IGIT1 -*j 

NSB5917 Display (Front View) 






IT 



.(FOR LOW NOISE 



3" 



First letter code: 

A * anode MSD -» digit 2 

C -» cathode SSD ♦ digit 3 

TSD ^ digit 4 

LSD - digit 5 

FIGURE 3. 4 1/2 Digit DVM 



5-28 



timing diagrams 



4 1/2-Digit DPM 



2 
w 

W 

w 
o 



COMPARATOR 
OUTPUT 



INDETERMINATE 




1_C 



RESET 
PULSE 



JL 



SL 



INTEGRATOR 
OUTPUT 




Note. Here the LF 13300 always operates 
as an autozeroed, high input impedance 
inverting integrator; bipolar input volt- 
ages are handled by offsetting the analog 
ground by 2.2V. 



529 




Analog to Digital (A/D) Converters 



MM5863 12-bit binary A/D building block 



general description 

The MM5863 is the digital controller for the LF13300D* 
analog building block. Together they form an integrating 
12-bit A/D converter. The MM5863 provides all the 
necessary control functions, plus features like auto 
zeroing, polarity and overrange indication, as well as 
continuous conversion. The 12-bit plus sign parallel and 
serial outputs are TR I STATE® TTL level compatible. 
The device also includes output latches to simplify 
data bus interfacing. 



See LF13300D data sheet for more information 



features 

■ 12-bit binary output 

■ Parallel or serial output 

■ Parallel TRI-ST ATE output 

■ Polarity indication 

■ Overrange indication 

■ Continuous conversion capability 

■ 100% overrange capability 

■ 5V, —15V power requirements 

■ TTL compatible 

■ Clock frequency to 500 kHz 



connection diagram 






(SCLK) SERIAL CLOCK 


Dual-ln-Line Package 


28 (P/S) PARALLEL/SERIAL 
SELECT 




2 
(SO START CONVERSION 




— (CLK) INPUT CLOCK 


3 
(0E) OUTPUT ENABLE 




26 (P0) POLARITY 
DETECT 


(LSB) LEAST 
SIGNIFICANT BIT 


2-"-i 




25 
V GG 




2 -,'-i 




^-V S s 




2 -10 L 




23 (E0C) END OF 
CONVERSION 




2 -9^ 




— (RN) RAMP NEGATIVE 




2 - 8 JL 




— (RP) RAMP POSITIVE 


PARALLEL DATA 


,-7-i 




20 {0O OFFSET 


OUTPUT LINES ' 


2 ' 




CORRECTION 




2 -6 




(RR) REFERENCE RAMP 




2 -5 




18 

GND 




„ 12 
2 -4 — 




17 (P0L/SD0I POLARITY/SERIAL 
DATA OUTPUT 




13 
2- 3 — 




— (OR) OVERRANGE 




L 2 2 — 




_1£_2~ 1 (MSBI MOST 
SIGNIFICANT BIT 




TOP VIEW 




Order Number MM5863N 






See Package 23 





5 30 



absolute maximum ratings 






Supply Voltage (Vss> 5.25V 
Supply Voltage (Vqg) -16.5V 
Voltage at Any Input 5.25V 
Operating Temperature 0°C to +70°C 
Storage Temperature -40°C to +1 50°C 
Clock Frequency 500 kHz 
Lead Temperature (Soldering, 10 seconds) 300°C 






electrical characteristics 








VsS = 5V, Vqg = ~1 5V, 0°C to +70°C, unless otherwise specified. 






PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Power Supply Voltage (Vss) 




4.75 


5.00 


5.25 


V 


Power Supply Voltage (Vgg) 




-13.5 


-15.00 


-16.5 


V 


Power Supply Current { 1 SS^ 








28 


mA 


Power Supply Current (Iqg) 








34 


mA 


Logic "1" Input Voltage 




3.4 






V 


Logic "0" Input Voltage 








0.8 


V 


Logic "1" Output Voltage 


Vss = 4.75, loH = 100 mA 


3.8 






V 


Logic "0" Output Voltage 


Vss = 5.25, l0L = -1-6mA 






0.4 


V 


Width of EOC 


Auto Cycle 


5/f 






Sec 


Prop. Delay PD to EOC 




4/f 




5/f+1 MS 


Sec 


Output Enable Time 


OE to Any Data Output, 
SC= 1,P/S = 






1.0 


US 


Output Disable Time 


OE to Any Data Output, 
SC = 1 , P/S = 






2.4 


Ms 


Output Enable Time 


P/S to Any Data Output 
Except Polarity, SC = 1 , 
OE = 






0.9 


lis 


Output Disable Time 


P/S to Any Data Output 
Except Polarity, SC = 1 , 
OE = 






2.2 


lis 


Output Enable Time 


SC to Any Data Output, 
OE = 0, P/S = 






1.0 


MS 


Output Disable Time 


SC to Any Data Output, 
OE = 0, P/S = 






2.4 


Ms 


Prop. Delay Serial Clock 


SCLK to POL/SDO 






0.6 


Ms 


Conversion Time 


Full Scale 






8966/f 


Sec 


Conversion Time 


100% Overrange 






13062/f 


Sec 





5-31 



functional description 

OPERATION 

The MM5863 is designed for use with the LF 13300 
analog front end. Four control signals are supplied to 
the LF13300 and 1 control signal is required from the 
LF 13300. The conversion cycle is composed of 5 
distinct phases. They are: Phase I — Offset Correct; 
Phase II - Polarity Detect; Phase III - Offset Correct; 
Phase IV — Ramp Unknown; Phase V - Ramp Reference. 

Phase I - Offset Correct (256 Clock Periods) 

This phase is initiated by taking the Start Conversion 
(SO and the Output Enable (OE) lines to a logic "1". 
At this time, Offset Correct (OC) will be a logic "1". 
The LF13300 requires this phase to correct any intrinsic 
offset voltage errors prior to the polarity detect phase. 

Phase II - Polarity Detect (256 Clock Periods) 

This phase is used to determine polarity of the analog 
input. At the midpoint of this phase, PD from the 
LF13300 is examined for polarity. If PD = logic "1", 
then the input voltage is positive. If PD = logic "0", then 
the input is negative. The Ramp Positive signal (RP) 
will be a logic "1", and Offset Correct will be logic "0" 
for the entire phase of 256 clock periods. The above 
operation is also necessary to determine which integrator 
input (positive or negative) of the LF13300 should be 
used for proper A/D conversion (see LF 13300 data 
sheet). 

Phase III - Offset Correct (256 Clock Periods) 

This phase is identical to Phase I and is used by the 
LF 13300 to eliminate any offsets induced as a result of 
the Polarity Detect Phase. Offset Correct (OC) will be at 
a logic "1". 

Phase IV - Ramp Unknown (4096 Clock Periods) 

The unknown input voltage is integrated for a fixed 
time during this phase. The result of the Phase II 
Polarity Detect Cycle determines whether RP or RN 
will be at logic "1". If Phase II indicates a positive input, 
the RP signal will be a logic "1". If phase II indicates a 
negative input, Ramp Negative (RN) will be a logic 

truth table 



"1". These 2 signals will never be at logic "1" simul- 
taneously. 

Phase V — Ramp Reference 

This phase is a variable length phase depending on the 
magnitude of the analog input voltage. During this time. 
Ramp Reference (RR) will be in the logic "1" state. 
When PD goes to a logic "0" state, or when the internal 
counter reaches 100% of full scale (8192 clock periods), 
the Ramp Reference (RR) signal goes to the logic "0" 
state, the counter output is loaded into the output 
register, and the End of Conversion, (EOC) signal goes 
to a logic "1". The Polarity Bit will reflect whatever 
value was determined during Phase II. The output 
register will hold the data until a new conversion is 
completed and new data is loaded into the register. 
The OE line must be low in the logic "0" state and SC 
must be high in the logic "1 " state to enable the outputs. 

DATA OUTPUTS 

Both serial and parallel outputs are available. In either 
case, OE must be low and SC must be high to enable 
the outputs. For parallel output, the P/S line must be 
low in the logic "0" state. For serial outputs, the P/S 
line must be high. In the serial mode, the data is shifted 
out of the Polarity /Serial Output POL/SDO line and all 
other data outputs are in the high impedance state. 
Each Serial Clock (SCLK) will right shift the output 
register one bit. Thus, 13 clock pulses are required to 
fully shift out the data. The data will be shifted out in 
the following order: Polarity, Overrange, MSB, 2SB, 

3SB LSB. If OE and P/S are in the logic "0" state 

and SC in the logic "1" state, all outputs will momen- 
tarily go to the logic "1" state for 1 clock period 
immediately preceding EOC. 

CONTINUOUS CONVERT MODE 

In this mode, the End of Conversion (EOC) output is 
connected to the OE input. As long as SC is in the 
logic "1" state, then each EOC will initiate a new con- 
version. The data outputs will be disabled for the first 
5 clock cycles after EOC goes high. 



INPUT 


SC 


OE 


P/S 


LSB 






















MSB 


OVER- 
RANGE 


POLARITY 


100% Full Scale 










1 


1 


1 


1 


1 


1 


1 


1 


1 


! 


1 


1 


1 


1 


Full Scale 










1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 





1 


Zero 

















































1 


Zero 




















































-Full Scale 










1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 








-100% Full Scale 










1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 


1 





Any 




1 


X 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


Any 







1 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


Serial Output 


Any 





X 


X 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


z 


Z 



1 = High 

= Low 

Z = High Impedance 

X = Don't Care 



5-32 



timing diagrams 

The following timing diagrams are shown for the MM5863 connected in the auto-cycle mode. 



Positive Input 



| PHASE I 

j OFFSET 

CORRECT 



PHASE II I 


PHASE III 


POLARITY 


OFFSET 


DETECT 


CORRECT 



PHASE IV 

RAMP 
UNKNOWN 



PHASE V 

RAMP 

REFERENCE 



- rLTLT 



sc , _| 

OC I 256X1/1 | | 256 X 1/f |_ 



i r 



nn. 



UTPUT \ / 
DATA /T\_ 



DATA FROM PREVIOUS CONVERSION 



~L 



>^ 



Negative Input 



OFFSET CORR 256 X 1/f 



RN 


| 4096 X 1 <f 


n 












RR 


J _ 8192 X 1/f | 












PD 


1 


1 
1 










EOCIOEI [ 5/1 ] 


5/1 [ 


n 


Serial Output 







JTJTJTJTJTJTJTJ~LJlJ _ lJTJT_n_rL 



Hpoooooooooooooc 

i T : ?qr I— I SR 



Jr 



- 2SB 

- MSB 

- OVERRANGE 
POLARITY 



SERIAL OUTPUT 



5-33 



timing diagrams (Continued) 



Output Enable/Disable Time 



/ \ 



DATA OUTPUT 



DISABLE 

DELAY 



3> 



< 



ENABLE 
"DELAY 



Serial Clock Delay 



/ \^^ r 



X 



Output Enable/Disable Time 



-/ \ 



ENABLE _ 
DELAY 



J r 0.4 



»%\ 



DISABLE 
DELAY 



block diagram 



Digital Control Integrated Circuit 



"BEF V|N 
1 i 



BIPOLAR ANALOG 

INTEGRATED CIRCUIT 

L F 1 3300 CONTAINING 

OP AMP, SWITCHES, 

COMPARATOR AND 

RELATED CIRCUITRY 



CLOCK 
GENERATOR 



SERIAL CLOCK 
(SCLK)' 



POLARITY 
DETECT <PO) 



t 



START CONV. (SO- 
OUTPUT ENABLE (OEI- 
PARALLEL/SERIALIP/SI- 



13 BIT 

COUNTER 



SWITCH CONTROL 
LOGIC 



n* 
b 



OVERRANGE 
DETECTOR 



OUTPUT 
LATCHES 



POLARITY 
LATCH 



J_\« 

12 LINES) PA 

— I — V DL 



TRISTATE 
BUFFERS 



TRISTATE 
ENABLE 



OVERRANGE 
-"►INDICATION 
{OR) 



PARALLEL 
UTPUT 



_ POLARITY/SERIAL DATA 



-► END OF CONV. (EOC) 



5-34 



typical applications 

1N1DM 

^| y. - .^ J LM340-15 ~^^) 1! 




' "" ^ 1 IM34D1S 



3 3/4-3 1/2-Digit DPM 

5.1 

VSA* 



I 100 

6— VW- 




-L. ,_L 




O v x O- 



Hh 






FEJZF 



3 V miv JH^UU 



n 



POir 



OVERRAN 
T-'B DSB871 ■>■ 



5V POLARITY 




$f*r®± 



— XJOO 



i 



NSB3881 DISPLAY 



MSD SSD TSD LSD 

III III D D 
U.U.U.U. 






-ifcxA- 



71 K^ 




DP. POSITIONING FOR 
„„„ „ , RANGES 
BOO mV * 

I 4 800V 

Oaov 



Note 1: All diodes, 1N914. 

Note 2: All resistors 1/4W, 5% tolerance. 

Note 3: Circuit drawn for 8V full scale operation input scaling not shown. 



5-35 




Analog to Digital (A/D) Converters 



DIGITAL VOLTMETERS AND THE MM5330 
INTRODUCTION 

The first of what could be called the modem digital 
voltmeter began to appear in the early sixties. Prior to 
that time a few laboratory types were available, but 
they were plagued by inaccuracy, temperature drifts, 
and other problems inherent in vacuum tube technology. 

One of the first successful, relatively low cost DMVS 
was a gated voltage-controlled oscillator configuration. 
The components of this technique consist of a high 
gain amplifier, a dc-to-frequency converter, and a linear, 
accurate frequency to-dc-converter developed from the 
reference voltage, which supplies the summing voltage 
at the input node. The amplifiers used were of the 
chopper stabilized type, that is, the error voltage is 
chopped to from an ac component which is amplified 
by ac coupled amplifiers then reconverted to dc. The 
choppers were made with light sensitive resistors, neon 
bulbs and light pipes. 

They were built as the only method possible to avoid 
the drifts and offsets which were unavoidable in early 
transistor technology. Obviously the low current op 
amps so readily available today, are a significant advan- 
tange over these old systems. 

The gate voltage was developed from the 60 Hz line. A 
problem which occurs when the gate is asynchronous 
with the frequency fed to the display counter, is also 
shown in Figure 1 . A beat frequency effect is developed 
between the gate and the dc to frequency converter and 
produces a cyclic one digit error. These early voltmeters 
allowed this phenomenon to occur, today cyclic display 
errors are unacceptable. 

A second display characteristic of these early voltmeters, 
was to use the ripple counters as the display storage, 
that is, the rippled counts would move through the 
display until the gate closed and the final value would be 
displayed. This was done primarily because of the number 
of discrete devices required to perform counting and 
latching. With the coming of integrated circuits, displays 
were improved, latches were employed, and blink-free 
displays were adopted. 



Polarity selection was made by a front panel switch 
which internally rearranged references and other cir- 
cuitry. 

An example of today's use of the VCO technique is 
shown in Figure 2. This is a low cost digital thermometer, 
which, while not a DVM, still employs the basic com- 
ponents of the voltage-controlled oscillator system. 
These are the high gain amplifiers contained in the 
LM5700, the dc-to-frequency converter consisting of the 
transistor source and LM555 timer, and the frequency- 
to-dc converter consisting of the CMOS inverters and 
reference voltage. This brings up a characteristic of 
CMOS most useful in DVM's and other anaiog-to- 
digital converters, the ability to switch directly to the 
supply and ground without offsets. In this case the 
fixed width negative-going pulses, when filtered, produce 
a feedback voltage directly proportional to the number 
of pulses— frequency-to-dc conversion. 

The early counter storage display system previously 
mentioned, is shown in Figure 3. Because the best 
display available was the gaseous tube, no attempt was 
made to blank displays during the counting period. 
When the gate closed, the counters had reached a 
certain count and these counts were displayed. 

After the development of the integrated circuit, displays 
took on a configuration as in Figure 4. Between the 
counters and display, latches were placed to display 
previous data while new counts were accumulated. The 
cost and pack count of this scheme made another 
display technique popular, that of multiplexing. 

Briefly, this technique consists of connecting, sequen- 
tially, each of the latches to a single decoder driver 
which drove the display digit which corresponded to 
that latch. When sequenced at a 50 Hz rate or greater, a 
flicker-free display results. For this type of display 
system, TRI-STATE® counter-latches were developed 
(Figure 5). This technique is still used today in many 
DVM's. 





DC TO 
FREQ, 




f fi \t IN 




2T 




J 






Vref 

T 








FREQ. TO 
DC 




k 






GATE 
SIGNAL 



I 1 i | I I j I I I I I fr-L- 



FIGURE 1. Basic VCO Scheme 



5-36 



V a TEMP 




5^ 



r.^LJ^ - i_r 



x 




<<H<1- 



■"LT" 



FIGURE 2. Typical VCO Circuit 



iate — 1 J 





DECAOE 










DECADE 










DECADE 








DECAOE 






COUNTER 




COUNTER 




COUNTER 




COUNTER 












































DECODE 
DRIVE 




OECOOE 
OfllVE 




DECODE 
DRIVE 




DECODE 
DRIVE 




















































GASEOUS 
DISPLAY 




GASEOUS 
DISPLAY 




GASEOUS 
DISPLAY 




GASEOUS 
DISPLAY 





FIGURE 3. Early Display Configuration 























































































LATCH 




LATCH 




LATCH 




LATCH 




































DECODER 
DRIVER 




DECODER 
DRIVER 




DECODER 
DRIVER 




DEC 
DR 


DER 

VER 









































ISPLAY 






DISPLAY 




DISPLAY 




DISPLAY 





FIGURE 4. Integrated Circuit Display 



537 



in 

LA 



DECODER 
DRIVER 



MULTIPLEX 
CONTROL 



FIGURE 5. Multiplexed Display 



While multiplexing cuts display costs considerably, the 
series connection of counters required to accumulate the 
counts proportional to voltage, could not be multi- 
plexed to do the very nature of VCO or dual slope 
voltmeter schemes. 

The recirculating remainder circuitry to be discussed 
next is unique in that the data is both derived and 
displayed on multiplexed, that is sequential digit basis 
(as seen in Figure 6.) 

The technique used in the recirculating remainder 
circuit is to subtract digit valued voltage steps from the 
input voltage, until ten times the difference between 
these two voltages is less than ten times the digit valued 
steps. The number of voltage steps required is the 
display data and the ten times the difference voltage 
becomes the new voltage input for the next digit 
conversion. An example is shown in Figure 7. 

An analog input of 6.903V is applied to the [(V| N - 
Vstep) x 10] amplifier. The -H2 and decade counters 
are clocked simultaneously until a (difference x 10) less 
than V REF is detected by the comparator. At this time, 
the decade counter stops counting. In this example, the 
decade counter ceases counting on a six during the digit 
one period, thus a six is latched in the display. When the 
digit period ends, both counters are reset and the 
(difference x 10) voltage is recirculated via the CMOS 
switch and sample and hold capacitor to become the 
digit two input voltage (9.03V). The process is then 



repeated for the next digit. At a repetition rate of 50 Hz 
or greater, this produces a flicker-free, blink-free display. 
As such the recirculating remainder system has but one 
counter, one latch, and one decoder driver for as many 
digits as are desired. Once again CMOS is used for its 
capability to swing directly to the supply rail and con- 
trols the R-2R ladder directly from the reference voltage. 

Some disadvantages of the system are the difficulties in 
reading voltages of both polarities and an unusual sort 
of error characteristic when slight ladder or reference 
drifts occur. While both VCO and dual slope techniques 
have gradual slope or linearity errors, the recirculating 
remainder errors are step-like in response to gradual input 
voltage changes. Lastly, the update rate is fixed by 
display flicker requirements and thus measurements of 
noisy voltages cause an annoying inability to read the 
last digits. It was however, an accurate low-cost technique 
used successfully in pre-LSI digital voltmeters. 

The most widely used system for analog-to-digital 
conversion is the dual slope circuit. The basic dual slope 
system appears in Figure 8. Assuming the integrator 
output at zero when V x is applied, the integrator 
begins to ramp with an output voltage V = \ x t/C 
where l x = — V x /R. Simultaneously with the beginning 
of this ramping, counts from an oscillator are fed into 
the display counters. At some fixed time, usually 
counter overflow, V x would be disconnected and the 
reference voltage connected to the resistor. The integra- 
tor now ramps at V - l REF t/C where l REF = V REF /R. 



5-38 



!| SWITCH B 



1 



rcH E 

I O.P. 1 



CLK 
V RFF ENABLE 



-J-*A/V-< 



I 2R 




O'JT = (V, N ■ V STt( .) X 10 



-^WV- 



2R 




| S¥VI ILN U — 



T 



DECODE 

DRiVE 



LATCH BLANK 






-►DIGITIZING PERI0D4 



-AAAr- 



FIGURE 6. Basic Recirculating Remainder System 





[\ 




69,03 


~L 9Q3 


l_ 30 


3.n 




"L 


L, REMAINDER 


l-i REMAINDER 

XT- 


REMAINDER 

1 3D.BV 

-Ur- 




\ 



OUTPUT OF IV, N - V STEP ) X 10 AMP 



Example: (Voltage in = 6.903V) 

6 1.000V steps-display 6 



6.903 
6.000 

0.903 i 10' 9.03 



y 



v^ 



9.030 
-9.000 

0.03 x 10 = 0.3 



9 1.000V steps-display 9 



DIGITIZE 


DIGITIZE 


DIGITIZE 


DIGITIZE 


DIGITIZE 


DIGIT 1 


3IGIT2 


DIGIT 3 


DIGIT 4 


DIGIT ! 


DISPLAY 


DISPLAY 


DISPLAY 


DISPLAY 


DISPLAY 


DIGIT 4 


DIGIT 1 


DIGIT 2 


DIGIT 3 


DIGIT 4 


SWITCHES 


SWITCHES 


SWITCHES 


SWITCHES 


SWITCHES 


ES D 


A& C 


B & D 


AS, C 


E & D 


CLOSED 


CLOSED 


CLOSED 


CLOSED 


CLOSED 



0.300 
-0. 000 1.000V steps- display 

0.3 x 10 = 3 



3.000 
-3.000 



3 1.000V steps-display 3 



FIGURE 7. Recirculating Remainder Waveforms 



5-39 




V - -.-- 



xT REF IrepT x 



V X T I!FF - V RFF T X 



FIGURE 8. Basic Dual Slope 



When the integrator crosses the comparator threshold, 
the counters are latched to the number of counts 
accumulated from T to T x . Clearly the voltage at T REF 
was l x T REF /C and the voltage integrated from T R6F 
to T x was -I re f T x /C and these two voltages are 
equal. Therefore, 



lx T R 



REF 



V x T REF 



C 

/ref T x 



Thus, the number of counts accumulated in the display 



from T F 



to T x is proportional to the unknown 



voltage. Thus, the basic dual slope system has no gate, 
and requires stability of the R, C and count frequency 
only over one conversion period. 

The technique for insuring that the ramp begins at zero 
on each conversion cycle, is to short the capacitor with 
a switch after each conversion is made. This, of course, 
forces the integrator output to zero until the next 
conversion period begins. It is also necessary to start 
each conversion cycle synchronously with the counter 
input frequency, or cyclic display errors like that of 
the gated VCO will appear in the display. 

To measure both polarities in conventional dual slope 
systems, V REF must change in polarity. A problem 
which can occur is that bias currents which will add to 
the slope in one polarity, will subtract from the slope in 
the other. The usual solution, is to use op amps of very 
low input bias current. Also offset voltages in either the 
op amps or comparator can cause significant error 
unless carefully controlled. 

Hence, while conventional dual slope has many advan- 
tages, its use requires considerable care in op amp, and 
comparator selection. Also, the measurement of either 
polarity requires two reference voltages which are, in 
accurate systems, quite expensive. 



The MM5330 is the display and control for a modified 
dual slope system. It contains, as shown in Figure 9, the 
counters and latches, together with a multiplexing 
system to provide four digits of display with one 
decoder driver. It also provides a sign digit, either plus 
or minus, and a ten-thousand counts digit for a full 
display of ±19999. By eliminating the right-most digits 
it may also be used as a 2 1 /2 or 3 1/2 digit DVM chip. 



The basic modified dual slope system for which the 
MM5330 is designed, is shown in Figure 10. The 
integrator is now used in a non-inverting mode and is 
biased to integrate negatively for all voltages below 
V MAX . Thus, if the maximum positive voltage at V iN 
is 1.9999V, the V MAX would be set at 2.2000V. In this 
way, all voltages measured are below V MAX . This 
eliminates the need for reference switching and makes 
the system automatic polarity, with no additional com- 
ponents. Also, it can be shown that the amplifier input 
bias currents which cause the aforementioned errors in 
conventional dual slope systems, are eliminated by 
merely zeroing the display. Thus, low bias current op 
amps are not necessarily required unless a high input 
impedance is desired at V, N . 



Secondly, the use of a conventional op amp for a 
comparator, allows zeroing of all voltage offsets in both 
the op amp and comparator. This is achieved by zeroing 
the voltage on the capacitor through the use of the 
comparator as part of a negative feedback loop. During 
the zeroing period, the non-inverting input of the 
integrator is at V REF . As this voltage is within the active 
common-mode range of the integrator the loop will 
respond by placing the integrator and comparator in the 
active region. The voltage on the capacitor is no longer 
equal to zero, but rather to a voltage which is the sum 
of both the op amp and comparator offset voltages. 
Because of the intrinsic nature of an integrator, this 
constant voltage remains throughout the integrating 
cycle and serves to eliminate even large offset voltages. 



540 



DIGIT DRIVERS 



_u_ 



DECADE 

COUNTER 



r^^P^P-^ 



4 TO 1 MULTIPLEX 



CODE 
CONVERTER 



TTT 



LATCH LATCH LATCH 



FIGURE 9. Block Diagram MM5330 



^L 





ZEROING 
SWITCH 



COMPARATOR 
THRESHOLD 




ki™n 



FIGURE 10. Modified Dual Slope 



5-41 



The waveforms at the output of the integrator are as 
shown. The voltage at A is the comparator threshold 
just discussed. Simultaneously, with the opening of 
switch A, V| N is connected to the input of the inte- 
grator via switch B. The output then slews to V, N . Inte- 
gration then begins for the reference period, after which 
time, the reference voltage is again applied to the input. 
The output again slews the difference between V REF 
and V, N then integrates for the unknown period until 
the comparator threshold is crossed. At this point, the 
accumulated counts are transferred from the counters 
to the latches and zeroing begins until the next conver- 
sion interval. 

It may be obvious, however, that while we have eliminated 
several of the basic dual slope circuits disadvantages, we 
have created another— the number of counts are no 
longer proportional to V (N but rather to (V MAX -V| N ). 
In fact, when we short V, N to ground we are actually 
measuring our own 2.2000V V MAX . 

What is done in the MM5330 is to code convert the 
number of counts as shown in Figure 11. This chart 
shows a code conversion starting at the time of a reset. 
The first 18,000 counts are the reference period after 
which time the integrator changes slope. If a comparator 
crossing is detected within the next 2000 counts, a plus 
overrange condition will occur at the display. This 
condition results in a lit plus sign, a lit one and four 
blanked right-most digits. A transfer at 20,000, however, 
will create a reading of +1.9999, at 20,001 a reading of 
19,998 and so on, until at 40,000 a reading of +0000 
would be displayed. A transfer occuring at 40,001 
would cause a -0001 display and so on until 60,000 
counts were entered at which time a -1 with four 
blanked zeros would be displayed indicating a minus 
overrange condition. 



A typical circuit for a low cost 4 1/2 digit circuit is 
shown in Figure 12. The display interface used is a TTL, 
seven-segment decoder driver and four FNP transistors. 
The ±1 digit is driven directly by CMOS. The clock- 
synchronous reset and transfer functions prevent any 
cyclic digit variations and present a blink-free flicker-free 
display. CMOS analog switches are used as reference, 
zero, and input switches and used also in a comparator 
slew rate circuit. 



A problem with all dual slope systems occurs when short 
integrating times and high clock frequencies are used. 
Because of the very slow rise time of the rarnp into the 
comparator, the output of the comparator will normally 
ramp at approximately 1/10 of its actual slew rate. Thus 
a significant number of extra counts are displayed due 
to the slow rate of rise of the comparator. A technique 
to improve this consists of capacitor C s and analog 
switch section four. An unstable positive loop is created 
by this capacitor when the comparator comes out of 
saturation. This causes the output to rise at its slew rate 
to the comparator threshold. As soon as this threshold is 
reached the analog switch opens and zeroing is initiated 
as previously discussed. 



The rapid improvement in display and LSI technology 
has allowed considerable improvement in digital volt- 
meters. The modified dual slope technique together 
with the simplified display interface of the MM5330 are 
felt to be a much improved technique when compared 
to circuits of just a short time ago. While DVM chips do 
not by themselves solve all inherent problems, their 
careful use allows low cost, high accuracy units, with 
excellent display characteristics. 



COUNTS AFTER 
RESET 






DISPLAY 









+ 1 


18,000 














+1 


19,999 








20,000 






+19999 


20,001 






+19998 


40,000 






+ 0000 


40,001 






- 0001 


59,999 






-19999 


60,000 






-1 


FIGURE 11. 


Code 


Conversion Table 


MM5330 



5-42 



i5£ 



o — v^v- 

2.2000V 




— ♦ — wv •— 




> 

Z 

i 

w 



-V MAX (ZERO ADJUST) 




X. 



^ 



C=H 



-tHh 



HK> — ^ 




-x^ 



;r^ 



TRANSFER 
RESET 



100 pF I 

O.VFd 

T 



NSN71 

LED 

DISPLAY 



NSN71 

LED 

DISPLAY 



o_A ^JT\ <^A 



NSN71 

LED 

DISPLAY 



FIGURE 12. Typical Application MM5330 



5-43 




Analog to Digital (A/D) Converters 



SPECIFYING A/D AND D/A CONVERTERS 



The specification or selection of analog-to-digital (A/D) 
or digital-to-anaiog (D/A) converters can be a chancey 
thing unless the specifications are understood by the 
person making the selection. Of course, you know you 
want an accurate converter of specific resolution; but 
how do you insure that you get what you want? For 
example, 1 2 switches, 1 2 arbitrarily valued resistors, and 
a reference will produce a 12-bit DAC exhibiting 12 
quantum steps of output voltage. In all probability, the 
user wants something better than the expected perfor- 
mance of such a DAC. Specifying a 12-bit DAC or an 
ADC must be made with a full understanding of accuracy, 
linearity, differential linearity, monotonicity, scale, gain, 
offset, and hysteresis errors. 

This note explains the meanings of and the relationships 
between the various specifications encountered in A/D 
and D/A converter descriptions. It is intended that the 
meanings be presented in the simplest and clearest 
practical terms. Included are transfer curves showing the 
several types of errors discussed. Timing and control 
signals and several binary codes are described as they 
relate to A/D and D/A converters. 

MEANING OF PERFORMANCE SPECS 

Resolution describes the smallest standard incremental 
change in output voltage of a DAC or the amount of 
input voltage change required to increment the output of 
an ADC between one code change and the next adjacent 
code change. A converter with n switches can resolve 1 
part in 2 n . The least significant increment is then 2" n , or 
one least significant bit (LSB). In contrast, the most 
significant bit (MSB) carries a weight of 2 _1 . Resolution 
applies to DACs and ADCs, and may be expressed in 
percent of full scale or in binary bits. For example, an 
ADC with 12-bit resolution could resolve 1 part in 2 12 
(1 part in 4096) or 0.0245% of full scale. A converter 
with 10V full scale could resolve a 2.45mV input change. 
Likewise, a 1 2-bit DAC would exhibit an output voltage 
change of 0.0245% of full scale when the binary input 
code is incremented one binary bit (1 LSB). Resolution 
is a design parameter rather than a performance specifi- 
cation; it says nothing about accuracy or linearity. 



Accuracy is sometimes considered to be a non-specific 
term when applied to D/A or A/D converters. A linearity 
spec is generally considered as more descriptive. An 
accuracy specification describes the worst case deviation 
of the DAC output voltage from a straight line drawn 
between zero and full scale; it includes all errors. A 
12-bit DAC could not have a conversion accuracy better 
than ±Vz LSB or ±1 part in 21^+1 (+0.0122% of full 
scale due to finite resolution). This would be the case in 
figure 1 if there were no errors. Actually, ±0.0122% FS 
represents a deviation from 100% accuracy; therefore 
accuracy should be specified as 99.9878%. However, 
convention would dictate 0.0122% as being an accuracy 
spec rather than an inaccuracy (tolerance or error) spec. 

Accuracy as applied to an ADC would describe the 
difference between the actual input voltage and the full- 
scale weighted equivalent of the binary output code; 
included are quantizing and all other errors. If a 12-bit 
ADC is stated to be ±1 LSB accurate, this is equivalent 
to ±0.0245% or twice the minimum possible quantizing 
error of 0.0122%. An accuracy spec describes the 
maximum sum of all errors including quantizing error, 
but is rarely provided on data sheets as the several errors 
are listed separately. 




000 001 010 011 100 101 no in 
DIGITAL CODE 



FIGURE 1. Linear DAC Transfer Curve Showing Minimum 
Resolution Error and Best Possible Accuracy 



5-44 



Quantizing Error is the maximum deviation from a 
straight line transfer function of a perfect ADC. As, by 
its very nature, an ADC quantizes the analog input into 
a finite number of output codes, only an infinite 
resolution ADC would exhibit zero quantizing error. A 
perfect ADC, suitably offset Y 2 LSB at zero scale as 
shown in figure 2, exhibits only +V2 LSB maximum 
output error. If not offset, the error will be +0 LSB as 
shown in figure 3. For example, a perfect 12-bit ADC 
will show a ±% LSB error of ±0.0122% while the 
quantizing error of an 8-bit ADC is ±V 2 part in 2^ or 
±0.195% of full scale. Quantizing error is not strictly 
applicable to a DAC; the equivalent effect is more 
properly a resolution error. 




ooi 010 oil 100 101 110 111 

DIGITAL CODE 




ANALOG INPUT 



FIGURE 2. ADC Transfer Curve, J4 LSB Offset at Zero 



FIGURE 4. Linear, 1 LSB Scale Error 

Gain Error is essentially the same as scale error for an 
ADC. In the case of a DAC with current and voltage 
mode outputs, the current output could be to scale 
while the voltage output could exhibit a gain error. The 
amplifier feedback resistors would be trimmed to correct 
the gain error. 

Offset Error (zero error) is the output voltage of a DAC 
with zero code input, or it is the required mean value of 
input voltage of an ADC to set zero code out. (See 
figure 5.) Offset error is usually caused by amplifier or 
comparator input offset voltage or current; it can usually 
be trimmed to zero with an offset zero adjust potentio- 
meter external to the DAC or ADC. Offset error may be 
expressed in % FS or in fractional LSB. 





. LSa _^uuu J 



000" 001 010 Oil 100 101 110 111 



ANALOG INPUT 



DIGITAL CODE 



FIGURE 3. ADC Transfer Curve, No Offset 



FIGURE 5. Linear, 7 2 LSB Offset Error 



Scale Error (full scale error) is the departure from design 
output voltage of a DAC for a given input code, usually 
full-scale code. (See figure 4.) In an ADC it is the depar- 
ture of actual input voltage from design input voltage for 
a full-scale output code. Scale errors can be caused by 
errors in reference voltage, ladder resistor values, or 
amplifier gain, et at. (See Temperature Coefficient.) 
Scale errors may be corrected by adjusting output 
amplifier gain or reference voltage. If the transfer curve 
resembles that of figure 7, a scale adjustment at % scale 
could improve the overall ± accuracy compared to an 
adjustment at full scale. 



Hysteresis Error in an ADC causes the voltage at which a 
code transition occurs to be dependent upon the direction 
from which the transition is approached. This is usually 
caused by hysteresis in the comparator inside an ADC. 
Excessive hysteresis may be reduced by design; however, 
some slight hysteresis is inevitable and may be objec- 
tionable in converters if hysteresis approaches 14 LSB. 

Linearity, or, more accurately, non-linearity specifica- 
tions describe the departure from a linear transfer curve 
for either an ADC or a DAC. Linearity error does not 
include quantizing, zero, or scale errors. Thus, a specif i- 



5-45 



cation of ±14 LSB linearity implies error in addition to 
the inherent ±14 LSB quantizing or resolution error. In 
reference to figure 2, showing no errors other than 
quantizing error, a linearity error allows for one or more 
of the steps being greater or less than the ideal shown. 

Figure 6 shows a 3-bit DAC transfer curve with no more 
than ±14 LSB non-linearity, yet one step shown is of zero 
amplitude. This is within the specification, as the maxi- 
mum deviation from the ideal straight line is ±1 LSB 
{14 LSB resolution error plus 14 LSB non-linearity). With 
any linearity error, there is a differential non-linearity 
(see below). A ±14 LSB linearity spec guarantees 
monotonicity (see below) and < ±1 LSB differential non- 
linearity (see below). In the example of figure 6, the 
code transition from 100 to 101 is the worst possible 
non-linearity, being the transition from 1 LSB high at 
code 100 to 1 LSB low at 110. Any fractional non- 
linearity beyond ±14 LSB will allow for a non-monotonic 
transfer curve. Figure 7 shows a typical non-linear curve; 
non-linearity is 1% LSB yet the curve is smooth and 
monotonic. 




000 001 010 Oil 100 101 110 111 
DIGITAL CODE 



Differential Non-Linearity indicates the difference be- 
tween actual analog voltage change and the ideal (1 LSB) 
voltage change at any code change of a DAC. For 
example, a DAC with a 1.5 LSB step at a code change 
would be said to exhibit 14 LSB differential non- 
linearity (see figures 6 and 7). Differential non-linearity 
may be expressed in fractional bits or in % FS. 

Differential linearity specs are just as important as lin- 
earity specs because the apparent quality of a converter 
curve can be significantly affected by differential non- 
linearity even though the linearity spec is good. Figure 6 
shows a curve with a ±14 LSB linearity and ±1 LSB 
differential non-linearity while figure 7 shows a curve 
with +1% LSB linearity and ±14 LSB differential non- 
linearity. In many user applications, the curve of figure 7 
would be preferred over that of figure 6 because the 
curve is smoother. The differential non-linearity spec 
describes the smoothness of a curve; therefore it is of 
great importance to the user. A gross example of differ- 
ential non-linearity is shown in figure 8 where the 
linearity spec is ±1 LSB and the differential linearity 
spec is ±2 LSB. The effect is to allow a transfer curve 
with grossly degraded resolution; the normal 8-step curve 
is reduced to 3 steps in figure 8. Similarly, a 16-step 
curve (4-bit converter) with only 2 LSB differential non- 
linearity could be reduced to 6 steps (a 2.6-bit conver- 
ter?). The real message is, "Beware of the specs." 
Do not ignore or omit differential linearity character- 
istics on a converter unless the* linearity spec is tight 
enough to guarantee the desired differential linearity. As 
this characteristic is impractical to measure on a produc- 
tion basis, it is rarely, if ever, specified, and linearity is 
the primary specified parameter. Differential non-linear- 
ity can always be as much as twice the non-linearity, but 
no more. 



''6 LSB Non-Linearity (Implies 1 LSB Possible 
Error), 1 LSB Differential Non-Linearity (Implies 
Monotonicity) 



FS 


V* LSB DIFF 

NON-LINEAR - ^ J^7 




\ rV 




Vi LSB DIFF TT^\ ' 
N0.N LINEAR \ yA LSB 




/ 1 A^ h LSB 




/F/j^LSB 




Y/ Wlsb 



000 001 010 Oil 100 101 110 111 
DIGITAL CODE 





/ 


2 LSB 

NON 

/ 


DIFF 

INEAR / 

/ 


Y 

\ 3 LSB 


, 


3 LSB L 


LSB DIFF 
ON LINEAR 



000 001 010 011 100 101 
DIGITAL CODE 



FIGURE 8. ±1 LSB Linear, ±2 LSB Differential Non-Linear 



FIGURE 7. 1% LSB Non-Linear, 1 / a LSB Differential Non- 
Linearity 



Linearity specs refer to either ADCs or to DACs, and do 
not include quantizing, gain, offset, or scale errors. 
Linearity errors are of prime importance along with 
differential linearity in either ADC or DAC specs, as all 
other errors (except quantizing, and temperature and 
long-term drifts) may be adjusted to zero. Linearity 
errors may be expressed in % FS or fractional LSB. 



Monotonicity. A monotonic curve has no change in sign 
of the slope; thus all incremental elements of a mono- 
tonically increasing curve will have positive or zero, but 
never negative slope. The converse is true for decreasing 
curves. The transfer curve of a monotonic DAC will 
contain steps of only positive or zero height, and no 
negative steps. Thus a smooth line connecting all output 
voltage points will contain no peaks or dips. The transfer 
function of a monotonic ADC will provide no decreasing 
output code for increasing input voltage. 



5-46 



Figure 9 shows a non-monotonic DAC transfer curve. 
For the curve to be non-monotonic, the linearity error 
must exceed ±Vi LSB no matter by how little. The 
greater the linearity error, the more significant the 
negative step might be. A non-monotonic curve may not 
be a special disadvantage in some systems; however, it is 
a disaster in closed-loop servo systems of any type 
(including a DAC-controlled ADC). A ±Y 2 LSB maximum 
linearity spec on an n-bit converter guarantees mono- 
tonicity to n bits. A converter exhibiting more than ±14 
LSB non-linearity may be monotonic, but is not 
necessarily monotonic. For example, a 12-bit DAC with 
±Vz bit linearity to 10 bits (not ±V* LSB) will be mono- 
tonic at 10 bits but may or may not be monotonic at 12 
bits unless tested and guaranteed to be 1 2-bit monotonic. 




(a) Full-Scale Step 



'/, LSB C 


IFF 




NON-LINEAR 


X 




\/ 










i 




% LSB 


iv I P 


I'lsbi 1 




LSB] J ' 


V. 






V, LSB D 


FF 



ooo ooi oio on ioo 101 no m 

DIGITAL CODE 



lOmV/DIV 




1 1 1 I 
CONTROL LOGIC 




|| 


















1 
DAC OUTPUT 








r 












~± 


h 


SETTLING TIME ■ 




i 




1 






















III 




Iais/DIV 







FIGURE 9. Non-Monotonic (Must be > ±Vi LSB Non-Linear) 



(b) 1 LSB Step 
FIGURE 10. DAC Slew and Settling Time 



Settling Time is the elapsed time after a code transition 
for DAC output to reach final value within specified 
limits, usually ±% LSB. (See also Conversion Rate below.) 
Settling time is often listed along with a slew rate 
specification; if so, it may not include slew time. If no 
slew rate spec is included, the settling time spec must be 
expected to include slew time. Settling time is usually 
summed with slew time to obtain total elapsed time for 
the output to settle to final value. Figure 10 delineates 
that part of the total elapsed time which is considered to 
be slew and that part which is settling time. It is 
apparent from this figure that the total time is greater 
for a major than for a minor code change due to 
amplifier slew limitations, but settling time may also be 
different depending upon amplifier overload recovery 
characteristics. 

Slew Rate is an inherent limitation of the output 
amplifier in a DAC which limits the rate of change of 
output voltage after code transitions. Slew rate is usually 
anywhere from 0.2 to several hundred vo!ts//is. Delay in 
reaching final value of DAC output voltage is the sum of 
slew time and settling time as shown in figure 10. 

Overshoot and Glitches occur whenever a code transition 
occurs in a DAC. There are two causes. The current 
output of a DAC contains switching glitches due to 
possible asynchronous switching of the bit currents 
(expected to be worst at half-scale transition when all 



bits are switched). These glitches are normally of 
extremely short duration but could be of Vt scale 
amplitude. The current switching glitches are generally 
somewhat attenuated at the voltage output of the DAC 
because the output amplifier is unable to slew at a very 
high rate; they are, however, partially coupled around 
the amplifier via the amplifier feedback network and 
seen at the output. The output amplifier introduces 
overshoot and some non-critically damped ringing which 
may be minimized but not entirely eliminated except at 
the expense of slew rate and settling time. 

Temperature Coefficient of the various components of a 
DAC or ADC can produce or increase any of the several 

errors as the operating temperature varies. Zero scale 
offset error can change due to the TC of the amplifier 
and comparator input offset voltages and currents. Scale 
error can occur due to shifts in the reference, changes in 
ladder resistance or non-compensating RC product shifts 
in dual-slope ADCs, changes in beta or reference current 
in current switches, changes in amplifier bias current, or 
drift in amplifier gain-set resistors. Linearity and mono- 
tonicity of the DAC can be affected by differential 
temperature drifts of the ladder resistors and switches. 
Overshoot, settling time, and slew rate can be affected 
by temperature due to internal change in amplifier gain 
and bandwidth. In short, every specification except 
resolution and quantizing error can be affected by 
temperature changes. 



5-47 



Long-Term Drift, due mainly to resistor and semicon- 
ductor aging can affect all those characteristics which 
temperature change can affect. Characteristics most 
commonly affected are linearity, monotonicity, scale, 
and offset. Scale change due to reference aging is usually 
the most important change. 

Supply Rejection relates to the ability of a DAC or ADC 
to maintain scale, offset, TC, slew rate, and linearity 
when the supply voltage is varied. The reference must, of 
course, remain constant unless considering a multiplying 
DAC. Most affected are current sources (affecting 
linearity and scale) and amplifiers or comparators 
(affecting offset and slew rate). Supply rejection is 
usually specified only as a % FS change at or near full 
scale at 25° C. 

Conversion Rate is the speed at which an ADC or DAC 
can make repetitive data conversions. It is affected by 
propagation delay in counting circuits, ladder switches 
and comparators; ladder RC and amplifier settling times; 
amplifier and comparator slew rates; and integrating time 
of dual-slope converters. Conversion rate is specified as a 
number of conversions per second, or conversion time is 
specified as a number of microseconds to complete one 
conversion (including the effects of settling time). Some- 
times, conversion rate is specified for less than full 
resolution, thus showing a misleading (high) rate. 

Clock Rate is the minimum or maximum pulse rate at 
which ADC counters may be driven. There is a fixed 
relationship between the minimum conversion rate and 
the clock rate depending upon the converter accuracy 
and type. All factors which affect conversion rate of an 
ADC limit the clock rate. 

Input Impedance of an ADC describes the load placed 
on the analog source. 

Output Drive Capability describes the digital load driving 
capability of an ADC or the analog load driving capacity 
of a DAC; it is usually given as a current level or a voltage 
output into a given load. 

CODES 

Several types of DAC input or ADC output codes are in 
common use. Each has its advantages depending upon 
the system interfacing the converter. Most codes are 
binary in form; each is described and compared below. 

Natural Binary (or simply Binary) is the usual 2 n code 

with 2, 4, 8, 16 2 n progression. An input or output 

high or "1" is considered a signal, whereas a "0" is 
considered an absence of signal. This is a positive true 
binary signal. Zero scale is then all "zeros" while full 
scale is all "ones." 

Complementary Binary (or Inverted Binary) is the 
negative true binary system. It is identical to the binary 
code except that all binary bits are inverted. Thus, zero 
scale is all "ones" while full scale is all "zeros." 

Binary Coded Decimal (BCD) is the representation of 
decimal numbers in binary form. It is useful in ADC 
systems intended to drive decimal displays. Its advantage 
over decimal is that only 4 lines are needed to represent 
10 digits. The disadvantage of coding DACs or ADCs in 
BCD is that a full 4 bits could represent 16 digits while 
only 10 are represented in BCD. The full-scale resolution 
of a BCD coded system is less than that of a binary 



coded system. For example, a 12-bit BCD system has a 
resolution of only 1 part in 1000 compared to 1 part in 
4096 for a binary system. This represents a loss in 
resolution of over 4:1 . 

Offset Binary is a natural binary code except that it is 
offset (usually % scale) in order to represent negative and 
positive values. Maximum negative scale is represented to 
be all "zeros" while maximum positive scale is represented 
as all "ones." Zero scale (actually center scale) is then 
represented as a leading "one" and all remaining "zeros." 
The comparison with binary is shown in figure 1 1. 

Twos Complement Binary is an alternate and more 
widely used code to represent negative values. With this 
code, zero and positive values are represented as in 
natural binary while all negative values are represented 
in a twos complement form. That is, the twos comple- 
ment of a number represents a negative value so that 
interface to a computer or microprocessor is simplified. 
The twos complement is formed by complementing each 
bit and then adding a 1; any overflow is neglected. The 
decimal number -8 is represented in twos complement 
as follows: start with binary code of decimal 8 (off 
scale for ± representation in 4 bits so not a valid code in 
the ± scale of 4 bits) which is 1000; complement it to 
0111; add 0001 to get 1 000. The comparison with offset 
binary is shown in figure 11. Note that the offset binary 
representation of the ± scale differs from the twos 
complement representation only in that the MSB is 
complemented. The conversion from offset binary to 
twos complement only requires that the MSB be inverted. 




ANALOG SCALE 



(a) Zero to + Full-Scale 



Oil 
010 


Oil 
010 


111 

110 










1 


s~ 


001 


001 


101 










rJ 




000 


000 


100 


-'/■ 


-V, 


-V. 


«i 


', 




100 








I' 1 




*v, +•/. 


101 


111 


011 




1 




I 






110 

111 


110 
101 
100 


010 
001 
000 


V 


_J 











* k '-OFFSEt BINARY 

tWOS COMPLEMENt BINARY 
SIGN + MAGNItUOE 



(b) ± Full-Scale 



FIGURE 11. ADC Codes 



5-48 



Sign Plus Magnitude coding contains polarity information 
in the MSB (MSB = 1 indicates a negative sign); all 
other bits represent magnitude only. This code is com- 
pared to offset binary and twos complement in figure 1 1 . 
Note that one code is used up in providing a double 
code for zero. Sign plus magnitude code is used in 
certain instrument and audio systems; its advantage is 
that only one bit need be changed for small scale changes 
in the vicinity of zero, and plus and minus scales are 
symmetrical. A DVM might be an example of its use. 

CONTROL 

Each ADC must accept and/or provide digital control 
signals telling it and/or the external system what to do 
and when to do it. Control signals should be compatible 
with one or more types of logic in common use. Control 
signal timing must be such that the converter or con- 
nected system will accept the signals. Common control 
signals are listed below. 

Start Conversion (SC) is a digital signal to an ADC which 
initiates a single conversion cycle. Typically, an SC signal 
must be present at the fall (or rise) of the clock waveform 
to initiate the cycle. A DAC needs no SC signal; however, 
such could be provided to gate digital inputs to a DAC. 

End of Conversion (EOC) is a digital signal from an ADC 
which informs the external system that the digital output 



data is valid. Typically, an EOC output can be connected 
to an SC input to cause the ADC to operate in continu- 
ous conversion mode. In non-continuous conversion 
systems, the SC signal is a command from the system to 
the ADC. A DAC does not supply an EOC signal. 

Clock signals are required or must be generated within 
an ADC to control counting or successive approximation 
registers. The clock controls the conversion speed within 
the limitations of the ADC. DACs do not require clock 
signals. 

CONCLUSION 

Once the user has a working knowledge of DAC or ADC 
characteristics and specifications, he should be able to 
select a converter to suit a specific system need. The 
likelihood of overspecification, and therefore an un- 
necessarily high cost, is likewise reduced. The user will 
also be aware that specific parameters, test conditions, 
test circuits, and even definitions may vary from 
manufacturer to manufacturer. For practical production 
reasons, parameters may not be tested in the same 
manner for all converter types, even those supplied by 
the same manufacturer. Using information in this note, 
the user should, however, be able to sort out and under- 
stand those specifications (from any manufacturer) 
pertinent to his needs. 



5-49 



■ 




SECTION 6 

COMMUNICATIONS/CB 
RlDlOCIRCUltS 




Communications/CB Radio Circuits 



MM5303 universal fully asynchronous 
general description 

The MM5303 is a fully asynchronous receiver/transmit- 
ter, fabricated with National's metal-gate, depletion load, 
PMOS technology. All inputs and outputs are fully TTL 
compatible, requiring no external resistors or level 
shifting. 

This device is a programmable interface between an 
asynchronous serial data channel and a parallel data 
channel. The transmitter section converts parallel 
data into a serial word which includes: start bit, data, 
parity bit (if selected), and stop bit(s). The receiver 
converts a serial word of the same format into a par- 
allel one and automatically checks start bit, parity (if 
selected), and stop bit(s). 

Both transmitter and receiver are doubly buffered; in 
addition, received data out and status words may be 
TRI-STATED, facilitating bus configurations. 

Status conditions are: transmission complete, Tx buffer 
register empty, Rx data available, parity error, framing 
error, and over-run error. 

The MM5303 is fully programmable. It can operate 
full or half duplex, transmitting and receiving simulta- 
neously at different baud rates; word length may be 5, 
6, 7 or 8 bits; parity generation/checking may be even, 
odd or inhibited; the number of stop bits may be either 
1 or 2, with 1 1/2 bits when transmitting a 5 bit code. 



features 

■ Low power 

■ High speed 



receiver/transmitter 



Fully externally programmable: 

Word length 

Parity mode 

Number of stop bits 
Fully double buffered eliminating need for precise 
synchronization 
Full or half duplex operation 
Direct TTL/DTL compatibility 

Automatic data received/transmitted status genera- 
tion 

TRI-STATE outputs 

Automatic start bit generation/verification 
Internal pull-ups on all inputs 



applications 

■ Peripherals 

■ Terminals 

■ Mini computers 

■ Facsimile transmission 

■ Modems 

■ Concentrators 

■ Asynchronous data multiplexers 

■ Card and tape readers 

■ Printers 

■ Data sets 

■ Controllers 

■ Keyboard encoders 

■ Remote data acquisition systems 

■ Asynchronous data cassettes 



connection diagram 



Dual-ln-Line Package 









"ss-^ 




39 


«EG — 






"»" — 




NDB 1 


b 




NDB 2 

36 


RD 8 — — 




NSB 


RD 7 




NPB 


RD 6 




CS 






TO E 


9 




32 


RD 4 




TD 7 


RD 3 — 




— TD 6 


11 






RD 2 — 

12 




TO 5 

29 


13 




28 


RPE — 




I TD3 


RFE — 




— TO 2 
2i 

— TD 1 


ROR 




IB 






SWE 




— TSO 


17 






RCP 




TEOC 


1DAR 




— TDS 


19 




22 


RDA — 






20 




21 


RSI 




MR 



Order Number MM5303N 
See Package 24 



6-2 



absolute maximum ratings (NoteD 

Voltage at Any Pin V ss - 25V/V SS + 0.3V* 

Operating Temperature Range -25 C to +70 C 

Storage Temperature Range —65 C to +150 C 

Lead Temperature (Soldering, 10 seconds) 300 C 

'Outputs should not have more than V ss — 15V 

dc electrical characteristics 



T A within operating temperature range, V ss 


= 5V ±5%, V DD = 0V, V GG = -12V 


+5% unless 


otherwise r 


oted. 




PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


V,H 


High Input Voltage Levels 


(Note 3) 


Vss-1-5 




Vss +0-3 


V 


V|L 


Low Input Voltage Levels 




VoD 




0.8 


V 


V H 


High Output Voltage Levels 


l OH = -100/jA 


2.4 






V 


Vol 


Low Output Voltage Levels 


l OL = 1.6 mA 






0.4 


V 


Iih 


High Levei Input Current Levels 


ViN=V SS 






10 


J"A 


IlL 


Low Level Input Current Levels 


V IN =0.4V, V ss = 5.25V 






1.6 


mA 


l0L 


Output Leakage Current Level 


SWE = RDE = V| H , 
0<Vqut<5V 






-1 


MA 


'os 


Output Short Circuit Current 
Level 


V OUT = 0V, (Note 4) 






25 


mA 


C|N 


Input Capacitance 


(Note 2! 












All Inputs 


V, N = V ss , f = 1 MHz 




5 


10 


pF 


OoUT 


Output Capacitance 














All Outputs 


SWE = RDE = V IH , f = 1 MHz 




10 


20 


PF 


'ss 


Power Supply Current 


All Inputs at V ss 




13 


25 


mA 


'gg 


Power Supply Current 


All Inputs at V ss 




6 


15 


mA 



ac electrical characteristics at 25c 



2 
01 

W 

o 
w 



PARAMETER 



CONDITIONS 



MIN 



UNITS 



Clock Frequency 

t PW Pulse Width 

Clock 

Master Reset 
Control Strobe 
Tx Data Strobe 
Rx Data Available Reset 

x r Coincidence Time 



Input Set Up Time 

Input Hold Time 

Output Propagation Delay to 
Low State 

Output Propagation Delay to 
High State 



RCP, TCP 
MR 
CS 
TDS 



RDAR, (Note 5) 

TDS 

CS 

TD1-TD8 

NPB, NSB, NDB, POE 

TD1-TD8 

NPB, NSB, NDB, POE 

RDE, SWE Enable to Outputs Low 
RDE, SWE Enable to Outputs High 



1 

5 

1 

300 

200 

300 

1 




300 




500 



500 



Ms 

U.S 
MS 



Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for 
Temperature Range" thev are not meant to imply that the devices should be operated at these limits. The table of "Electrical Chai 
provides conditions for actual device operation. 
Note 2: Capacitance is guaranteed by periodic testing. 
Note 3: Positive true logic notation is used: 

Logic " 1 " - most positive voltage level 

Logic "0" = most negative voltage level 
Note 4: Only one output should be shorted at a time. 
Note 5: Refer to Receiver Timing diagram for detail. 

63 



"Operating 
acteristics" 



functional block diagrams 



"""Mf@-| 

poe o — r^r- 

NSB o [7^1 

NDBI o F777V 

3B.^f 



II 1 ,1 1 , 1 I I I I I I I I I 



r 



TRANSMITTER HOLDING 

REGISTER 

I I I I I I I 



jT7 i iilii l i iTi 



58 



1, 1 ,11,1 



EMPTY DETECT 



mil i ^~ 



T©? 



■o TDS 
TBMT 




RPE RFE RDflfi ROR RDF ROB RDF RD6 RD5 RD4 RD3 RD2 RDI RD» 

NOTE ^E^ TRI STATE OUTPUT 



flow charts 



Transmitting Sequence 



Receiving Sequence 




POWER UP AND 

SET CONTROL BITS 
IND CONTROL STROBE 

CSiNOTE I) 




ANSMISSfQNOR 
IR CORRECTION 

ROUTINE 











— C STATUS 
»5\ OK / 








yvEs 






i* 






< RDA , 1 J>— ' 






jTyfS 








TRANSFER DATA 
AND PULSE ROAR 






| ,..„, 





OPERATION EXTERA 




SENSF CONTROL INPUT 

AND RECEIVE DATA 
RJTS AND A PARITY BIT 




Note 1: Control Strobe should be made only at the beginning of transmission and remain inactive during transmission. 

It may be tied high if no change is necessary. 

Note 2: The tine must stay low for 8 RCP pulses to be verified. 



Note 3: RDAR <- will cause RDA +- 0, refer to receiver timing for detail. 



6-4 



pin funct 


ions 






PIN NO. 


SYMBOL 


NAME 


FUNCTION 


1 


Vss 


Power Supply 


+5V supply 


2 


Vgg 


Power Supply 


-12V supply 


3 


Vpp 


Ground 


Ground 


4 


RDE 


Received Data Enable 


A low-level input enables the outputs (RD8-RD1 ) of the 
receiver buffer register. 


5-12 


RD8-RD1 


Receiver Data Outputs 


These are the 8 TR l-STATE data outputs enabled by RDE. 
Unused data output tines, as selected by NDB1 and NDB2, 
have a low-level output, and received characters are right 
justified, i.e., the LSB always appears on the RD1 output. 


13 


RPE 


Receiver Parity Error 


This TR l-STATE output (enabled by SWE) is at a high-level 






Output 


if the received character parity bit does not agree with the 
selected parity. 


14 


RFE 


Receiver Framing Error 


This TRI-STATE output (enabled by SWE)is at a high-level 






Output 


if the received character has no valid stop bit. 


15 


ROR 


Receiver Over Run 


This TRI-STATE output (enabled by SWE) is at a high-level 






Output 


if the previously received character is not read (RDA output 
not reset) before the present character is transferred into the 
receiver buffer register. 


16 


SWE 


Status Word Enable 


A low-level input enables the outputs (RPE, RFE, ROR, RDA, 






Input 


and TBMT) of the status word buffer register. 


17 


RCP 


Receiver Clock 


This input is a ciock whose frequency is 16 times (16X) the 


18 




Receiver Data Available 


desired receiver baud rate. 

A low-level input resets the RDA output to a low-level. 


RDAR 






Reset Input 




19 


RDA 


Receiver Data Available 


This TRI-STATE output (enabled by SWE} is at a high-level 






Output 


when an entire character has been received and transferred 
into the receiver buffer register. 


20 


RSI 


Receiver Serial Input 


This input accepts the serial bit input stream. A high-level 
(mark) to low-level (space) transition is required to initiate 
data reception. 


21 


MR 


Master Reset 


This input should be pulsed to a high-level after power turn-on. 
This sets TSO, TEOC, and TBMT to a high-level and resets RDA, 
RPE, RFE and ROR to a low-level. 


22 


T8MT 


Transmitter Buffer Empty 


This TRI-STATE output (enabled by SWE) is at a high-level 






Output 


when the transmitter buffer register is empty and 
may be loaded with new data. 


23 


TDS" 


Transmitter Data Strobe 


A low-level input strobe enters the data bits into the transmitter 






Input 


buffer register. 


24 


TEOC 


Transmitter End of 


This output appears as a high-level each time a full character is 






Character Output 


transmitted. It remains at this level until the start of transmission 
of the next character or for one full TCP period in the case of 
continuous transmission. 


25 


TSO 


Transmitter Serial Output 


This output serially provides the entire transmitted character. 
TSO remains at a high-level when no data is being transmitted. 


26-33 


TD1-TD8 


Transmitter Data Inputs 


There are 8 data input lines (strobed by TDS) available. 
Unused data input lines, as selected by NDB1 and NDB2, may 
be in either logic state. The LSB should always be placed on TD1. 


34 


cs 


Control Strobe Input 


A high-level input enters the control bits (NDB1, NDB2, NSB, 
POE and NPB) into the control bits holding register. This line 
may be strobed or hard wired to a high-level. 


35 


NPB 


No Parity Bit 


A high-level input eliminates the parity bit from being trans- 
mitted; the stop bit (s) immediately follow the last data bit. In 
addition, the receiver requires the stop bit(s) to follow imme- 
diately after the last data bit. Also, the RPE output is forced 
to a low-level, See pin 39, POE . 


36 


NSB 


Number of Stop Bits 


This input selects the number of stop bits, 1, 1 1/2, or 2 to be 
transmitted. A low-level input selects 1 stop bit; a high-level 
input selects 2 stop bits, except when 5-bit data is selected, 
then 1 1/2 stop bits will occur. 



6-5 



CO 

o 

CO 

If) 

5 



pin functions (con't) 



PIN NO. 


SYMBOL 


37-38 


NDB2, 




NDB1 



39 



TCP 



Number of Data E 
Character 



Odd/Even Parity 
Select 



Transmitter Clock 



These 2 inputs are internally decoded to select either 5, 6, 7 
or 8 data bits/ character as per the following truth table; 



NDB2 


NDB1 


data hi 


s/characte 


L 


L 




5 


L 


H 




6 


H 


L 




7 


H 


H 




8 



The logic level on this input, in conjunction with the NPB 
input, determines the parity mode for both the receiver and 
transmitter, as per the following truth table; 



NPB POE 




MODE 


L L 




odd parity 


L H 




even parity 


H X 




no parity 

X - don't care 


This input is a clock whose f 


equency is 16 times (16X) the 


desired transmitter baud 


rate 





timing diagrams 

Transmitter Timing — 8-Bit, Parity, 2 Stop Bits 

«~U u 



1 i 1 t r — i 

STAHT J DATA 1 | • • • • • . UATA 8 . PARITY i STOP 1 STGP2 



Transmitter Start-Up 



JL 



t_t 



i_r 



-■-*-'■ i.'IB BIT TIME ■-*■ 



Upon data transmission initiation, or when not 
transmitting at 100% line utilization, the start 
bit will be placed on the TSO line at the high 

to low transition of the TCP clock following 
the trailing edge of TDS. 



Receiver Timing— 8-Bit, Parity, 2 Stop Bits 



i r i r~~ 

STAHT . DATA! i *•••*! DATA S . PARIP 



' ST UP 



Resetting RDA 



S\S\ 



RDAR may go low any time after the RDA 
comes up but must stay low for at least 200 ns 
after the first clock pulse period. RDAR 
may be hard wired low, in which case RDA 
will go high and remain high for the duration of 
the positive clock pulse. 



6-6 



timing diagrams (con't) 

Data/Control Timing Diagram 



Start Bit Detect/Verify 







III 


tds 


A, / 


1 1 

SEUINVtRlFV BfGIMVtniFV 




„ 








^ 




"."3t 


-— , -; )( 


If the RSI line remains spacing for 1/2 a bit 
time, a genuine start bit is verified. Should the 


DATA INPUTS tL 
1, = 1) - 20 ns 
'SETUP 
'HDtD^O 




line return to a marking condition prior to 1/2 
a bit time, the start bit verification process 
begins again. 


CS 

'SETUP "*-j 


/ \ 

'— — ' — I'HOLOr" — 




CONTROL INPUTS )C 


- ,— x 






Output Timing Diagram 




HDE SWE \ 


r 

OU T fL T S DISABLED — 




OUTPUTS " UM 
(RD1-RD8. I'OA. 
RPE. flFE THMTi 


X 





Note: Waveform drawings not to scale for clarity. 



6-7 



CO 
CO 

m 



a 



Communications/CB Radio Circuits 



MM5393 push button telephone dialer 



general description 

The MM5393 is a monolithic metal gate CMOS integrated 
circuit which provides all logic required to convert a 
push button input to a series of pulses suitable for 
simulating a telephone dial. Storage is provided for 21 
digits, therefore, the information is retained after the 
call is completed and the number is available for redial. 
Entering a new number simply overrides the previous 
one. An interdigital pause can be externally selected 
as either 415 ms or 830 ms. A muting output is supplied 
to mute receiver noise during outpulsing, and a 600 Hz 
tone is activated every time a key is depressed. 



features 

■ 2 1 -digit storage 

■ Selectable interdigital pause 

■ Redial of last number 

■ 600 Hz tone 

■ Line powered operation 



connection diagram 



Dual-ln-Line Package 



K4 — 


U 


2 
Kl — 




3 
KZ — 




4 
KJ — 




HOOK SWITCH — 




6 
0SC J — 




7 
0SC2 — 




e 

OSC 3 — 




9 

DlftL PULSE — 





DPSELECT 
— TONE 



block diagram 



Order Number MM5393N 
See Package 20 



i___l_. 



OSC. AND 
TIMING 
CONTROL 



l'_L_L_L_. 



- rrr 

OSC 1 OSC 2 OSC 3 



6-8 



absolute maximum ratings 

Voltage at Any Pin 
Operating Temperature Range 
Storage Temperature Range 

vdd-v ss 

Lead Temperature (Soldering, 10 seconds) 



Vss~0.3V to VDD + 0-3V 

-30° C to +65°C 

-40°Cto+70°C 

6V max 

300° C 



electrical Characteristics Ta within operating temperature range, Vss = Gnd, 2V < VrjD < 5.5V 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Input Voltage Levels 












Logical "1" 




VDD-0.25 




VDD 


V 


Logical "0" 




vss 




Vss+0.25 


V 


Output Current Levels 












Dial Pulse 












Logical "1 " 


V DD = 3V, VOUT- V DD -0.5 


150 






uA 


Logical "0" 


V D D = 3V,VouT = Vss + 0.5 


150 






/jA 


Mute 












Logical "1" 


V D D = 3V, V UT = Vdd-0.5 


100 






ma 


Logical "0" 


V DD = 3V, V UT = Vss + 0.5 


100 






ma 


Tone 












Logical "1" 


V DD = 3V, V UT = V DD -0.5 


10 






ma 


Logical "0" 


V DD = 3V, V 0U T = Vss + 0.5 


10 






ma 


01,02,03 












Logical "1 " 


V DD = 3V, V 0U T = V DD -0.5 


20 






ma 


Logical "0" 


V DD = 3V, V UT = Vss + 0.5 


150 






ma 



functional description 

The time base for the MM5393 is an RC controlled 
oscillator nominally tuned to 20 kHz. This is succes- 
sively divided to provide timing signals for the various 
counters. The keyboard inputs, K1— K4, in conjunction 
with the scan counter outputs, 01—03, indicate the 
presence of a particular key depression. If only one 
key is detected for 5 ms, the decoded key will be loaded 
into the RAM. The push button inputs are accepted at 
an asynchronous rate, loaded into a first-in-first-out 
memory, and outpulsing of the correct number of 
pulses begins immediately after the first digit is entered. 
After the first digit has been completed, outpulsing will 
cease unless another key has been entered. This allows 
use in a PBX system to ensure receipt of a dial tone 
before entering the remainder of the number. If the call 
was not successful, it can be redialed at a later time by 
pressing the redial key (i). If an access code is required 
as in a PBX system, it can be entered, the dial tone can 
be established, then the redial key can be pushed. Only 
one key can be entered before pushing the redial key 
because after the second key entry, the memory is 
erased. A block diagram of the MM5393 is shown in 
Figure 1 . 



KEYPAD DATA INPUTS 

Keypad closures cause the connection of 2 of 7 switch 
contacts arranged as a matrix (shown in Figure 2). 
Key closures are protected from contact bounce for 
5 ms. 



IMPULSING MARK-TO-SPACE RATIO 

The mark-to-space ratio is 1.6:1 (61.5% to 38.5%). 

IMPULSING OUTPUT 

The number of pulses will correspond to the input 
digit. For example, key 5 will generate 5 pulses. The 
outpulsing rate is 10 Hz, and it can be varied by 
adjusting the frequency of the oscillator. Because it is 
intended to drive a transistor buffer, the outpulsing data 
is inverted. Digits are separated by an interdigital pause 
which is pin programmable for either 415 ms or 830 ms. 



6-9 



CO 
O) 
CO 

in 

5 



switching time waveforms 



KEYBOARD SCAN 



IS 



IT 



IS 



u 



u~ 



KEY CLOSURE (3)" 



i r 




I INTERDIGITAL PAUSE 
U — 415 msOR 830 ms - 
I (PIN PROGRAMMABLE) | 



Note. All times are based on a 20 kHz oscillator. 
FIGURE 1 



n_r 



keypad matrix 



U- 



-& 



-£ 



typical application 



01 02 03 

FIGURE 2 

Proposed Interface 




6-10 



sa 



Communications/CB Radio Circuits 



2 

in 

CO 



MM5395 TOUCH TONE® generator 
general description 

The MM5395 ts an integrated circuit that can provide 
all tone frequency pairs required for the TOUCH 
TONE® telephone dialing system. The output frequen- 
cies are generated by programmably dividing the 
frequency of the on-chip crystal-controlled oscillator; 
thus, accurate output frequencies can be obtained 
without tuning. The only external component needed 
for the oscillator is an inexpensive 3.579545 MHz 
crystal. 



The device has four row and four column inputs. Inputs 
to the device can either be in a 2-out-of-8 code format 
from a keyboard, or by BCD signals to the row inputs. 



Interface with single contact low-cost keypad option 

Multi-key lockout with single tone capability 

On-chip high band and low band tone generators and 

mixer 

High band pre-emphasis 

Low harmonic distortion 

Accurate tone frequencies 

Open emitter, emitter follower output 

Mute switch output 

Can be powered directly from the telephone line 



The device is fabricated using our low voltage CMOS 
process so that it may be powered directly from the 
telephone line. 

The MM5395 is designed to be used in a wide variety of 
tone signaling and data transmission applications. 

features 

■ 3V to 5V supply 

■ On-chip 3.579545 MHz crystal-controlled oscillator 

■ Interface with standard telephone keypad 



functional description 

The functional block diagram of MM5395 is shown in 
Figure 1. The device can be operated in Keypad Inter- 
face Mode or Signal Interface Mode (BCD into row 
input) depending on the logical level at "Control" 
input. In either mode, the MM5395 will digitally syn- 
thesize the high and/or low band sine waves when valid 
signals are applied to row or column inputs. The sum of 
the two sine waves is then provided at the "Tone 
Output." The base of the output NPIM transistor is 
brought out ("FILTER") for easy filtering. Operational 
functional features are summarized in tables. 



block diagram 



CONTROL - 

XMIT- 



OUT 








I 








PROGRAMMABLE DIVIDER 




osc 




4 


fc 










46 33 
42 :34 



















i 


L 
















KEYBOARD 
LOGIC 

CONTROL 
LOGIC 






' 


' 




PROGRAMMABLE DIVIDER 

BO -66 
-73 5B 






1 























WAVEFORM 
GENERATOR 



V D 
E--4 TONE 



OUTPUT 
-FILTER 



6-11 



absolute maximum ratings 

Voltage at Any Pin 
Operating Temperature Range 
Storage Temperature Range 

VDD - Vss 

Lead Temperature (Soldering, 10 seconds) 



Vss -0.3V to Vrj D + 0.3V 

-40"C to +70°C 

-65°Cto+150"C 

6V 

300° C 



electrical characteristics 

Ta within operating temperature, 3V < Vdd ~ Vss ^ 5V, unless otherwise specified. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Input Pull-Up Resistor @ Column Inputs 


ViN = Vss 


100 




400 


kU 


Input Pull-Down Resistor @ "Xmit" 


VfN "" V DD 


100 




400 


k!2 


Internal Resistor @ Row Inputs 












To VqD (Option A} 


V|N = V SS 


100 




400 


ki> 


To Vss (Option B) 


V|N = V DD 


100 




400 


k<> 


Input Voltage Levels 












Logical "1" 




VDD-0.25 




vdd 


V 


Logical "0" 




vss 




Vss+0.25 


V 


Output Voltage Swings (g> "TONE 


VDD-VsS 3,0V, 










OUTPUT" 


R L > 500U 










Low Band Only 






820 




mVp-p 


High Band Only 






1000 




mVp-p 


Harmonic Distortion 


Rl,; 500*', 

No External Fi Itering 






-20 


dB 


Tone Frequency Deviation 








1.0 


% 


Operating Frequency 






3.579545 




MHz 


Key-Down Debounce Time 






7 


11.35 


ms 


Key-Up Debounce Time 






4 


7.15 


iris 


Power Dissipation 


VDD- V S S = 6V, 
R L = 500<2 






30 


mW 


Output Current Level @ "MUTE" 


Vdd v ss = 3.ov 










Logical " 1 " 


V0UT = V DD 0.2V 


20 






AiA 


Logical "0" 


vout^ v S s + o.5v 


2.0 






mA 



functional description (Continued) 



TABLE I. Interface Mode Control 



CONTROL 


XMIT 


INTERFACE MODE 



1 
1 


Open 

1 


Keypad 

Idle ]BCD Signal 

Send tonesje.g. MM5393 



6-12 



functional description (Cominu 



ed) 



TABLE II. Keypad Interface 
(a). Functional Truth Table 



ROW 


COLUMN 


LOW BAND 


HIGH BAND 


None 


None 


DC 


DC 


One 


One 


'L 


*H 


None 


One 


DC 


fH 


One 


None 


tL 


DC 


Two or more 


None 


DC 


DC 


Two or more 


One 


DC 


fH 


None 


Two or more 


DC 


DC 


One 


Two or more 


fL 


DC 



(b). Output Frequencies 



INPUTS 


DESIRED 
FREQUENCIES 


ACTUAL 

FREQUENCY 

(Hz) 


PERCENT 
DEVIATION 


f L (Hz) 


f H (Hz) 


Rl 


697 




699.1 


0.306 


P2 


770 




766.2 


0.497 


R3 


852 




847.4 


-0.536 


R4 


941 




9480 


0.741 


CI 




1209 


1215.9 


0.569 


C2 




1336 


1331 7 


-■0.324 


C3 


- 


1477 


1471.9 


0.35 


C4 




1633 


1645.0 


0.736 



TABLE III. Functional Truth Table for Signal Interface 

















FREQUENCIES 


XMIT 


CI 


C2 


R1 


R2 


R3 


R4 


GENERATED 


f L (Hz) 


fH (Hz) 





X 


X 


X 


X 


X 


X 


DC 


DC 




Open 


Open 














941 


1336 




Open 


Open 











1 


697 


1209 




Open 


Open 








1 





697 


1336 




Open 


Open 








1 


1 


697 


14 77 




Open 


Open 





1 








770 


1209 




Open 


Open 





1 





1 


770 


1336 




Open 


Open 





1 


1 





770 


1477 




Open 


Open 





1 


1 


1 


852 


1209 




Open 


Open 


1 











852 


1336 




Open 



Open 
Open 


1 








1 


852 

'L 


14 77 
DC 












Open 







Valid BC 


D Inputs 




DC 


fH 


















DC 


DC 



6-13 



typical applications 



Standard Telephone Keypad 




TONE 
OUTPUT 



CONTROL 
OSCIN 



Hh 




V. 



I I 

COMMON SWITCHES 









0- 




[ TX J TRANSMITTER 



(REV) RECEIVER 



Df 



£f 



Df 



HOOK SWITCHES 



Single Contact Keypad 



row — \- 







£- 



6 14 



connection diagram 



Dual-ln-Line Package 



vss- 



NC — 

OSC^ 
OUT 
5 
MUTE — 

6 
C4 — 



CI — 
9 



u 





VOD 


17 


TONE 


16 


FILTER 


15 


XMIT 


14 


CONTROL 


13 


R1 



Order Number MM5395N 
See Package 20 



6 15 



a 



Communications/CB Radio Circuits 



MM55104, MM55106, MM55114, MM55116 PLL frequency synthesizer 
general description 



The MM55104 and MM55106 devices contain phase 
locked loop circuits useful for frequency synthesizer 
applications in C.B. transceivers. The devices operate 
off a single power supply and contain an oscillator, 
a 2 1u or 2 1 ' divider chain, a binary input programmable 
divider, and phase detector circuitry. The devices may 
be used in double I.F. or single I.F. systems. The 
MM55104, MM55114, MM55106 and MM55116, use a 
10.24 MHz or 5.12 MHz quartz crystal to determine the 
reference frequency. The MM55106 and MM551 16 have 
an output pin which provides a 5.12 MHz signal, which 
may be tripled for use as a reference oscillator frequency 
in two crystal systems. Also, the MM55106 provides an 
additional input to the programmable divider which 
allows 2 y — 1 division of the input frequency (F|f\j). 
The inputs to the programmable divider are standard 
binary signals. Selection of a channel is accomplished by 
mechanical switches or by external electronic program- 
ming of the programmable divider. 

The 0VCO output provides a high level voltage (sources 
current) when the VCO frequency is lower than the lock 



frequency, and 0VCO provides a low level voltage (sinks 
current) when the VCO frequency is higher than the 
lock frequency. The 0VCO output goes to a high impe- 
dance (TRI-STATE®) condition under lock conditions, 
and the lock detector output LD goes to a high state 
under lock conditions. 



features 

■ Single power supply 

■ Low power CMOS technology 

■ Binary input channel select code 

■ 5kHzor10kHz output from oscillator divide 

■ 5.12 MHz output (MM55106 and MM55116 only) 

■ On-chip oscillator 

■ Pull-down resistors on programmable divider inputs 

■ Low voltage operation-5V (MM55104, MM55106! 

■ High voltage operation-8V (MM55114, MM55116) 



block diagrams 



rREOSELECT 







OSC OUT 
I 4 




"0"- 5 kHz 
I 5 


" 


VCO ( 


UTPUT 
6 






I 




1 


10 kHz/ 
5 kHz 




3 




REFERENCE 
OSCILLATOR 




OSC DIVIDER 
2 1D OR2 11 


osc 




L 
1 




IN 










PHASE 
DETECTOR " 


_2_ 




PROGRAMMABLE DIVIDER 2 B -1 








I I I I I I I I 








[l f IB f IS 


|l4 


13 J 12 |11 J 10 |9 |3 









V cc DND P0 PI P2 P3 



LOCK 
7_ DETECTOR 
"I" tor locked 
'0" for unlocked 



REFERENCE 
OSCILLATOR 



FREQSELECT 
5.12 MHZ "1" = 10 kHz 
OUT "0" = 5 kHz 



DSC DIVIDER 
2^ OR 2^ 



PROGRAMMABLE DIVIDER 2 9 -l 



PHASE 
DETECTOR 



[1 |18 ( 17 |l6 J15 |14 [13 (12 |l1 |10 

V cc GNDP0 PI P2 P3 P4 P5 P6 P7 



LOCK 
^DETECTOR 
"1" for locked 
"0" for unlocked 



MM55104, MIVI55114 



MM55106, MM55116 



pin descriptions 



P0-P8 Programmable divider inputs 

F|fsj Frequency input from VCO (mixed 

down) 
OSC IN Oscillator amplifier input Terminal 

OSC OUT Oscillator amplifier output terminal 

LD Lock detector 

pVCO Output of phase detector for control 

of the VCO 
FS Frequency division select 10 kHz a 

5 kHz - "1" is 10 kHz; "0" is 5 kHz 
5.12 MHz OUT OSC Frequency divided by 2 outpu 



truth table 



Truth table fo 


r binary inputs to pr 


ogrammable c 


ivider. 






N 


P8 


P7 


P6 


P5 


P4 


P3 


P2 


P1 


PO 


1 


























X 


2 























1 





511 


1 


1 


1 


1 


1 


1 


1 


1 


1 



F OUT "= F )M'''N 
1 = High voltage level, Vqh 
- Low voltage level, Vq[_ 
X = Don't care 



6-16 



absolute maximum ratings 


Vcc M ax 




Voltage at Any Pin Vcc + °- 3v to Gnd - 0.3V 


MM55104, MM55106 


7V 


Operating Temperature Range —30 C to +75 C 


MM55114, MM55116 


12V 


Storage Temperature Range — 40°C to +125 C 


Lead Temperature (Soldering, 10 seconds) 


300°C 


electrical characteristics ta = 25°c 






PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Supply Voltage (Vcc) 














MM55104, MM55106 






4.5 


5.0 


5.5 


V 


MM55114, MM55116 






7.0 


8.0 


10.0 


V 


Supply Current dec) 


Freq @> Osc In = 10 MHz, 
<s> F| N = 2.5 MHz, All Oth 
I/O Pins Open, (Note 1) 


er 










MM55104, MM55106 


V C C = 5V 






3 


10 


mA 


MM55114, MM55116 


V C C = 8V 






8 


16 


mA 


Logical "1" Input Voltage (V||\|(1)) 














P0-P8, FS. F| N 






(VCC-0-4V) 






V 


Logical "0" Input Voltage (V||\|(o)) 














P0-P8, FS, Fin 










0.4 


V 


Logical "1 " Output Voltage 














5.12 MHz Out, LD 


lO = 0.5 mA 














0VCO 


lO = 0.4mA 






(VCC-0.5V) 






V 


Osc Out 


lO = 0.25mA 














Logical "0" Output Voltage 














0VCO, 5.12 MHz Out, LD 


lO = -0.5mA 1 








0.5 


V 


Osc Out 


IO = -0.25mAj 








Logical "1" Input Current 














FS (Pull-Up) 










1.0 


MA 


MM55104, MM55106 ] prj-P8 


V C C = 5V 




5 


20 


50 


ma 


MM55114, MM55116 J (Pull-Down) 


V C C = 8V 




10 


40 


100 


HA 


Logical "0" Input Current 














P0-P8 (Pull-Down) 










1.0 


MA 


MM55104, MM55106 1 

} FS (Pull-Up) 
MM55114, MM55116 J 


VCC = 5V 
Vcc = 8V 




-10 
-30 


-35 
-120 


-100 
-300 


ma 
ma 


Toggle Frequency @ F|pg 






3 






MHz 


Oscillator Frequency (9> Osc In 






10.24 






MHz 


TRI-STATE Leakage @ 0VCO 










1.0 


fiA 


Connection diagrams (Dual-ln-Line Packages, Top View) 






GND PO PI P2 P3 P4 P5 PS 


GND PO PI P2 P3 P4 P5 P6 P7 






| IE |lS |l4 |l3 |l2 |ll |ID \l 






MB ||7 |l6 |l5 |l4 [l3 |l2 |ll |l 








|, \2 |3 |. |S |. |7 |. 
V cc F, N DSC OSC FS .VC0 LD P7 
IN OUT 






|, |2 |3 |, | S |. |, |. |, 

U cc F, N OSC OSC 512 FS VC0 L0 PB 
IN OUT MHz 
OUT 






Order Number MM55104N or MM55114N 


Order Number MM55106N or MM551 16N 




See Package 19 


See Package 20 





typical applications 



INTRODUCTION TO FREQUENCY SYNTHESIS 

The components of a frequency synthesizer are shown 
in Figure 1 . The voltage controlled oscillator produces 
the desired output frequencies spaced f v Hz apart 
according to the relation: 



fv 



f r N 



The reference frequency, fr, must be equal to or less 
than the (channel) spacing between the frequencies 
being synthesized. 









I 






REFERENC 


\. 


vN 


U 


PHASE 
DETECTOR 


~ 1 












I I I I I I I I 

CHANNELSELECTCQDE 




l 






VCO 






OUTPUT) l v 




" 











FIGURE 1. Basic Frequency Synthesizer 

Although simple in concept, the circuit of Figure J has 
certain difficulties. In CB, we are synthesizing the 
following frequencies: 



Ch 1 
Ch 2 



Ch23 



26.965 
26.975 



27.225 



Although the channel spacing is 10 kHz, a reference 
frequency of 5 kHz would be necessary due to the odd 
5 kHz in the assigned channel. This in itself poses no 



problem; however, present technology limits the counting 
speed of programmable dividers to something less than 
5 MHz, ruling out the approach shown in Figure 1. 

Two solutions to this problem are shown in Figure 2. 

Frequency prescaling shown in Figure 2(a) reduces the 
VCO frequency by M (a fixed number) to a frequency 
that can be divided by the programmable counter. The 
reference frequency f r must also be reduced by M. In the 
case of CB, if M = 10, f v = 26.965 MHz, the input to the 
programmable divider will be 2.6965 MHz, and the 
5 kHz reference frequency will be reduced to 500 Hz. 
This poses problems in speed of response of the phase 
locked loop. 

The second technique mixes the output frequency of 
the VCO with a stable fixed frequency to obtain a 
related reference frequency. 

fv = Nf r + f 

This technique has the advantage of allowing a 10 kHz 
reference frequency in the loop instead of 5 kHz. 

Further complexity arises when one considers that the 
synthesizer must also generate a local oscillator signal as 
well as a transmitter input signal for the radio (Figure 3). 
A system which provides these frequencies, as well as 
the proper offset to allow the programmable divider to 
operate within its limits is shown in the typical applica- 
tions diagrams (Figure 4). The only departure from the 
ideal situation shown in Figure 3 is that the first IF 
frequency of 10.7 MHz must be changed to 10.695 MHz 
(a change of 5 kHz). 




















I 






OFFSET 
GENERATOR 


( o 


MIXER 




tN 


U 


PHASE 
DETECTOR 




* 


'v-'o 


~~ 1 
















I I I 


I I 




v -f c )/n 










f v 


VCD 














* 









T 



FIGURE 2(a). Frequency Prescaling 



FIGURE 2(b). Frequency Offset 




| 2S95S | ►[ 



FIGURE 3. Signals Needed to Transmit and Receive Ch 1 



6-18 



typical applications (con't) 

I^S. . TO RECEIVER ZND 
"I/""* MIXER 




T 



, * _J REFERENCE I J QSC0IV10ER I 

' £"^ loSCILLATQRJ * \ ?'PQR2 11 \ ~\ 

'T^ Muitciri* in ju, PHAbt 



MM5S104 ?0 



PROGRAMMABLE DIVIDER 2 B 



'r y ........ - 

4i " » in An in J,io is ,1,8 i 



T 



224 N- 260 



Js\ 2 240 - 2.&C0 MH; f " [ J ,,„„ I 

-^ _ MIXER U • j VCO U • > 

1 ™ 



3 J 35 420 MH; 



OSC MIXEfi r 



1C69SMH; | ' | 



FIGURE 4(a). MM55104 or MM55114 3-Crystal Application 



,0!, p!£{^ |_|£-. 







~*°~ i 



J\_.T0 RECEIVER 
| ^ ^2Nt] MIXER 



3 J REFERENCE |_J , L J OSC DIVIDER ! 
T^^ IOSCIELATORn ' [ ** | 2SqR2"> | H 



PROGRAMMABLE 0IV10ER 2 9 - 



ki7 aibaisAmAisA^AiiAiom 



trrju 



x 

T 



«"■">« U.3IU- 

/H 120DMH* I I 

_<" _ J MIXER M— 



XL 

r 



^i 1 

ItOREC. MIXER _L 



16 270 - lii.BGO 



FIGURE 4(b).MM55106 or MM551 16 2-Crystal, 23-Channel Application 






T 



^ I REFERENCE L J _, I JREFEHENCE DIVIDER) 

'T^ IOSOLEATORn Pi i' OB i" | 



6-19 




J* 




TO TRANSMITTER 
26 96 3 -ZJ.2Z5MH; 
TO RFT.EIVER 
1ST MIX 
16.27-16.56 MHz 



'HQGRAMMABLE DIV 2 9 -1 



12 13 14 15 16 p7 



jr~n 



XT 











SWITCH 

WAFER 

C 


III 

LI 




□ 

G 




LED 


DIS 


LAV 





CHANNEL 

SELECT 

SWITCH 



FIGURE 4(c). MM55106 or MM55116 Single Crystal, 
23-Channel Application 



2 



Communications/CB Radio Circuits 



MM55108, MM55110 PLL frequency 
general description 

The MM55108 and MM55110 PLL frequency synthe- 
sizers are monolithic metal gate CMOS integrated 
circuits which contain phase lock loop circuits useful for 
frequency synthesis applications in CB transceivers. The 
devices operate from a single power supply and contain 
an oscillator with feedback resistor, divider chain, 
a binary input programmable divider with control logic 
for the transmit mode (^ by (N + 91)), and the necessary 
phase detector logic. The devices may be used in double 
IF or single IF systems. 

Both the MM55108 and the MM551 10 use a 10.24 MHz 
quartz crystal to determine the reference frequency. 
The MM55108 has a 2'^ divider chain which generates 
a 5 kHz reference frequency. The MM551 10 has a 
selectable 2'^ or 2' ' divider chain which gives either a 
10 kHz or 5 kHz reference frequency. The selection of 
reference frequency is made by use of the FS pin. 
In addition, the MM551 10 contains an amplifier for filter 
applications and an additional input to the program- 
mable divider which allows 2 1 ^ — 1 division of the input 
frequency (f|[\j) for FM applications. Due to the internal 
amplifier stage at input frequency input (f||\|). the 
MM55108 and MM55110 may take a 1 Vp-p signal at 
f||\| as the input frequency for the programmable divider. 
Inputs to the programmable divider are standard binary 
signals. Selection of a channel is accomplished by 
mechanical switches or by external electronic program- 
ming of the programmable divider. The 0VCO output 



synthesizer with receive/transmit mode 

provides a high level voltage (sources current) when the 
0VCO frequency is lower than the lock frequency, and 
0VCO provides a low level voltage (sinks current) when 
the 0VCO frequency is higher than the lock frequency. 
The 0VCO output goes to a high impedance state 
(TRI-STATE®) while in lock mode, and the lock 
detector output LD also goes to a high state under lock 
condition. 

features 

■ Single crystal operation 

■ Single power supply 

■ Low power CMOS technology 

■ Binary input channel select code 

■ 2!0 or 2 11 divider chain from oscillator input 
(MM55110),2 11 divider chain (MM55108) 

■ Buffered 5.12 MHz and buffered 10.24 MHz outputs 

■ On-chip oscillator with bias resistor 

■ Pull-down resistors on programmable divider inputs 

■ Receive/transmit input for ^ by (N+91) while in 
transmit mode 

■ Amplifier for filter applications (MM551 10) 

■ Programmable 29 - 1 division of f | |\j 

■ Additional programmable input for 210-1 division 
of f|M (MM55110) 

■ Amplifier stage on f||\j input to accept 1Vp-p signal 



block diagrams 



i-^/W 1' 

j 5M 

i-TSo-l 



£>c-L 



SOQk 



OSCILLATOR DIVIDER 



T F 



PROGRAMMABLE DIVIDER 



17 16 15 14 13 12 11 10 9 
P1 P2 P3 R x P4 P5 P6 P7 PB 



"1" FDR 
LOCKED 
"0" FOR 
UNLOCKED 



FREQUENCY 
SELECT 
&.1ZMH; 1G.24MHz 1" 10 kHz FiLTER FILTER VCO 

OUT OUT 0"5 kHz IN OUT OUTPUT 



i—'Wv it 

5M 



|>c-^ 






> 



OSCILLATOR DIVIDER 
210 or 2*11 



PROGRAMMABLE DIVIDER 



[u | 23 ] 22 21 20 18 17 16 j 15 1 14 j 13 12 

GND PO PI P2 P3 Rv PI P5 P6 P7 P8 P9 



"1" FOR 
LOCKED 
"0" FOR 
UNLOCKED 



6-20 



absolute maximum ratings 

Voltage at Any Pin 

Operating Temperature Range 

Storage Temperature 

Operating Vqc 

Lead Temperature (Soldering, 10 seconds) 



VCC + 0.3V toGnd - 0.3V 

-30°Cto+75°C 

-40°Cto+125°C 

12V 

300° C 



electrical Characteristics Ta = 25°C, Vcc = 8V unless otherwise specified 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Supply Voltage (Vfjrj) 




4.5 




10 


V 


Supply Current (Ice! 


Freq. at Osc. In = 10.24 MHz 
atf|N = 2.5 MHz, All Other 
I/O Pins Open 




4 


10 


mA 


Logical "1" Input Voltage (V|N(1)) 
P0-P9, Is 




(VcC-0-4) 






V 


Logical "0" Input Voltage (V|[\j(o)) 
P0-P9, Is 








0.4 


V 


Logical "1 " Output Voltage 

(pVCO, 10.24 MHz Out, 5.12 MHz Out, 

Osc. Out, LD 


l(0 = -0.5 mA 


(VcxrO-5) 






V 


Logical "0" Output Voltage 

4>VCO, 10.24 MHz Out, 5.12 MHz Out, 

Osc. Out, LD 


l = 0.5 mA 






0.5 


V 


Logical "1" Input Current 
Filter In (Pull-Up) 
R X /Tx (Pull-Up) 
FS.P0-P9 (Pull-Down) 




20 


40 


1 
1 
60 


uA 
MA 
M A 


Logical "0" Input Current 
Filter In (Pull-Up) 
R S /T X (Pull-Up) 
FS, P0-P9 (Pull-Down) 




-60 


-120 


-1 

-180 
1 


M A 
piA 
uA 


Toggle Frequency at f|[\j 




3 






MHz 


Input Signal at f | |\j (Maximum 3 MHz) 


For ac Signal or 

<V|N<1)> 

<V|N(0)> 


1 
(Vcc-0-4) 




0.4 


Vpp 
V 
V 


Oscillator Frequency at Osc. In 








10.24 


MHz 


TRI-STATE Leakage at <?VCO 


v OUT = V CC or Gnd 






11. 


uA 



6-21 



connection diagrams 



Dual-ln-Line Package 

GND PI P2 PJ Rx /T X P4 ps p6 P 7 

IB 17 |lB J T 5 1 14 ||3 |l2 |ll Jl 




Order Number MM55108N 
See Package 20 



pz 



DuaMn-Line Package 

P3 NC RX'TX P4 P5 
20 19 18 17 




TOP VIEW 

Order Number MM551 ION 
See Package 22 



pin descriptions 



P0-P9 

f IN 

OSC IN 
OSC OUT 
LD 

«VCO 
FS 



Programmable Divider Inputs 5.12 MHz OUT 

Frequency Input From VCO (Mixed down) 

Oscillator Amplifier Input 10.24 MHz OUT 

Oscillator Amplifier Output 

Lock Detector FILTER IN 

Output of Phase Detector for Control of VCO FILTER OUT 

Frequency Division Select &x/ T X 

"1"for 2 10 Division 

"0" for 2 11 Division 



Buffered 5.12 MHz Output (Oscillator 

Frequency ^ By 2) 

Buffered 10.24 MHz Output (Oscillator 

Frequency) 

Filter Amplifier Input 

Filter Amplifier Output 

Receive/Transmit Input 

"0" for Transmit Mode (+ by (N+91 )) 



typical applications 




^.TxOUT 

26 9G5-27 405MH; 



v cc .ivO 



FIGURE 1. Single Crystal 40-Channel Low Side Injection with MM55108 and LM1862 



FIRST MIXER 
*-H x 0UT 

16.27 - IB 71 MHz 



6-22 



typical applications (Continued) 



X" 



I — w\» — 

5M 



{>>hL 



n 



OSCILLATOR DIVIDER 



zgk 



PROGRAMMABLE DIVIDER 



SW GMD V CC 



690666606 — 



SW OPEN ■ R x fc 



TO RECEIVER 
—►1ST MIXER 

15 27 16.71 MHz 



-x^ 



H 




I 



CHANNEL 
SELECT 
SWITCH 



1 82 < N < 270 where N = binary 
number for programmable divider 



FIGURE 2. MM55108 Single Crystal 40-Channel Low Side Injection 



X 



i- 1 



x 



i — vw — i 

5M 



|>~L- 



xa 



SW G M V c c 



VVYVVVVy?" 



ope-j ■ q x >t 

CLOSE T, \ 



J35.B4MH; 



SUFFERED 
<J 5.12 MHz 
OUT 



OSCILLATOR DIVIDER 



TO RECEIVER 
—►1ST MIXER 

36.75- 37.19 MHi 



H 



^i 



-X T X 



I 



CHANNEL 
SELECT 
SWITCH 



182 < N < 270 where N = binary 
number for programmable divider 



FIGURE 3. MM55108 Single Crystal 40-Channel High Side Injection 



623 



Hi 

in 



truth tables 



oo 
o 

2 



Channel 1 ■■* 



Channel 40 -* 



TABLE I. Binary Inputs to Programmable Divider for MM55108 



Rx/t x 


«x/Tx 


INPUTS 


28 


27 


26 


25 


2 4 


23 


22 


21 


N 


N 


P8 


P7 


P6 


P5 


P4 


P3 


P2 


PI 


1 


92 


























2 


93 























1 


4 


95 




















1 





182 


273 
















1 





1 




270 


361 


1 
















1 




510 


601 


1 






1 






1 




1 





1 - logical "1 " 
= logical "0" 



TABLE II. Binary Inputs to Programmable Divider for MM55110 



Channel 40 -+ 



Rx/Tx 


Rx/Tx 


INPUTS 


2 9 


2 8 


2? 


26 


25 


2 4 


23 


22 


21 


2 


N 


N 


P9 


P8 


P7 


P6 


P5 


P4 


P3 


P2 


P1 


P0 


1 


92 





























X 


2 


93 


























1 





3 


94 


























1 


1 


182 


273 







) 


1 





1 


1 





1 


1 





270 


361 























1 


1 





1023 


1114 


1 






1 


1 


1 


1 


1 


1 


1 


1 



X = don't care 
1 = logical "1" 
= logical "0" 



6-24 





SECTION 7 
WATCHES 










Watches 



MM5829 LED watch circuit 
general description 

The MM5829 is a low threshold voltage, ion-implanted, 
metal-gate CMOS integrated circuit that provides or con- 
trols all signals needed for a 3 1/2 digit LED watch. The 
display format is 12 hours. The circuit time base is a 
32768 Hz crystal controlled oscillator. This time base 
frequency is successively divided to provide drive signals 
for a multiplexed 7 segment LED display of either 
HOURS-MINUTES or SECONDS upon demand. Out- 
puts interface with currently available standard bipolar 
segment and digit driver integrated circuits. The device 
operates from a single 2.4V to 5.0V supply. A STOP 
MODE is provided such that an entire watch may be 
placed in a powered down state with the oscillator 
stopped when still connected to the battery. The 
MM5829 is available in a 30-lead ceramic flat package or 
as unpackaged die suitable for hybrid assembly. 



features 

■ 32768 Hz crystal controlled operation 

■ Single 3V supply 

■ Low power dissipation (15/jW typ) 

■ Seconds, minutes and hours operation 

■ 3 1/2 digit, 12 hour display format 

■ Simple display/set controls 

■ Power-down mode 

■ Easy interface to standard bipolar IC's for display 
drive 



block diagram 



chip pad layout 



;r2rn 



1096 Hz TEST 1 Hz/TEST FRI 

o o o 

4— ..L-L, 



STROBE 

AMD 
STOflE 



J* 



1 Hz/TEST FREQ 



DISPLAY 

ANDSET 

CONTROL 

LOGIC 



EI 



DIGIT 


=s;l 


CONTROL 




LOGIC 


O 3 




O.J 



13a MILS - 



□ SET 

□ TIME 

ni" 

DA 

n> 

ni 

□ E 

DC 

an 



'l D 

2 a 

IIGITS ■ ,_, 
4 □ 

1 □ 

0SC0UT D 



TEST 
V ss LAMP FREQ TEST 4096 OSC IN 

d a a a a a 



=> 



connection diagram 



7SEGMENT DECODE 



TTTTTTT 

A B C D E F G 
SEGMENTS 

FIGURE 1. 











































TIME i 


f 4 3 2 
5 


1 30 29 2S27 

26 


} DIGIT 3 


SEG F <, " 


6 26 


~i DIGIT 2 


SEG A i 


7 24 


I DIGIT4 


SEG b r 


8 23 


~~~ 7 DIGIT 1 


SEG E I 


9 22 


> OSC OUT 


SEG G 1 ' 


10 21 


~~~> OSC IN 


SEGC 1 " 


" 12 13 14 15 16 17 IB 19 2D 


"7 nc 








































FREQ 
TOP VIEW 






Fl( 


3UR 


E 


3 







7-2 



absolute maximum ratings 

Voltage at Any Pin 
Operating Temperature Range 
Storage Temperature Range 

Dice 

Packages 

v DD - V ss 

Lead Temperature (Soldering, 10 seconds) 



electrical characteristics 



V SS -0.3V to V DD +0.3V 
-5°C to +70°C 

-25°C to +85°C 

-55°Cto+125°C 

5V max 

300° C 



T A within operating temperature range, V ss = GND, 2.4 < V DD < 4.0V, unless otherwise noted. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Oscillator Start Voltage 


T A = 25°C 


2.7 






V 


Input Voltage Level @ Time, Set 


V DD = 3.0V 










Logical "1" 




1/2 V DD 




V DD 


V 


Logical "0" 


300 kfi Pull-Down to V ss 




Open 




V 


Input Voltage Level @ Test Frequency 


V DD = 3.0V 










Logical "1" 




V DD -0.25 




v DD 


V 


Logical "0" 




Vss 




Vss+0.25 


V 


Input Voltage Level @ Lamp, Test 


Voo "3.0V 










Logical "1" 


1 MSI Pull-Upto V DD 




Open 




V 


Logical "0" 




Vss 




Vss +0.25 


V 


Input Current @ Time and Set 


Vin = V DD , Sink Only, V DD = 3.0V 






10 


UA 


Input Current @ Lamp and Test 


Vin = V ss , Source Only, V DD = 3.0V 






3 


M 


Input Capacitance 


f = 1.0 MHz, V IN =0.0V 
All other pads GND 






6 


pF 


Output Voltage Level @ Segment Drivers 










V 


Logical "1" 


V DD =2.4V, Isource >10/jA 


V DD -0.2 




v DD 


V 


Logical "0" 


V DD =2.4V, l SINK >300uA 


Vss 




Vss+0-5 


V 


Output Voltage Level @ Digit Drivers 












Logical "1" 


V DD = 2.4V, I S ource>840mA 


V DD -1.3 




Vdd 


V 


Logical "0" 


V DD =2.4V, l SINK >20uA 


Vss 




Vss+0-2 


V 


Output Voltage Level @ 4096, 1 Hz 


Vod = 3.0V 










Logical "1 " 


Isource > 10uA 


V DD -0.2 




Vdd 


V 


Logical "0" 


Isink > 10/jA 


Vss 




Vss+0.2 


V 


Supply Current (I D d) 


f = 32768 Hz, T A = 25° C 

Vqd " 3.0V, Unused Inputs Open, 

Outputs Open 




5 


10 


MA 


Supply Current ll DD } 


Stop Mode, T A = 25°C, V DD = 3.0V, 
Unused Inputs Open, Outputs Open 






1 


MA 



functional description 

A block diagram of the MM5829 digital watch chip is 
shown in Figure 1 . A chip pad layout is shown in Fig- 
ure 2 and a package connection diagram in Figure 3. 

Time Base 

The precision time base of the watch is provided by the 
interconnection of a 32768 Hz quartz crystal and the 
RC network shown in Figure 4 together with the CMOS 
inverter/amplifier provided between the oscillator in and 
oscillator out terminals. Resistor R1 is necessary to bias 
the inverter for class A amplifier operation. Resistor R2 
is required in order to (a) reduce the voltage sensitivity 
of the network, (b) limit the power dissipation in the 



quartz crystal, and (c) provide added phase shift for 
good start-up and low voltage circuit performance. 
Capacitors C1 and C2 in series provide the parallel load 
capacitance required for precise tuning of the quartz 
crystal. 

The network shown provides >100 ppm tuning range 
when used with standard X-Y flexure crystals trimmed 
for C L = 12 pF. Tuning to better than ±2 ppm is easily 
obtainable. 

The 4096 Hz output or 1 Hz output can be used to 
monitor the oscillator frequency during initial tuning 
without disturbing the network itself. 



7-3 



functional description (con't) 

Time Display 

The HOURS-MINUTES/SECONDS Display feature is 
controlled by a normally open switch connected to the 
Time input as shown in Figure 6. A logic "1" applied 
to the Time input will cause HOURS-MINUTES to be 
displayed for not less than 1.5 seconds or more than 2.0 
seconds. The hours digits can display values 1 — 12 while 
the minutes digits can display values 00—59. All zero 
values are displayed for minutes and leading zero values 
of hours are blanked. The character display font is 
shown in Figure 5. Holding a logic "1" on the Time 
input after the time-out of HOURS-MINUTES will cause 
SECONDS to be displayed in digit positions 3 and 4 
until the Time input is opened. SECONDS will blink 
while displayed. Each value is visible for 0.5 seconds and 
blanked for 0.5 seconds. The SECONDS digits can dis- 
play values 00—59. All zero values are displayed. 

Display Multiplexing 

Outputs from each counter are time-division multiplexed 
to provide digit-sequential access to the time data. Thus, 
instead of requiring 28 leads to interconnect a four digit 
(7 segments/digit) watch, only 1 1 output leads are re- 
quired. Figure 6 shows the interconnection of an LED 
watch system. The four digit outputs of the MM5829 are 
designed to interface with the bipolar DM8650 digit 
driver chip. The seven segment outputs are designed to 
interface with the bipolar DM8651 segment driver chip. 
The four digits of the LED Display are multiplexed with 
a 25% duty cycle, 1024 Hz signal during Display. The 
digit drivers are turned off for 1 5us during change of 
digits to allow the seven segments to change without 
"ghosting" of the Display. When the MM5829, DM8650, 
and DM8651 are used as shown in the typical applica- 
tion of Figure 6 the peak segment on currents are 
typically 9 mA. The 0101 LED Display gives excellent 
brightness under these drive conditions. 

Time Setting 

A normally open switch connected to the Set input is 
used in conjunction with the Time switch to set hours, 
minutes, and synchronize seconds. 

HOURS: A logic "1" applied to the Set input will cause 
HOURS-MINUTES to be displayed and will advance 



HOURS at a 1 Hz rate. The Seconds and Minutes 
counters continue normal counting during this 
condition. 

SECONDS: With a logic "1" on the Time input, the 
application of a logic "1" to the Set input will immedi- 
ately reset the Seconds counter to 00 and allow a normal 
seconds count from there. 

MINUTES: A logic "1" applied to both the Time and 
Set inputs will allow HOURS-MINUTES to be displayed 
and will advance the MINUTES at a 1 Hz rate. A transi- 
tion from 59 to 00 will not advance the Hours counter 
in this condition. 

CONTACT BOUNCE: Debounce circuitry is provided 
on the Time and Set inputs to remove any logic 
uncertainty upon either closure or release of switches 
providing switch bounce settles within 20 ms. 

Oscillator Stop 

The oscillator can be stopped in order to conserve 
battery life during shipment of the watch. The oscillator 
will stop if a logic "1" is momentarily applied to the 
Time input and while HOURS-MINUTES are displayed 
a logic "1" is momentarily applied to the Set input. 
The Display is inactive during this mode. The oscillator 
will start again when a logic "1" is applied to the Set 
input. 

Test Points 

Four pins are provided for test purposes. A 4096 Hz 
symmetrical signal is brought out for oscillator tuning. 
The pin 1 Hz/Test Frequency is an input/output under 
control of Test. With Test open, a 1 Hz output will 
appear on the 1 Hz/Test Frequency pin. If Test is con- 
nected to a logic "0," the 1 Hz/Test Frequency becomes 
an input and any frequency connected to it will be 
divided by the Seconds counter in place of the normal 
1 Hz signal. This feature is provided to allow high speed 
functional testing of the watch system. If lamp is con- 
nected to a logic "0," all segments will be forced to an 
on condition under control of the normal 25% duty 
cycle of the digit drivers. An internal pull-up resistor will 
normally hold the lamp input to logic "1." 



CMOS IMVERTEA 



H>- 




45 pF 

♦ V D0 OR Vy; 



J 



n 



n 

L/f r 





FIGURE 4. Crystal Oscillator Network 



FIGURE 5. Character Display Font 



functional description (con't) 



-\Q\~ 



\f 32768 Hz 

/ CRYSTAL " 



OSCOUT 

TIME 



MM5B29 
(CMOS) 



SEGMENT DRIVER 
DM8551 

'BIPOLAR! 



DIGIT DRIVER 
DMB650 

(BIPOLAR) 



— 1.5V 

-CASE 



T 



^ 



U^-L 



li. 



nrzzjr : 

d — JJ 
rr — <n 






LiZZ 



n 

! /c 



0101 
LEO 
DISPLAY 



FIGURE 6. Typical Application 



7-5 




Watches 



MM5860, MM58601, MM5880, MM58801 
two time zone LED watch circuits 

general description 

The MM5860/MM5880 is a low threshold voltage, ion- 
implanted, metal-gate CMOS integrated circuit that 
provides or controls all signals needed for a 4-digit 
LED watch. The display format is either 12 or 24 
hours. The circuit time base is a 32,768 Hz crystal con- 
trolled oscillator. This time base is successively divided 
to provide drive signals for a multiplexed 7 -segment LED 
display of Date-Month, Local Hours-Minutes, Zone 
Hours-Minutes, or Seconds upon demand for the 
MM5860 version. The MM5880 version will vary only in 
the date display by displaying Month-Date. The 
MM58X01 versions will blink the Month during the 
date display. Outputs interface with currently available 
standard bipolar segment and digit driver integrated 
circuits. The device operates from a single 2.4— 4.0V 
supply. All versions are available as unpackaged die 
suitable for hybrid assembly or in 40-lead dual-in-line 
packages for evaluation purposes. 



features 

■ 32,768 Hz crystal controlled operation 

■ Single 3V supply 

■ Low power dissipation (15jUW typical) 

■ Seconds, Minutes, Local and Zone Hours, Date, and 
Month display 

■ 4 year calendar 

■ 4-digit, 12/24 hour display format 

■ AM indication in 12-hour format 

■ Simple display/set controls 

■ Auto return from Set and Display mode 

■ Easy interface to standard bipolar IC's for display 
drive 

■ Display brightness control 



block and connection diagrams 



hz/test freq 



'LA 



I t Hz/TES 
I FREQ. 



LAMP O— — • 



r^— r 




M M i 1 



1 O D 




lUUr 



IXXXXXX 



0SC0UT - 
DSC IN - 
0IG1T2 - 



TT 



- SEGMENT B 

- SEGMENT A 

- SEGMENT F 



- CYCLE 

- ZONE 



7-6 



absolute maximum ratings 



Voltage at Any Pin 
Operating Temperature Range 
Storage Temperature Range 

VDD - VSS 

Lead Temperature (Soldering, 10 seconds) 



Vss -0.3V to Vqd + 0-3V 

-5°Cto +70°C 

-25°Cto+85°C 

5V max 

300° C 



electrical characteristics 

Ta within operating temperature range, Vgs = 



Gnd, 2.4V < Vrjp < 4V, unless otherwise noted. 



PARAMETER 



CONDITIONS 



MIN 



TYP 



UNITS 



2 
00 

o> 
o 



en 

00 

o 



Oscillator Start Voltage 

Input Voltage Levels at Cycle, 
Set/Display and Zone 

Logical "1 " 

Logical "0" 
Input Voltage Levels at 4 Hz/Test Freq, 
24 Hr, 

Logical "1 " 

Logical "0" 

Input Voltage Levels at Lamp, Test 
Logical "1 " 
Logical "0" 

Input Voltage Levels at Dim 
Display Duty Cycle = 21.875% 
Display Duty Cycle = 9.125% 
Display Duty Cycle = 3.125% 

Input Current at Cycle, Set/Display 

and Zone 

input Current at Lamp and Test 

Input Current of Dim 

Input Capacitance 

Output Current Levels at Segment Drivers 
Logical "1 ,*" Source 
Logical "0," Sink 

Output Current Levels at Digit Drivers 
Logical "1 ," Source 
Logical "0," Sink 

Output Current Levels at 4 Hz/Test Freq, 
4096 Hz 

Logical "1," Source 

Logical "0," Sink 
Output Current Levels at Colon 

Logical "0," Sink 

Supply Current OddI 



Supply Current { 1 DD ) 



T/\ = 25" C, Circuit of Figure 4 
V DD = 3V 

300k<: Internal Pull-Down to V'ss 



V DD =3V 

1 MS2 Internal Pull-Up to Vqd 



5 MP. Pull-Down to Vss 



V|N = V DD. Sink Only, 
V DD =3V 

V|N = VSS. Source Only, 
V 0D =3V 

V|N = V DD. sink Only, 
V DD =3V 

f = 1 MHz, V|N = 0V, 
All Other Pads Gnd 

V DD = 2.4V, V 0U T= V D D- 0.2V 
V DD = 2.4V, VQUT = VSS + 0.5V 

V DD = 2.4V, V UT= V D D - 1 -3V 
V DD =2 4V,V UT= V S S + 02V 

V DD =3V 

V0UT= V OD -0.2V 
VOUT = V S S f 0.2V 

VDD =2,4V, V 0UT = 1V 
f = 32,768 Hz, T A - 25°C, 
VpD = 3V, Unused Inputs Open, 
Outputs Open 

Oscillator Stopped, Ta = 25"C, 
VDD ~ 3V, Unused Inputs Open, 
Outputs Open 



1 2V DD 



VDD-025 
VSS 



VSS 

Open 

Vss+0.9 

VdD-05 

0.2 

0.2 



10 
300 



840 
10 



10 
10 



Open 



Open 



VDD 



VDD 
VSS+0.25 



Vss+0-25 

VsS+03 
VDD-1-1 

10 



30 
600 



1500 
30 



0.05 



10 



V 

V 

V 

uA 



uA 



uA 



pF 



AlA 
uA 



uA 
uA 



uA 
uA 



mA 
HA 



UA 



7-7 



functional description 

Unless otherwise specified, all references to the 
MM58X0 will also refer to the MM58X01. A block 
diagram of the MM5860/MM5880 is shown in Figure 1. 
The connection diagram is shown in Figure 2 and the 
chip pad layout in Figure 3. 



\ 


□ 4096 Hz 
□ OSC0UT 


O 

1 Hz/TEST 
FREQ 


D □ 

TEST LAMP 


"ssD 

' »D 


i 


Dose IN 






CD 


j 


2 








ED 


59 K 


IIS 


Di 

D3 


DIGITS 




SEGMENTS 


GD 
BD 
AD 

FD 












SET DISPLAY Q 






21 HR 

D«ddD 


DIM 
□ 


COLON ZONE CYCLE 
□ □ □ 



to allow the segment decoding circuitry adequate time 
to switch to the next digit's information. This eliminates 
the possibility of "ghosting" information between digits. 
When the MM5860/MM5880, DS8658 and DS8659 are 
used in a typical application as shown in Figure 6 the 
peak segment "ON" currents are typically 11 mA. 
The NSCO101 LED display gives excellent brightness 
under these drive conditions. 



FIGURE 3. Pad Layout 
Time Base: The precision time base of the watch is pro- 
vided by connecting a crystal-controlled RC network to 
the on-chip CMOS inverter/amplifier as shown in Figure 
4. For proper operation, the network should be tuned 
to 32,768 Hz. Resistor R1 is used to bias the on-chip 
inverter for class A amplifier operation. Resistor R2 is 
used to (a) reduce the voltage sensitivity of the network; 

(b) limit the power dissipation in the quartz crystal; and 

(c) provide added phase shift for good start-up and low 
voltage circuit performance. Capacitors C1 and C2 in 
series provide the parallel load capacitance required for 
precise tuning of the quartz crystal. The network shown 
in Figure 4 provides greater than 100 ppm tuning range 
when used with standard X-Y flexure quartz crystals 
trimmed for Cl = 12 pF. Tuning to better than 2 ppm 
is easily obtainable. 



^trrfn 




C 250k 

i> Mf- I 



♦■ TO COUNTERS 



FIGURE 4. Oscillator RC Network 

The 4096 Hz output or the 4 Hz output can be used to 
monitor the oscillator frequency during initial tuning 
without disturbing the network itself. 

Display Multiplexing: The counter data selected to be 
displayed is time-division multiplexed to provide digit- 
sequential presentation to the LED display. This reduces 
the number of outputs required to drive the 4-digit 
display to 1 1 (7 segment drivers and four digit drivers). 
The display font is shown in Figure 5. Figure 6 is a 
schematic diagram of a typical LED watch using the 
MM5860/MlVI5880 watch chip. The digit outputs of the 
MM5860/MM5880 are designed to interface with the 
bipolar DS8658 digit driver chip and the segment driver 
outputs will interface with the bipolar DS8659 segment 
driver chip. The four digits of the LED display are 
multiplexed with a 25% duty cycle, 1024 Hz signal 
during the display period. The digit drivers are dis- 
abled for 32^s at the beginning of each digit enable time 



FIGURE 5. Character Display Font 

DISPLAY CONTROL 

The Time and Date display sequence is controlled by a 
normally open switch connected to the Set/Display 
input. With the display off, depressing the Set/Display 
switch will activate the Locai Hour: Minute display. This 
display will remain on for 1 .25 seconds ±0.125 seconds. 
If the switch is still held in at the end of this time out. 
Seconds will be displayed, blinking on for 0.25 seconds 
and off for 0.75 seconds, until the Set/Display switch is 
released. If, during the HounMinute display, the Set/ 
Display switch is released and depressed a second time 
the date will be displayed as Date Month in the IVIM5860 
version and as Month Date in the MM5880 version. 
The Month will blink on for 0.25 seconds and off for 
0.75 seconds in the MM58601 and the MM58801 
versions and not blink in the MM5860 and the MM5880 
versions. The display will remain on for 1.25 seconds 
and turn off automatically if the Set Display switch has 
been released. Holding the Set/ Display switch in past 
the display time out will maintain the display until 
the Set/Display switch is released. Zone Hour:Minute 
can be displayed by depressing the Zone switch. This 
display will also remain on for 1.25 seconds ±0.125 
seconds. Holding the Zone switch depressed beyond 
this period will cause Seconds to be displayed until 
the switch is released. The date information can not 
be displayed using the Zone switch. Leading zeros are 
blanked on the Month, Date and Hour displays. 

TIME SETTING 

The setting sequence is controlled by a normally open 
switch connected to the Cycle input. Depressing the 
Cycle switch will advance the watch to the next set 
mode. 

Set Hour Mode: With the watch in normal Run mode 
and the display off, depressing the Cycle switch will 
advance the watch to the Set Local Hour mode. In this 
mode local hours will be displayed in digit positions 1 
and 2 followed by the colon. The AM dot will be on 
during AM time display. Depressing the Set/Display 
switch will advance the Local Hour counter at a 2 Hz 
rate. Depressing the Zone switch while in the Set Local 
Hour mode will cause zone hours information to replace 
the local hours information in digit positions 1 and 2. 




(1 ) Anti-resonant quartz crystal, C|_ = 1 2 pF 

FIGURE 6. System Schematic 



The colon and the AM dot will stiil be presented as in 
the Local Hours display. The Zone Hour counter can 
now be advanced at a 2 Hz rate by depressing the Set/ 
Display switch. 

In either of the above Set Hour modes if no switches are 
depressed for 5.25 seconds ±0.125 seconds consecu- 
tively, the watch will automatically return to the Run 
mode. Depressing the Cycle switch while in the Set 
Zone Hour mode will return the watch to the Run 
mode. Depressing it while in the Set Local Hour mode 
will place the watch in the Set Minutes mode. 

Set Minutes Mode: The Set Minutes mode will display 
minutesin digit positions 3 and 4 preceded by the colon. 
Depressing the Set/Display switch while still holding 
the Cycle switch in will enable the Hold flag but will not 
allow advancement of the Minutes Counter. Depressing 
the Set/Display switch after the Cycle switch has been 
released will do the following: 

a. Reset and hold the Seconds Counter 

b. Enable the Hold flag, and 

c. Advance the Minutes Counter at a 2 Hz rate 

If none of the switches are depressed for 5.25 seconds 
±0.125 seconds consecutively while in the Set Minutes 
mode, the watch will automatically return to the Run 
Mode if minutes have not been set or will jump to the 
Hold mode if minutes have been set. Depressing the 
Cycle switch while in the Set Minutes mode will advance 
the watch to the Set Date mode for the MM5860 version 
or the Set Month mode for the MM5880 version. 

Set Date Mode: The Set Date mode will display the Day 
of Month in digit positions 1 and 2 in the MM5860 
version, or in digit positions 3 and 4 in the MM5880 
version, with no colon displayed. Depressing the Set/ 
Display switch while in the Set Date mode will advance 
the Date Counter at a 2 Hz rate. 



If none of the switches are depressed for 5.25 seconds 
±0.125 seconds consecutively while in the Set Date 
mode, the watch will automatically return to the Run 
mode if the Minutes Counter was not set or will jump to 
the Hold mode if the Minutes Counter was set. Depres- 
sing the Cycle switch while in the Set Date mode will 
advance the watch to the Run mode if the Minutes 
Counter was not set or will advance it to the Hold mode 
if the Minutes Counter was set for the MM5880 version. 
Depressing the Cycle switch while in the Set Date mode 
of the MM5860 version will advance the watch to the 
Set Month mode. 

Set Month Mode: The Set Month mode will display the 
month in digit positions 3 and 4 in the MM5860 version, 
or in digit positions 1 and 2 in the MM5880 version, 
with no colon displayed. Depressing the Set/Display 
switch while in the Set Month mode will advance the 
Month Counter at a 2 Hz rate. 

If none of the switches are depressed for 5.25 seconds 
±0.125 seconds consecutively while in the Set Month 
mode, the watch will automatically return to the Run 
mode if the Minutes Counter was not set or will jump 
to the Hold mode if the Minutes Counter was set. 
Depressing the Cycle switch while in the Set Month 
mode will advance the watch to the Run mode if the 
Minutes Counter was not set or will advance it to the 
Hold mode if the Minutes Counter was set for the 
MM5860 version. Depressing the Cycle switch in the Set 
Month mode of the MM5880 version will advance the 
watch to the Set Date mode. 

Hold Mode: In the Hold mode the Seconds Counter is 
held at 00. Local HounMinute will blink on for 0.25 
seconds and off for 0.75 seconds. Depressing the Cycle 
switch while in the Hold mode will put the watch back 
into the Set Hour mode and then the counters can be 
set as described previously. With the Hold mode still 
activated, the watch will return to the Hold mode only. 
Depressing the Set/Display switch while in the Hold 



7-9 



mode will place the watch into the display Local Hour: 
Minute mode and allow the Seconds Counter to begin 
normal operation. 

There is no roll-over of the next higher counter while a 
counter is being set. For example, while the Minutes 
Counter is set from 59 to 00 neither the Local Hour nor 
the Zone Hour Counter will be advanced. 

Figure 7 is a state diagram showing the display and set 
functions for both the MM5860 and the MM5880. 

COLON OUTPUT 

This output provides direct drive of the colon in the 
LED display unit. Colon will sink current when acti- 
vated. The colon output will be activated during the 
display of either one of the hour counters or the minute 
counter or both. 

CONTACT BOUNCE 

Debounce circuitry is provided on the "Set/Display" 
and "Cycle" inputs to remove any logic uncertainty 
upon either closure or release of switches provided 
switch bounce settles within 100 ms. 

12/24 HOUR OPTION 

12/24 hour mode operation of the watch is controlled 



by the logical state of the "24 Hr" input. If the "24 Hr" 
input is a logical "1" the watch will operate in the 24 
hour mode. When the "24 Hr" input is a logical "0" 
the watch operates in 12 hour mode. 

DIM INPUT 

The Dim input is a three level input used to control 
the display intensity of the watch. This input has a pull- 
down to VgS to hold it normally at a logical "0." 

In this condition the display will normally be at maxi- 
mum intensity. With the Dim input at 1/2 Vqq, the dis- 
play will be at approximately 1/2 of full intensity. 
Placing the input at Vqq wi " reduce the display inten- 
sity to approximately 1/8 of full intensity. Figure 8 
shows the switching threshold ranges for the three level 
DIM input. 

TEST POINTS 

Four pads are provided for test purposes. 

4096 Hz: This pad outputs a 4096 Hz signal that can be 
used for oscillator tuning. 




USER CONTROLLED ROUTES 



FIGURE 7. Control State Diagram MM5860 IMM5880I 





DISPLAY TIME/DIGIT 


DISPLAY CONDITION 


V|N = VqD 


3.125% 


Low Ambient Light Levels 


V|N = V DD -0.5V 


Threshold Region 




V|N = V DD -1.1V 


9.125% 


Moderate Ambient Light Levels 


V|N = V S s + 0-9V 


Threshold Region 




V|N = VSS + 0.3V 


21.875% 


High Ambient Light Levels 


V|N = VsS 







FIGURE 8. Counter Voltage Levels at Dim Input 



7-10 



TEST POINTS (CON'T) 

4 Hz/Test Freq: This is an input/output pad under the 
control of the "Test" input. When "Test" is at a logical 
"0," the "4 Hz/Test Freq" pad becomes an input and 
any frequency connected to it will replace the normal 
internal 4 Hz signal. This feature is provided to allow 
high speed functional testing of the watch system. 
When "test" is open or at a logical "1", a 4 Hz output 
will appear on the "4 Hz/Test Freq" pad. 

Test: This pad is used as an input to control "4 Hz/ 
Test Freq." An internal pull-up resistor will normally 
hold "Test" at a logical "1." 



Changing the Test input from a logical "1" to a logical 
"0" will generate a reset pulse which will Set the internal 
counters to 1 PM on January the first. The watch is now 
in a known state for testing purposes. 

Lamp: When the "Lamp" input is at a logical "0," all 
segments of the display will be forced to an "ON" 
condition under control of the normal 25% duty cycle 
of the digit drivers. An internal pull-up resistor will 
normally hold the "Lamp" input at a logical "1." 



2 

00 
05 
O 

01 
00 
<7> 

g 

en 
oo 
oo 
o 

Ul 
00 
00 

o 



(J) 
<n 
oo 

in 



CO 
CO 
ID 

5 




Watches 



MM5879, MM5889, MM5899 RC circuits 



en 

CO 

if) 



general description 



The MM5879, MM5889, MM5899 are RC circuits 
which may be used in watch modules and other similar 
applications. They are available in die form. All die 
are pad-for-pad interchangeable, offering a range of 
capacitance and resistance values. 



absolute maximum ratings 

v S s 



Voltage at Any Pad 
Operating Temperature 
Storage Temperature 



0.3V to Vss - 20V 
-5°C to+70°C 
-65°Cto+150°C 



schematic diagram 



vss 



"ss 



PART NUMBER 


R1 


R2 


CAP (Note 1) 


MIN 


MAX 


MIN 


MAX 


MIN 


MAX 


MM5B79 
MM5889 
MM5889AB 
Mlt,5899 


125k 
250k 
250k 
250k 


235k 
470k 
470k 
470k 


15M 
15M 
15M 
15M 


30 M 
30M 
30M 
30M 


9 pF 
45 pF 
24 pF 
14 pF 


13 pF 
55 pF 
36 pF 
20 pF 



Note 1: Capacitances are measured periodically only. Capacitance measured from 
Vgs *° common. 



chip pad layout 



-30 MILS- 




JLi 



S 



C0MM 



36 MILS 



7-12 



a 



Watches 



MM5885, MM5886 direct drive LED watch 
general description 

The MM5885, MM5886 is a low threshold voltage, 
ion-implanted, metal-gate CMOS integrated circuit 
that provides or controls all signals needed for a 4-digit 
LED watch. The display format is 12 hours. The circuit 
time base is a 32,768 Hz crystal controlled oscillator. 
This time base frequency is successively divided to 
provide drive signals for a multiplexed 9-segment, alpha- 
numeric LED display of DAY-DATE, HOURS-MINUTES 
or SECONDS upon demand. A Month counter is 
provided to control the count sequence of the Date 
counter. The MM5885 uses one button to display while 
the MM5886 uses two buttons for display purposes. 
Outputs interface directly with an alphanumeric LED 
display. The device operates from a single 2.4V to 4.0V 
supply. Both the MM5885 and MM5886 are available 
as unpackaged die suitable for hybrid assembly or in 
a 40-lead dual-in-line package for evaluation purposes. 

features 



No external 
crystal 



parts except the battery, LEDs and 



■ 32,768 Hz crystal controlled operation 

■ Single 3V supply 

■ Low power dissipation (15/iW typ) 

■ Seconds, Minutes, Hours, Day-of-Week, Date and 
Month operation 

■ 4 year calendar 

■ 4-digit, 12 hour display format 

■ Simple display/set controls 

■ Inertial switch input 

■ Alphanumeric display 

■ Direct drive outputs 

■ Display brightness control 

■ AM/PM indication during set hours 

■ Month indication during set month 

■ Test features 

■ Single button display control (MM5885) 



01 
oo 
oo 
m 

00 
00 



block diagram 



13 STAGE DIVIDER 



X 



CONTROL LOGIC 



r~r 



TFST 4Hz TtSn 

I f 



Tt 



I0UNTER T * COUNTER * COUNTER I 



111 III 



n — i 



9SEGMENT 

DECODE AND 

BUFFERS 



IXTXXI 

A B C D E F G 
SEGMENTS 

FIGURE 1. 



7-13 



absolute maximum ratings 










Voltage at Any Pin 


V ss -0.3V to V DD +0.3V 










Operating Temperature Range 


-5°C to +70°C 










Storage Temperature Range 


-25°C to+85°C 










Vdd ~ V ss 


5V max 










Lead Temperature (Soldering, 10 seconds) 300°C 










electrical characteristics 










T A within operating temperature range, V ss = GND, 2.4 < V DD < 4.0V, unless otherwise 


noted. 






PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Oscillator Start Voltage 


T A » 25"C 


2.7 






V 


Input Voltage Levels at Cycle, 












Set/Display, Day/Date, Hour/Mm 












Logical "1 " 


300 k!2 Internal Pull-Down 
to V ss 


1/2 V DD 




V DD 


V 


Logical "0" 






Open 






Input Voltage Levels at 












4 Hz/Test Freq 












Logical "1" 




V DD -0.25 




V DD 


V 


Logical "0" 




Vss 




Vss + 0.25 


V 


Input Voltage Levels at Lamp, Test 












Logical "1 " 


100 kil Internal Pul!-Up 
to V DD 




Open 






Logical "0" 




Vss 




Vss+0.25 


V 


Input Voltage Levels at Dim, 


5 Mil Pull-Down to V ss 










Display Duty Cycle = 21.875% 




Open 




V S s+0.3 


V 


Display Duty Cycle - 9.125 : ,'o 




Vss+0.9 




V DD 1.1 


V 


Display Duty Cycle -- 3.125% 




V aD -0.5 




Vdd 


V 


Input Current at Cycle, Set/Display, 


V DD =3.0V, V tN "- V DD , 




30 


50 


uA 


Day/Date, Hour/Mm 


Sink Only 










Input Current at Lamp, Test 


V DD -3.0V, V, N - V ss , 
Source Only 




30 


50 


uA 


Input Capacitance 


f -- 1 MHz, V IN - 0V, 
All Other Pads GND 






5 


pF 


Output Current Levels at 


V DD =2.7V 










Segment Drivers 












"ON" Source 


Vqut - V DD -0.5V 


7 


10 


15 


mA 


"OFF" Source 


Vout = V dd 1.1V 






50 


AiA 


Output Current Levels at 


V DD " 2.7V 










Digit Drivers 












"ON" Sink 


Vqut -- V ss * 0-6V 


50 


70 


2 


mA 


"OFF" Sink 


V OUT = 2.0V, All Digit Drivers Tied 
in Parallel 






1 


uA 


Output Current Levels at 












4 Hz/Test Freq., 4096 Hz 












Logical "1 " Source 


Vqut = V DD - 0.2V 


10 






KA 


Logical "0" Sink 


Vqut -V ss +0.2V 


10 






HA 


Operating Supply Current (I DD ) 


f = 32,768 Hz, T fl = 25°C, 
V DD = 3V, Unused Inputs Open, 
Outputs Open 




5 


10 


uA 


Quiescent Supply Current (l DD ) 


Osc In <5>Gnd, V DD = 3V, 
T A = 25"C, Other Inputs and 
Outputs Open 




0.05 


1 


MA 



7-14 



functional description 

A block diagram of the MM5885/MM5886 direct drive 
digital watch is shown in Figure 7. The chip pad layout 
is shown in Figure 2 and a package connection diagram 
in Figure 3. 



Time Base: The precision time base of the watch is 
provided by the 32,768 Hz crystal controlled oscillator, 
which consists of the quartz crystal, the CMOS inverter/ 
amplifier and the RC network shown in Figure 4. 
Resistor R1 is necessary to bias the inverter for class A 
amplifier operation. Resistor R2 is required in order to 
(a) reduce the voltage sensitivity of the network; (b)limit 
the power dissipation in the quartz crystal; and (c) pro- 
vide added phase shift for good start-up and low voltage 
circuit performance. Capacitors C1 and C eff in series 
provide the parallel load capacitance required for precise 
tuning of the quartz crystal. The network shown in 
Figure 4 provides greater than 100 ppm tuning range 
when used with standard X-Y flexure quartz crystal 
trimmed for C L = 12 pF. Tuning to better than 2 ppm 
is easily obtainable. 



Cap: This pin i; 
capacitance to 
Figure 4. 



used with Oscillator Out to add more 
the oscillator RC network shown in 



Display Control: The "Time" and "Date" display 
sequence is controlled by normally open switches 
connected to SET/DISPLAY, DAY/DATE (MM5886), 
and HOUR/MINUTE (inertial switch) inputs. With the 
display "OFF," depressing the SET/DISPLAY switch 
will activate the HOUR-MINUTE display. This display 
will remain "ON" for 1.25 seconds ±0.125 seconds. 
If the switch is still held in at the end of this time out, 
SECONDS will be displayed blinking "ON" for 0.25 
seconds and "OFF" for 0.75 seconds until the SET/ 
DISPLAY switch is released. If, during the HOUR- 
MINUTE display, the SET/DISPLAY switch is released 
and depressed a second time, the date will be displayed 
as DAY-DATE in the MM5885. The DAY-DATE display 
will remain "ON" for 1.25 seconds ±0.125 seconds 
and turn "OFF" automatically if the SET/DISPLAY 
switch has been released. Holding the SET/DISPLAY 
switch past the display time out will maintain the 
DAY-DATE display until the SET/DISPLAY switch 
is released. In the MM5886, depressing the SET/ 
DISPLAY a second time has no effect. To display 
DAY-DATE information in the MM5886, depress the 
DAY/DATE switch. The DAY-DATE display will remain 
"ON" for 1.25 seconds ±0.125 seconds. If the switch 
is still held in at the end of this time out, the display 
will remain until the DAY/DATE switch is released. 
"Time" may also be displayed in both the MM5885 and 



31.1- -E}° IG ! (HIOj =-23 



~ep a- --& 

I £ C 

"25 -:26 =27 



99.2 E|j-409t) (NC) ----19 

107.9 EB" CAp -1 a 



tfr- Ltj (tl A 



4 5 SQUARE. TYP 



=11 (NCI =8i.MC] 

DAV.-'DATE LAMP 

-10 =9 

(MODE) (DISPLAY: _r 

CYCLE SET "t 

A— tS & & 



; 18.9 ■ 36.2 
0.2 276 



726 103.2 

FIGURE 2. Pad Layout 



-EB 85.9 



SEGMENT I 
DIGIT 2 



DIGIT 3 ■ 
0IGIT4 ■ 
4096 Hz ■ 



VTEST ■ 

TEST ■ 

HR/MIN ■ 



SEGMENT E 
■ SEGMENT C 



SEGMENT D 
SEGMENT G 

SEGMENT B 

■ SEGMENT F 

■ SEGMENT H 

■ SEGMENT A 

■ NC 

■ NC 

■ LAMP 

■ SET/DISPLAY 

■ CYCLE 

■ DAY/DATE (MM5886) 



TOP VIEW 

FIGURE 3. Connection Diagram 




*• TO COUNTERS 



FIGURE 4(a). Oscillator RC Network for 
Anti-Resonant Quartz Crystals 




*■ TO COUNTERS 



FIGURE 4(b). Oscillator RC Network 
for Tuning Fork Quartz Crystals 



7-15 



functional description (con't) 

MM5886 by activating the HOUR/MINUTE input. 
The HOUR/MINUTE input is used with an inertial 
switch that is normally open. Closing the switch activates 
the HOUR/MINUTE display. This display will remain 
"ON" for 1.25 seconds ±0.125 seconds and then turn 
"OFF" automatically. 

Time Setting: The setting sequence is controlled by a 
normally open switch connected to the Cycle input. 
Depressing the Cycle switch will advance the watch to 
the next set mode. Figure 5 is a flow diagram showing 
the display and set functions for both the MM5885 
and the MM5886. 

Set Hour Mode: With the watch in the normal Run mode 
and the display "OFF," depressing the Cycle switch will 
put the watch into the Set Hour mode. In this mode, 
HOURS will be displayed in digit positions 1 and 2 
followed by the colon. An A or a P will be displayed in 
digit position 4 to indicate AM or PM, respectively. 
Depressing the SET/DISPLAY switch will advance the 
Hours counter at a 2 Hz rate. If neither the SET/ 
DISPLAY switch nor the Cycle switch are depressed 
for 5.25 seconds ±0.125 seconds, the watch will auto- 
matically return to the Run mode. Depressing the 
Cycle switch while in the Set Hours mode will advance 
the watch to the Set Minutes mode. 



Set Minutes Mode: The Set Minutes mode will display 
minutes in digit positions 3 and 4 preceded by the 
colon. Depressing the SET/DISPLAY switch while 
still holding in the Cycle switch will enable the hold 
flag but will not allow advancement of the MINUTE 
counter. Depressing the SET/DISPLAY switch after the 
Cycle switch has been released resets and holds the 
SECOND counter, enables the hold flag, and advances 
the MINUTE counter at a 2 Hz rate. If neither switch 
is depressed for 5.25 seconds ±0.125 seconds while 
the watch is in the Set Minutes mode, the watch will 
automatically return to the Run mode if minutes have 
not been set or will jump to the Hold mode if minutes 
have been set. Depressing the Cycle switch while in the 
Set Minutes mode will advance the watch to the Set 
Day mode. 

Set Day Mode: The Set Day mode will display DAY-OF- 
THE-WEEK in digit positions 1 and 2. Depressing the 
SET/DISPLAY switch while in the Set Day mode will 
advance the DAY counter at a 2 Hz rate. If neither 
switch has been depressed for 5.25 seconds ±0.125 
seconds while in the Set Day mode, the watch will 
automatically return to the Run mode if the hold flag 
was not set or will jump to the Hold mode if the hold 
flag was set. Depressing the Cycle switch while in the Set 
Day mode will advance the watch to the Set Date mode. 







r 


S/D 




S76 

STB 

D 


t 

1 






1 

1 

J 




RUM 


DISPLAY 
HR:MIN 


DISPLAY 
HRiMIN 


S/D 


DISPLAY 
DAY/DATE 


r* 


H/M 


S/D 




c 

1 


1 

1 












DISPLAY 
SECONDS 


STD 












i 










DISPLAY 
HOURS 


SET 

HOURS 


S/D -SET/DISPLAY 
H/M- HOOfi/MINUTE 
C- CYCLE 
— — — -TIME OUT ROUTE 




( m" 




'1 

' S/D 






| C 








01SPLAV 
M.NUIfcS 


SET 
MINUTES/HOLD 




. 1 STB * 




-t 






i C 








OISPLAV 

DAY 


SET 
DAY 




. S.'D ' 










1= 








DISPLAY 
DATE 


SET 
DATE 




1 s7d 




- -• 

1 S/D 






I' 








DISPLAY 
MONTH 


SET 

MONTH 




- 1 STB 




- -* 
_J 




|N0 


/ IS \. 

/ HOLD X 

X SE1 / 

YES 






c 


HOLD 












S/D 










S/D = SFT/DISPLAY 
H/M HOUR/MINUTE 
C - CYCLE 
-TIME OUT ROUTE 



FIGURE 5(a). MM5885 Flow Diagram 



FIGURE 5(b). MM5886 Flow Diagram 



7-16 



functional description (con't) 

Set Date Mode: The Set Date mode will display DATE in 
digit positions 3 and 4. Depressing the SET/DISPLAY 
switch while in the Set Date mode will advance the 
DATE counter at a 2 Hz rate. If neither the SET/ 
DISPLAY nor the Cycle switches have been depressed 
for 5.25 seconds ±0.125 seconds while in the Set Date 
mode, the watch will automatically return to the Run 
Mode if the hold flag was not set or will jump to the 
Hold mode if the hold flag was set. Depressing the 
Cycle switch while in the Set Date mode will advance 
the watch to the Set Month mode. 

Set Month Mode: The Set Month mode will display 
MONTH in digit positions 3 and 4 and an "M" in digit 
position 1. Depressing the SET/DISPLAY switch while 
in the Set Month mode will advance the MONTH counter 
at a 2 Hz rate. If neither the SET/DISPLAY nor the 
Cycle switches have been depressed for 5.25 seconds 
±0.125 seconds while in the Set Month mode, the watch 
will automatically return to the Run mode if the hold 
flag was not set, or will advance to the Hold mode if 
the hold flag was set. Depressing the Cycle switch while 
in the Set Month mode will advance the watch to the 
Hold mode if the hold flag was set; otherwise, the watch 
will advance to the Run mode. 

Hold Mode: In the Hold mode the SECOND counter is 
held at 00, and the HOUR-MINUTE display will blink 



"ON" for 0.25 seconds and "OFF" for 0.75 seconds. 
Depresssing the SET/DISPLAY switch will place the 
watch in the display HOUR/MINUTE mode for 1.25 
seconds ±0.125 seconds. Depressing the Cycle switch 
while in the Hold mode will advance the watch to the 
Set Hour mode. There is no roll-over of the next higher 
counter while a counter is being set at a 2 Hz rate. 



Month Counter: The MONTH counter provides "smart 
Date" but is only displayed during the Set Month mode. 
The DATE counter will count 28 days in February, 
30 in April, June, September and November, and 31 
in the remaining months. 



Contact Bounce: Debounce circuitry is provided on the 
SET/DISPLAY, CYCLE, DAY/DATE and HOUR/ 
MINUTE inputs to remove any logic uncertainty upon 
either closure or release of the switches. 20 ms debounce 
protection is provided for SET/DISPLAY, CYCLE and 
DAY/DATE inputs and 200 ms protection is provided 
for the HOUR/MINUTE input. 



Display Multiplexing: The counter data selected to be 
displayed is time-division multiplexed to provide digit- 
sequential presentation to the LED display. This reduces 



- 


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o 




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o 


- ■■ — ■;= 


-_ 






o 






".- 


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""■' — '- 


"- " ; 7 














rV" "'^-' 


_ 








0=, 


.: _ 


, 










n 










U ^ 








" 


U u 








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p 


iT"" XI 


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Ll 


P P 




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- 



FIGURE 5(c). Set Display Font 



7-17 



functional description (con't) 

the number of outputs required to drive the 4-digit 
display to thirteen (9-segment drivers and 4-digit drivers). 
The display font is shown in Figure 6. Figure 8 is a 
schematic diagram of a typical LED watch using the 
MM5885 watch chip. The segment and digit drivers 
are designed to interface directly with the LED display. 
The four digits of the LED display are multiplexed 
with a 23% duty cycle, 1024 Hz signal during the display 
period. The digit drivers are disabled for 32usec at the 
beginning of each digit enable time to allow the segment 
decoding circuitry adequate time to switch to the next 
digit's information. This eliminates the possibility of 
"ghosting" information between digits. 



Test Points: Four pads are provided for test purposes. 

4096 Hz: This pad outputs a 4096 Hz signal that can be 
used for oscillator tuning. 

4 Hz/Test Freq: This is an input/output pad under the 
control of the Test input pad. When "Test" is at a logical 
"0," the 4 Hz/Test Freq pad becomes an input and any 
frequency connected to it will replace the normal 
internal 4 Hz signal. This feature is provided to allow 
high speed functional testing of the watch system. 
When "Test" is open or at a logical "1," a 4 Hz output 
will appear on the 4 Hz/Test Freq pad. 



Dim Input: The Dim input is a 3-level input used to 
control the display intensity of the watch. This input 
has a pull-down to V ss to hold it normally at a logical 
"0." In this condition, the display will normally be at 
maximum intensity. With the Dim input at 1/2 V DD 
the display will be at approximately 1/2 of full intensity. 
Placing the input at V DD will reduce the display inten- 
sity to approximately 1/8 of full intensity. Figure 7 
shows the switching threshold ranges for the 3-level 
Dim input. 

Colon Output: Colon information is present on the "h" 
and "i" segment outputs during digit position 4. 



Test: This pad is used as an input to control the 4 Hz/ 
Test Freq pad. An internal pull-up resistor will normally 
hold "Test" at a logical "1." Changing the Test input 
from a logical "1" to a logical "0" will generate a reset 
pulse which will set the internal counters to 1 AM on 
Sunday, January the first. The watch is now in a known 
state for testing. 

Lamp: When the Lamp input is at a logical "0," all 
segments of the display will be forced to an "ON" 
condition under control of the normal 23% duty cycle 
of the digit drivers. An internal pull-up resistor will 
normally hold the Lamp input at a logical '"]." 






rf'—n 

4i Jy 



n r:-j 



'oi a // 



SUNDAY 



TUESDAY 



FRIDAY 




FIGURE 6. Display Font 



21.875% DUTY CYCLE 



_T 



9.375% DUTY CYCLE 



3.125% DUTY CYCLE 



n 



V|N 


DISPLAY TIME/DIGIT 


DISPLAY CONDITION 


Vdd 


3.125% 


Low Ambient Light 


V DD -0.5V 


Threshold Region 




V DD -1.1V 


9.375% 


Moderate Ambient Light 


Vss + 0-9V 


Threshold Region 




V ss + 0-3V 


21.875% 


High Ambient Light 


Vss 







FIGURE 7. Dim Input Levels 



7-18 



functional description (con't) 



£ 



r-: 



| 6-35 pF ~7^ 



~TT 



SEGMENT ENABLE 



NSC 9101 
NSC 0101 



NSC 9101 
NSC 0101 



Ui 






A B C D E F G H 



FIGURE 8(a). System Schematic for MM5885 LED Watch (Anti-Resonant Crystal) 



£ 



r-: 



SET/DISPLAY 



SEGMENT ENABLE 









o /; 

Ur- 



Jc=^U 



1 



A B C D E F G H 



FIGURE 8(b). System Schematic for MM588S LED Watch (Tuning Fork Crystal! 



7-19 



at 
oo 



a 



Watches 



MM5890 LCD chronograph circuit 
general description 

The MM5890 is a low threshold voltage, ion implanted, 
metal-gate CMOS integrated circuit that provides all 
signals needed to drive an LCD watch of six digits plus 
nine information segments. The circuit time base is a 
32.768 kHz crystal controlled oscillator. This base 
frequency is divided down to provide SECONDS, MIN- 
UTES, HOURS, DAY-OF-THE-WEEK, DATE and 
MONTH information in the normal watch mode with 
separate minutes, seconds, and hundredths of a second 
available in the stopwatch mode. Time display can be 
bonded to either 12 or 24 hour format. 51 phase con- 
trolled outputs are provided for direct drive of the 
display. The 32 Hz output is used as the backplane 
drive for normal operation and as a test frequency 
input during testing. The MM5890 operates on a single 
1.4V to 1.6V supply. An on-chip voltage multiplier is 
used to provide 2 or 3 times the battery voltage to drive 
the display. The MM5890 is available in die form suit- 
able for hybrid assembly or mounted on a 68-lead 
dual-in-line PCB assembly for test and evaluation 
purposes. 



features 

■ Direct continuous LCD drive capability 

■ 32.768 kHz crystal controlled operation 

■ Single 1.5V battery operation 

■ Voltage multiplier 

■ Low power dissipation 

■ 6-digit plus 9 information segment display 

■ Colon display 

■ 12 or 24 hour format 

■ 4 year calendar 

■ Stopwatch with split operation 

■ 6-function watch 

■ 4 button sequential operation 



block diagram 



DSC CAP 

nsciM 

OSC OUT 



START. STOP 

SET'DISP 

CVCLE 

MODE 

SW DISABLE 



SPLIT ( 
MONTH C 
COLON C 



HP 



OUTPUT 
PHASE 
CONTROL 



ffS^ 



CAP 1 CAP 2 CAP 3 V E t V ss Vq 

o o o o 



T 1 



S3 



..If 



u 



COUNTER 
SELECT 
LOGIC 



I A A A |I l { 

DIGIT 1 DIGIT 2 DIGIT 3 DIGIT; DIGIT 6 DIG 

fBI 171 fCI |7' (7) C 



OUTPUT LATCHES 



47 SEGMENT DRIVE OUTPUTS 



7-20 



absolute maximum ratings 








Voltage at OSC IN, OSC OUT, V DD + 0.3V to V ss - 0.3V Storage Temperature Range 

12 HR. SW Disable, Double, Triple Vqd - V EE 

Set/Display, Cycle, Mode, Start/Stop y _ v 

Voltage at Any Other Pin VpD + 0.3V to V EE -0.3V Lead Temperature (Soldering, 10 seconds) 

Operating Temperature Range — 5°C to +70'C 


-25°Cto+85°C 

6.5V 

3.0V 

300° C 


electrical characteristics 










T/\ within operating range, Vqd - Vss 


= 1 .5V, VrjQ - Vee = 4.5V, VpD @ Ground unless otherwise noted. 




PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Oscillator Start Voltage 


Ta = 25°C, (Note 1) 


1.40 






V 


Oscillator Sustaining Voltage 


Ta = -5 j C, (Note 1) 


1.30 






V 


Input Voltage Levels 












Set/Display, Cycle 












Start/Stop, Mode 












Logical "1 " 




V DD -0.25 






V 


Logical "0" 


Internal Pull-Down to Vss 




Open 




V 


Test 












Logical "1" 




V DD -0.25 






V 


Logical "0" 


Internal Pull-Down to Vee 




Open 




V 


32 Hz/Backplane 


Test Input = Vqd 










Logical "1 " 




V DD -0.25 






V 


Logical "0" 








Vee+0-25 


V 


12 HR, SW Disable 












Logical "1 " 




V DD ~0.25 






V 


Logical "0" 








VsS+0.25 


V 


Input Current Levels 












Set/Display, Cycle, Start/Stop, 


V|N = VDD 




30 


50 


MA 


Mode, Test 












Input Capacitance 


f = 1 MHz, V| N = 0V, 
All Other Pads Gnd 










OSC OUT 




8 






pF 


OSC Cap 




37 






pF 


All Others 








5 


pF 


Output Current Levels 












Segment Drivers 












Logical "1" Source 


V0UT= V DD -0.2V, 
(VDD-VEE-3V) 


2.0 






uA 


Logical "0" Sink 


V0UT= V EE +0.2V, 
(VDD- V E E = 3V) 


2.0 






IdA 


BP/32 Hz Output 












Logical "1 " Source 


V0UT= V DD -0.2V. 
(VDD- V EE = 3V) 


200 






uA 


Logical "0" Sink 


V0UT = VEE+0.2V, 
(V D D- V E E = 3V) 


200 






HA 


Output Current Levels 












Double, Triple 












Logical "1 ," Source 


V0UT = V DD - 0.25V, 
Phase 2 < 1 ms 


7.5 






MA 


Logical "0," Sink 


V0UT = V S S + 0.25V, 
Phase 3 


35.0 






AlA 



7-21 



electrical characteristics (Continued) 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Cap 1 












Logical "1 ," Source 


V0UT = VDD- 0.25V, 
Phase 1 


7.5 






UA 


Logical "0," Sink 


V0UT=V S S + 0.25V, 
Phase 2 


20.0 






uA 


Leakage 


VOUT = V D D-3.0V, 
Phase 3 






0.6 


/uA 


Cap 2 












Logical "0," Sink 


V0UT = V S S + 0.25V, 
Phase 1 


35.0 






uA 


Leakage 


V0UT=V EE +1.5V, 
Phase 2 






0.6 


M 


VEE 












Logical "0," Sink 


Cap 2 = V D D -4.2V, 
Phase 3 
V0UT=V DD - 3.95V 


250.0 






uA 


Input Debounce 


Test Input Open 










Cycle, Mode 


Osc. In Freq = 32.768 kHz 


120 




260 


ms 


Set ("0" to "1" Transition) 




120 




260 


ms 


Set ("1 " to "0" Transition) 




60 




130 


ms 


Start/Stop 




60 




130 


ms 


Supply Current Odd) 


Ta = 25°C, IeE = 1 MA, 










Doubler Operation 


f = 32,768 Hz, V D D - V S S = 




3.0 


6.0 


uA 


Tripler Operation 


1.6V, (Note 1) 




6,0 


8.0 


HA 


Supply Voltage (V|=e) 


T A = 25°C, C = 0.047 uF, 










Doubler Operation 


lEE = 1 i"A, f = 32,768 Hz, 


2.5 






V 


Tripler Operation 


VdD-V S S= 1-5V, 
(Figure 9), (Note 2) 


3.8 






V 



Note 1 : In oscillator network shown in Figure 4. 

Note 2: External capacitors connected as shown in Figure 9. 



functional description 



A block diagram of the MM5890 chronograph chip is 
shown in Figure 1 with the chip pad layout shown 
in Figure 2. 



Time Base: The precision time base of the chronograph 
is provided by connecting a crystal controlled RC net- 
work to the on-chip CMOS inverter/amplifier as shown 
in Figure 3. For proper operation the network should be 
tuned to 32.768 kHz. Resistor R1 is used to bias the 
on-chip inverter for class A amplifier operation. Resistor 
R2 is used to: a) reduce the voltage sensitivity of the 
network; b) limit the power dissipation in the quartz 
crystal: and c) provide added phase shift for good 
start-up and low voltage operation. Capacitors C1 and 
C2 in series provide the parallel load capacitance required 
for precise tuning of the quartz crystal. The network 
shown in Figure 4 provides greater than 100 ppm 
tuning range when used with standard X-Y flexure 
quartz crystals trimmed for C[_ = 13 pF. Tuning to 
better than 2 ppm is easily obtainable. The 32 Hz output 



can be used to monitor the oscillator frequency during 
initial trimming without disturbing the network itself. 



DISPLAY CONTROL 

Watch Mode: When used as a watch, the MM5890 has 
two display modes. The first mode displays the HOUR 
in digit positions 1 and 2, the MINUTE in digit positions 
3 and 4, the DATE in digit positions 5 and 6 and the 
DAY-OF-THE-WEEK /Figure 5). The second mode will 
display SECONDS in digit positions 5 and 6 instead of 
the DATE. Depressing the Set/Display switch will change 
the watch from one mode to the other. 

Leading zero values of the DATE and HOUR are 
blanked. The circuit contains a 4 year calendar which 
will automatically reset the Date Counter to 1 and 
advance the Month Counter at the end of each month 
(except for February in Leap Year). The character 
display font is shown in Figure 6. 



7-22 



functional description (continued) 



108.3 124.3 1403 



156 3 172.3 TEST 





5.5 


324 


! 52.5 81. B 


100.3 


16.3 132.3 I 

I I I I 


4B.3 I 


164.3J/8.5 


5.5 


□ □ 

v EE | 


□ 
CAP 2 


DDDD 

CAP 1 SET 1 


□ a a a □ a a a nao 

V DD V SS CYCLE'MOOE / M 


19.6 


TRIPLE 
□ A1/D1 




DOUBLE DSC 
IN 


0SC 1 
OUT 


HR SW 
DISABLE 


S,'S 


P/32 __ 
Hi G1 a 


29.6 


Q Bt 












ElD 


40.6 


QF2 












ci D 


51.6 


CA2 
□ B2 






190 






G2Q 




MILS 




73.6 
846 
956 


D SPLIT 

□ SUN 

□ MON 




MM5B9D 

LCD CHRONOGRAPH 

(ALL PADS AHE 5.0X5.0 MILS MINIMUM) 




E2D 
D2 □ 

C2 a 


106.6 
117.6 


□ TUES 

□ WEO 






t 






COLON G 
MONTH □ 


128.6 
132.6 


□ thur 

D Fflt 






1 
195 MILS 

1 






G3D 
E3D 


IBfl.6 


DSAT 












A3/D3 D 


161.6 


D D5 






T 






C3Q 


172.6 


DE5 












F4Q 




G5 F5 A5 
ODD 


B5 C5 G6 F6 A6 B6 C6 D6 E6 F3 B3 A4 B4 C4 04 

DnnanannaDDannn 


G4 a 

E4Q 








: i i 











18.1 ! 369 55 7 74 5 93.3 



1121 130.9 j 149.7 . 170 
102.7 121.5 1403 161.1 



145.5 
156.5 
1675 
178.5 



oo 

CO 

o 



FIGURE 2. Chip Pad Layout 



SW START/ BP/32 

12 HR V SS REJ CYC STOP M00E TEST 



1G IE 1C 2G !E 20 2C COLON MONTH 3G 3E 3A/3D 3C 4F 4G 4E 40 4C 4B 4A 



3F 6E 60 6C 



|68 |67 |&6 \ii [64 |s3 1 62 J61 |b0 |s9 j&fl j 57 |s6 |s5 \S4 |53 j 52 [51 |s0 j 49 |4B ]47 |46 |45 [44 \»3 \i2 )41 [40 |39 \3i J37 [36 |3S 




m m m Tu I15 lie ITt lia m [20 [21 [22 [23 T24 [25 m Trim m ho hi I32 pi Im 

Vqq OSC 0SC SET I CAP 1 CAP2 I V EE 1A/1D IB 2F 2A 2E SPLIT SUN MON TUE WED THU FRI SAT 5D 5E SG NC 5F 5A SB 5C 6G 6F 6A EB 
OUT IN I I 

DOUBLE TRIPLE 



FIGURE 3. Connection Diagram 




S Ml T W T F S 
U Q U E H R A 



,<^->,,. 



HOURS 
STOPWATCH 
MINUTES 



MINUTES 
STOPWATCH 
SECONDS 



FIGURE 4. Crystal Oscillator Network 



FIGURE 5. Display Format 



7-23 



functional description (continued) 




FIGURE 6. Display Font 



Stopwatch Mode: Depressing the Mode Switch will 
switch the watch from the normal watch mode to the 
stopwatch mode. When used as a stopwatch, the 
MM5890 displays the stopwatch MINUTE in digit posi- 
tions 1 and 2, the stopwatch SECOND in digit positions 
3 and 4, and the stopwatch 1/100 SECOND in digit 
positions 5 and 6. Depressing the Start/Stop Switch will 
either start the stopwatch if it is not counting or stop 
it if it is counting. 

Depressing the Set switch will activate the Split Time 
mode. In this mode the watch will freeze the time 
showing on the display at the instant the Set switch is 
depressed. The stopwatch continues counting and the 
colon will begin blinking at a 1 Hz rate to indicate the 
continuing count. Depressing the Start/Stop switch will 
stop or start the stopwatch counters. The colon will 
remain "ON" in the Split Time mode if the stopwatch is 
not counting. The Split indicator (refer to Figure 5) will 
be "ON" during the Split Time mode. Depressing the 
Set switch while the watch is in the Split Time mode 
will return the accumulated time in the stopwatch to the 
display and the Split indicator will turn "OFF." 

Depressing the Set switch while the stopwatch is not 
running and is not in the Split Time mode will clear the 
stopwatch counters to a zero count. Depressing the 
Mode switch while the stopwatch mode is active will 
transfer the watch to the normal watch mode. This 
transfer will not affect the stopwatch function and the 
stopwatch will continue performing the same function 
until the stopwatch mode is again activated with the 
mode switch. 



MINUTE: Depressing the Cycle switch while the watch 
is in the Set Hour mode will put the watch in the Set 
Minute mode with the MINUTE information displayed 
in digit positions 3 and 4. Depressing the Set/Display 
switch will advance the MINUTE counter at a 1 Hz rate 
and activate the Hold mode. 

DAY-OF-THE-WEEK: Depressing the Cycle switch 
while the watch is in the Set Minute mode will place it 
in the Set Day mode with the DAY-OF-THE-WEEK dis- 
played. Depressing the Set/Display switch will change 
the DAY-OF-THE-WEEK at a 1 Hz rate until the switch 
is released. 

DATE: Depressing the Cycle switch while the watch is 
in the Set Day mode will advance it to the Set Date 
mode with the DATE (day of the month) displayed in 
digit positions 5 and 6. Depressing the Set/Display 
switch while the watch is in the Set Date mode will 
advance the DATE at a 1 Hz rate until the switch is 
released. 

Month: Depressing the Cycle switch while the watch is 
in the Set Date mode will advance it to the Set Month 
mode with the Month displayed in digit positions 5 and 
6 and the Month indicator "ON." Depressing the Set/ 
Display switch while in this mode will advance the 
Month counter at a 1 Hz rate until the switch is released. 

Depressing the Cycle switch while the watch is in the 
Set Month Mode will place the watch in the normal 
display mode with HOUR, MINUTE, DATE, and DAY- 
OF-THE-WEEK information displayed. 

Hold: If the Hold mode was activated while in the Set 
Minute mode the colon will not blink in the normal 
time display but remain on continuously. The SECOND 
counter is held at 00, forcing the watch to remain at the 
displayed time. Depressing the Set/Display switch will 
switch the watch to the alternate time display mode 
(HOUR, MINUTE, SECOND, and DAY-OF-THE-WEEK) 
and release the SECOND counter allowing normal 
operation to begin. While in any of the Set modes, 
advancing the selected counter will not cause a roll-over 
of higher state counters. For example, advancing the 
HOUR counter from 11 PM to 12 AM will not cause the 
DATE or DAY-OF-THE-WEEK counters to advance. 

A control state diagram for the MM5890 is provided in 
Figure 7 . 



Setting Control: A normally open switch connected to 
the Cycle input is used in conjunction with the Set/ 
Display input to set the MONTH, DATE, DAY-OF- 
THE-WEEK, HOUR, MINUTE and synchronize the 
SECOND information. 



HOUR: With the watch in the watch mode depressing 
the Cycle switch will put the watch in the Set Hour 
mode. The HOUR information will be in digit positions 
1 and 2 with either an A or a P in digit position 4 
indicating AM or PM. While in this mode, depressing the 
Set/Display switch will cause the HOUR counter to 
advance at a 1 Hz rate until the switch is released. 



Contact Bounce: Debounce circuitry is provided on the 
Set/Display, Cycle, Start/Stop, and Mode inputs to 
remove any logic uncertainty upon either closure or 
release of switches provided switch bounce settles 
within 120 ms (Set/Display release bounce must settle 
within 60 ms.) 

12/24 Hour Option: 12/24 hour operation is controlled 
by the logical state of the 12 HR pad. Connecting the 
12 HR pad to a logical "1" will cause the watch to 
operate in the 12 hour mode while connecting the 
12 HR pad to a logical "0" will cause the watch to 
operate in the 24 hour mode. 



7-24 



functional description (Continued) 

Segment Outputs: The Segment outputs are designed to 
drive field-effect liquid crystal displays. Each display 
segment has its own output which supplies the proper 
32 Hz drive signal. By definition, the segment is "OFF" 
when its drive signal is in phase with the Back Plane 
drive signal (BP/32 Hz) and the segment is "ON" when 
the drive signal is 180° out of phase with the Back Plane 
drive signal (refer to Figure 8). 



BP/32 Hz: This input/output pad is under control of 
the Test input. When Test is open or at a logical "0," 
a 32 Hz signal is provided at BP/32 Hz which is used to 
drive the backplane of the LCD unit or to monitor the 
oscillator frequency. If Test is at a logical "1," the 
BP/32 Hz pad is converted into an input and any fre- 
quency connected to it will replace the normal internal 
32 Hz signal. This feature allows high speed testing of 
all timekeeping and stopwatch counters. 













SET 








DISPLAY 

DAY DATE 

HOUR : MINUTE 


DISPLAY 

DAY SECOND 

HOUR : MINUTE 




(CLEAR 
HOLD) 

"set ' 






i 


CYCLE 










f i 


' 


SET 








DISPLAY HOUR 
WITH A OR P 


ADVANCE 
HOUR 


SET 




i 


p CYCLE 






DISPLAY MINUTE 


ADVANCE 

MINUTE 

SET HOLD MODE 


SET 




1 


p CYCLE 






DISPLAY 
DAY-OF-WEEK 


ADVANCE 
DAY-OF-WEEK 


SET 




1 


p CYCLE 






DISPLAY 
DATE 


ADVANCE 
DATE 


SET 




1 CYCLE 






DISPLAY 


ADVANCE 






MOP 


JTH 






MOP 


JTH 



RESET 
COUNTERS 



( | MODE | ) 



SET 



DISPLAY 

MINUTE : SECOND 

1/100 SECOND 

HOLD COUNT 



I START J" 
^ /STOP | 



SET 



DISPLAY SPLIT TIME 

MINUTE : SECOND 

1/100 SECOND 

HOLD COUNT 



DISPLAY 

MINUTE : SECOND 

1/100SECOND 

STOPWATCH 

COUNTING 



SET 



SET 



I START ▲ 
/STOP | 



DISPLAY SPLIT TIME 

MINUTE : SECOND 

1/100 SECOND 

STOPWATCH 

COUNTING 



FIGURE 7. Control State Diagram 



BACKPLANE 



^OD I r 

v E e I 1 



1_ 



SEGMENT 



"DD 



"EE 



~LJ 



-OFF- 



-0N- 



FIGURE 8. Phase Drive Signals 



7-25 



o 

05 
00 

IT) 

1 



functional description (Continued) 

Test: This input is used to control the BP/32 Hz pad as 
described above. When Test is at a logical "1" the 
phase-control is disconnected from the segment drive 
outputs and the segment information is referenced to a 
logical "0" backplane. Switching the Test input from a 
logical "0" to a logical "1" generates a reset pulse that 
will reset the counters to Sunday, 1 AM on January the 
first. All stopwatch counters will be set to 00 and the 
watch will be placed in the normal time display mode. 



SW Disable: This input is used to control accessability 
to the stopwatch functions. If SW Disable is at a logical 
"0" the Mode switch can be used to activate the stop- 
watch functions. If SW Disable is at a logical "1" the 
Mode switch is inoperative and the stopwatch functions 
are locked out. 



536 pF 







\Y 






> Vddorv ss 






M 








32.768 kHz 


^Z^ 50pFTYP 






IMI 

osc *-* 

IN 


osc 

OUT 




v D d 






OSC 
CAP 


12 HP. 
















START/STOP 


— O O— i 


















SET/DISPLAY 


— O O— ll 








CYCLE 


_L 

— O O— i) 








MODE 


-o- 1 "^ 




DISPLAY 
UNIT 


51 

SEGMENT 

OUTPUTS 

1 


MM5890 


DOUBLE 
TRIPLE 




L 

0.05mF 


J 
1 








CAP 2 


_^ 0.05/jF 






BP 

SW DISABLE 


VEE 

Vdd 
vss 


0.0E 

T 


mF 

+ 






t 


























0.05 (l/F 



FIGURE 9. Typical Application 



7-26 



a 



Watches 



MM58104 direct drive LED watch 
general description 

The MM581 04 is a low threshold voltage, ion-implanted, 
metal-gate CMOS integrated circuit that provides or 
controls all signals needed for a 3 1/2 digit 3-function or 
a 4-digit 4-function LED watch. The display format is 
12 hours. The circuit time base is a 32,768 Hz crystal 
controlled oscillator. This time base frequency is suc- 
cessively divided to provide drive signals for a multi- 
plexed 7-segment LED display. Upon demand MM58104 
will display HOURS-MINUTES or SECONDS when it 
is used as a 3-function watch and will also display DATE 
when it is used as a 4-function watch. The outputs will 
directly drive a 7-segment LED display. The device 
operates from a single 2.4V to 4.0V supply. The 
MM58104 is available as unpackaged die suitable for 
hybrid assembly or in 40-lead dual-in-line packages 
for evaluation purposes. 



features 

■ 32,768 Hz crystal control oscillator 

■ Single 3V supply 

■ Low power dissipation (1 5/liW typical) 

■ 3 1/2 digit (3-function) or 4-digit (4-function) option 

■ 1 2 hour display format 

■ Simple display/set controls 

■ Direct drive outputs for LED's 

■ Display brightness control 

■ On-chip oscillator bias network 

functional description 

A block diagram of the MM58104 digital watch chip is 
shown in Figure 7. A chip pad layout is shown in 
Figure 2 and package connection diagram in Figure 3. 



2 
00 

o 



block diagram 



chip pad layout 



nsc in o [>>-t> ",( 

DSC OUT O 1 ♦_ 

LAMP O— • 1 



L 



IS 



DIGIT 

CONTROL 

LOGIC 



H 



7 SEGMENT DECODE 



TT 



COUNTER SELECT LOGIC 



A B C D E F G 



connection diagram (Top view) 







136 5 — 


Dv DD □ 


n 




□ a 


D 


□ a 








SEG g 


SEG 




SEGj SEG a 


0IS4 


DISS SET 






113.05 - 


□ SEG d 
















93 3 — 


□ SEG C 












142.0 
MILS 


70.4 - 


□ sEG e 






MM5B104 
DIMENSIONS TO 














CENTER OF PADS 






| 


56. rj — 


□ LAMP 












i 


48 6 


O TEST 














41. — 


n<Hz 














33. S - 


□ colon 














25 55- 


D DIM 














16.75 — 


□ 4096 






V SS 

DT 




CAP 

OSC OSC 






DIG 1 


DIG 


fCYCLE DIG 3 




DIG4 ( OUT IN 








D 




U 


DD □ 




□ a a a 




49.85 65 35 



DISPLAYS 
4 3 SET \C NC NC NC NC NC NC 



115.75 I 130.75 

12325 14025 



37 1 36 |35 1 34 ] 33 1 32 1 31 1 30 | J9 1 28 \ll | J6 1 25 1 24 \ 23 1 22 \2 



TEST 4 Hz/ COLON DIM 4096 NC 
TEST Hz 

FRED 



TTTTTT 



DIGITS 

FIGURE 3. 



7-27 



absolute maximum ratings 










Voltage at Any Pin 


V ss -0.3V to V DD +0.3V 










Operating Temperature Range 


-5°C to +70°C 










Storage Temperature Range 


-25°C to +85°C 










v DD -v ss 


5V max 










Lead Temperature (Soldering, 10 secon 


ds) 300°C 










electrical characteristics 












T A within operating temperature range 


V ss = GND, 2.4 < V DD < 4.0V, unless otherwise noted. 








PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Oscillator Start Voltage 


T A =25°C 


2.7 






V 


Input Voltage Levels @ Display 3, 


V D d =3.0V 










Display 4, Set 












Logical "1" 




1/2 V DD 




Vdd 


V 


Logical "0" 


300 kfi Internal Pull-Down to V ss 




Open 






Input Voltage Levels @ 4 Hz/ 


V DD =3.0V 










Test Freq, Dtcycl 












Logical "1 " 




V D D -0-25 




Vdd 


V 


Logical "0" 




Vss 




V ss +0.25 


V 


Input Voltage Levels @ Lamp, Test 


V D D=3.0V 










Logical "1 " 


1 M!T2 Internal Pull-Up to V DD 




Open 






Logical "0" 




Vss 




V ss +0.25 


V 


Input Current @> Display 3, Display 4, Set 


Vin =V DD , Sink Only, V DD -3.0V 




30 


50 


uA 


Input Current @ Lamp and Test 


Vin = V ss , Source Only, V DD = 3.0V 




30 


50 


pA 


Output Current Levels @ Segment Drivers 


V OD =2.7V 










"ON" Source 


Vout-V dd -0.5V 


7 


10 


15 


mA 


"OFF" 


Vout = V ss +1.1V 






50 


uA 


Output Current Levels @ Digit Drivers 


V D D = 2.7V 










"ON" Sink 


Vout = V ss + 0.6V 


50 


70 




mA 


"OFF" 


V OUT = 2.0V, All Digit Drivers 
Tied in Parallel 






2 


MA 


Output Current Level @ COLON 


V DD =2.7V 










"ON" Sink 


Vout = V SS + 0.7V 




6 




mA 


"OFF" 


Vout = V DD -1.6V 






0.5 


juA 


Output Current Levels <a 4096 Hz, 


V DD = 3.0V 










4 Hz/Test Freq. 












Logical "1 ," Source 


Vout=V dd ~ 0- 5V 


10 






uA 


Logical "0," Sink 


Vout = V ss + 0.5V 


10 






MA 


Supply Current Odd) 


f = 32,768 Hz, T A = 25°C, 

V DD = 3.0V, Unused Inputs Open, 

Outputs Open 




5 


10 


^A 


Supply Current (l DD l 


T A = 25°C, V ss , OSC IN & Dtcycl @GND, 
V DD = 3.0V, Unused Inputs Open, 
Outputs Open 




0.05 


1 


uA 


Input Capacitance 


f = 1.0 MHz 










OSC OUT 


V| N - 0.0V 




8 




pF 


CAP 


All Other Pads GND 




37 




pF 


All Others 








5 


pF 


Input Voltage Level @> DIM 


V DD =3.0V 










Positive-Going Threshold (V T , ) 






15 




V 


Negative-Going Threshold { V T . ) 






1.0 




V 


V T , - V T ._ Hysteresis 






0.5 




V 


Input Current® DIM 


Vin = V ss , V DD = 3.0V, Source Only 






0.3 


MA 



7-28 



functional description (con't) 



Time Base: The precision time base of the watch is 
provided by the interconnection of a 32,768 Hz quartz 
crystal and the RC network shown in Figure 4 together 
with the CMOS inverter/amplifier provided between the 
oscillator in and oscillator out terminals. Resistor R1 is 
necessary to bias the inverter for class A amplifier 
operation. Resistor R2 is required in order to (a) reduce 
the voltage sensitivity of the network; (b) limit the 
power dissipation in the quartz crystal; and (c) provide 
added phase shift for good start-up and low voltage 
circuit performance. Capacitors C1, C2 and C3 provide 
the parallel load capacitance required for precise tuning 
of the quartz crystal. The RC network except the trim 
capacitor C3 is integrated on-chip. 

The network shown provides > 100 ppm tuning range 
when used with standard X-Y flexure quartz crystals 
trimmed for C L = 1 2 pF. Tuning to better than ±2 ppm 
is easily obtainable. 



7-segment outputs of the MM58104 are designed to 
interface directly with the NSC0101 LED display. The 
four digits of the LED display are multiplexed with a 
25% duty cycle, 1024 Hz signal during Display. The 
digit drivers are turned off by the internally generated 
inter-digit blanking signal during the change of digits to 
allow the segments to change without "ghosting" of 
the Display. When MM58104 is used as shown in the 
typical application of Figure 6, the segment on currents 
are typically 9 mA. The NSC0101 LED Display gives 
excellent brightness under these drive conditions. 

The switch inputs "Display 3" and "Display 4" of the 
MM58104 are to be used for 3 and 4-function LED 
watches, respectively. However, "Display 3" can be 
connected to an inertial switch for HOURS-MINUTES 
Display in a 4-function watch. In subsequent paragraphs, 
the term "Display" will take the place of "Display 3" 
and/or "Display 4," unless otherwise specified. 



The 4096 Hz output or 4 Hz output can be used to 
monitor the oscillator frequency during initial tuning 
without disturbing the network itself. 

Display Multiplexing: Outputs from each counter are 
time-division multiplexed to provide digit-sequential 
access to the time data. Thus, instead of requiring 28 
leads to interconnect a four digit (7 segments/digit) 
watch, only 11 output leads are required. The character 
display font and segment identification is shown in 
Figure 5. Figure 6 shows the interconnection of a LED 
watch system. The 4-digit outputs, colon output and the 



Time Display: The DATE and HOUR-MINUTES/ 
SECONDS displays are controlled by a normally open 
switch connected to "Display" input as shown in Figure 
6. DATE or HOUR is displayed in digit positions 1 and 
2. MINUTE or SECOND is displayed in digit positions 
3 and 4. Colon output will be "ON" except when the 
Display involves DATE. The two colon dots are to be 
connected in parallel with their anodes to V DD and 
cathodes to the "COLON" output. 

Closure of the "Display" switch will cause HOUR- 
MINUTES to be displayed for 1.25 ±0.125 seconds. 




FIGURE 4. Crystal Oscillator Network 



7-29 



functional description (con't) 



Holding the "Display" switch closed after the time-out 
of HOUR-MINUTES display will cause SECONDS to 
be displayed until the "Display" switch is open. SEC- 
ONDS will blink while displayed. Each value is visible 
for, 0.25 second and blank for 0.75 second. HOURS 
digits can display values 1—12 with an AM indicator, 
which is the F segment of digit 1. Leading zero values 
of hours are blanked. MINUTES or SECONDS digits 
can display values from 00 to 59. All zero values of 
minutes or seconds are displayed. 

Closure of the "Display 4" switch twice before the 
time-out of HOURS-MINUTES display will cause 
DATE to be displayed for 1.25 ±0.125 seconds. Holding 
the "Display" switch closed will continue DATE display 
until the switch is open. Date digits can display values 
from 1 to 31. Leading zero values of Date are blanked. 

Time Setting: A normally open switch connected to 
the "Set" input is used in conjunction with the "Dis- 
play" switch to set date, hours, minutes and synchronize 
seconds. 

DATE: Closure of the "Display 4" switch twice and 
holding it closed will cause DATE to be displayed 



continuously. Closure of the "Set" switch will then 
advance DATE at a 2 Hz rate until the "Set" or both 
switches are opened. Seconds, Minutes and Hours 
counters continue normal counting during this condition. 

HOURS: Closure of the "Set" switch will cause HOURS- 
MINUTES to be displayed and will advance HOURS at a 
2 Hz rate until the "Set" switch is opened. Seconds and 
Minutes counters continue normal counting during this 
condition. 

MINUTES: Closure of both "Display" and "Set" 
switches will cause HOURS-MINUTES to be displayed 
and will advance MINUTES at a 2 Hz rate after both 
switches have been closed for 0.75 to 1 .0 seconds. When 
the minutes count is correct, opening the "Set" switch 
while keeping the "Display" switch closed will cause 
HOURS-MINUTES to be displayed and Hold the watch. 
HOURS-MINUTES will blink while displayed, visible 
for 0.25 second and blank for 0.75 second. The seconds 
counter is reset and held at 00 during Minutes setting 
or during the Hold Mode. All counters resume their 
normal counting when both "Set" and "Display" 
switches are opened. With the "Display" switch closed. 



:u 



CZJ 



"II I 
'r 


" 


I 1 










L I 


I I 





I l l 1 



I I 



SEGMENT IDENTIFICATION 



"II 1 

g 

i-— 'r 

.k L 



FIGURE 5. Character Display Font 



7-30 



functional description (con't) 



a closure of the "Set" switch for less than 0.75 second 
will reset the seconds counter to 00 without advancing 
the minutes. 

There is no roll-over of the higher counters while the 
lower time counters are being set. For example, while 
setting Minutes a 59 to 00 transition will not advance 
the Hours counter. 

Contact Bounce: Debounce circuitry is provided on the 
"Display" and "Set" inputs to remove any logic uncer- 
tainty upon either closure or release of switches provided 
switch bounce settles within 20 ms. 



Test Points: Four pads are provided for test purposes. 

4096 Hz: is an output. A 4096 Hz symmetrical signal 
is brought out for oscillator tuning. 

4 Hz/TEST FREQ: is an input/output under the control 
of "TEST." When "TEST" is open or at a logical "1," a 
4 Hz signal will appear on the "4 Hz/TEST FREQ 
pad." If "TEST" is at a logical "0," the "4 Hz/TEST 
FREQ pad" becomes an input and any frequency 
connected to it will replace the normal internal 4 Hz 
signal. This feature is provided to allow high speed 
functional testing of the watch system. 



Display Brightness Control: The display brightness is a 
function of digit on-time which is a fraction of the digit 
multiplexers. The digit on-time varies from 1/8 to 7/8 
of the digit multiplexer in steps depending on the logical 
levels of both "DIM" and "DTCYCL" inputs as shown 
in Table I. The "DIM" input has an internal pull-up 
resistor which will hold the open input at a logical 
"1." The logical levels at the "DIM" input can be 
established by a network as shown in Figure 6. 



TEST: is an input. It is used to control "4 Hz/TEST 
FREQ" as described above. An internal pull-up resistor 
will normally hold the "TEST" input to a logical "1." 

LAMP: is an input. When "LAMP" is at logical "0," all 
segments will be forced to an "ON" condition under 
control of the normal 25% duty cycle of the digit 
drivers. An internal pull-up resistor will normally hold 
the "LAMP" input to a logical "1 ." 



r 



L 



(PHOTO TRANSISTOR) 



DTCYCL 
SEGMENTS DIGITS 

Vss a-g COLON 1-4 



COLON 
ANODES 



<2L 




*dd "" «ss 



3Z 



NSCD101 
LED DISPLAY 



The DOT in the first digit is tied to segment bus "f ." 

tt is used as the AM indicator. 

FIGURE 6. Typical Application of MM 58 104 in LEO Digital Watch System 



TABLE I. Display Brightness Control 



DTCYCL 


DIM 


DIGIT ON-TIME 
(Fraction of Digit Multiplexer) 


1 


1 


7/8 


1 





2/8 





1 


4/8 








1/8 



7-31 



in 

oo 
in 



^ 



Watches 



MM58115 digitally tuned direct drive 6 
general description 

The MM58115 is a low threshold voltage, ion-implanted, 
metal-gate CMOS integrated circuit that provides or 
controls all signals needed for a 4-digit, 6-function LED 
watch. The display format is 12 hours. The circuit time 
base is a 32,768 Hz crystal controlled oscillator. This 
time base frequency is successively divided to provide 
drive signals for a multiplexed 9-segment, alphanumeric 
LED display of HOURS-MINUTES, DAY-DATE, 
MONTH-DATE or SECONDS upon demand. A month 
counter is provided to control the count sequence of 
the Date counter. Inputs are also provided to digitally 
tune the time base (i.e., no tuner capacitor is required) 
The MM58115 uses one button for display purposes 
Both segment and digit outputs can be directly inter 
faced with 100 mil LED displays of the NSC9101 type 
Special circuitry is included to provide uniform digit-to 
digit brightness. The device operates from a single 2.4V 
to 4V supply. The MM581 15 is available as unpackaged 
die suitable for hybrid assembly or in a 40-lead dual-in- 
line package for evaluation purposes. 



function LED watch 
features 

■ No external parts except the battery, LED display 
and crystal 

■ Single button display control 

■ Direct drive outputs 

■ Digital tune network 

■ Uniform display brightness 

■ 32,768 Hz crystal controlled operation 

■ Single 3V supply 

■ Low power dissipation OOjuW typ) 

■ Seconds, Minutes, Hours, Day-of-Week, Date and 
Month operation 

■ 4 year calendar 

■ 4-digit, 6-function, 12-hour display format 

■ Simple display/set controls 

■ Alphanumeric display 

■ Display brightness control 

■ AM/PM indication during set hours 

■ Month indication during set month 

■ Test features 



block diagram 



mil 



P4 P8 8 SECONDS TEST 
9 



13 STAGE DIVIDER 



CAP1 O— 
CAPZ O— 



-X 



111! 



rz^ 



Ul I u 



iflTE fc MOW 



COUNTER T CUUNTFR ~ *■ COUNTER |~" * COUNTER 



COUNTfcti SELECT 



9-SEGMENT 

UECOQE AND 

BUFFERS 



Txxxxxrrr 

A B C D E F G H I 
SEGMENTS 

FIGURE 1. 



7-32 



absolute maximum ratings 












Voltage at Any Pin 


Vss -0.3V to VDD + 0-3V 










Operating Temperature Range 


-5°C to +70°C 










Storage Temperature Range 


-25°C to +85°C 










vdd - vss 


5V max 










Lead Temperature (Soldering, 10 seconds) 


300°C 










electrical characteristics 












Ta within operating temperature range, Vss = Gnd, 2.4 < Vdd < 4V unless otherwise noted 








PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Oscillator Start Voltage 


T A = 25°C 


2.7 






V 


Input Voltage Levels at Cycle, 












Set/Display, Hour/Min 












Logical "1" 


100kn Internal Pull-Down 


1/2V DD 




vdd 


V 


Logical "0" 


to Vss 




Open 






Input Voltage Levels at 4 Hz/ 












Test Frequency 












Logical "1" 




VdD-0-25 




v D d 


V 


Logical "0" 




vss 




Vss+025 


V 


Input Voltage Levels at Lamp, Test 












Logical "1" 


100 kfi Internal Pull-Up to Vqd 




Open 






Logical "0" 




vss 




Vss+0.25 


V 


Input Voltage Levels at Duty Cycle 












Logical "1 " 


No Pull-Up (Must Be Bonded) 




v D d 




V 


Logical "0" 






vss 




V 


Input Voltage Levels at Dim 


Duty Cycle = Vss 










display duty cycle = 21 .875% 


5 MJ] Pull-Down to Vss 


Open 




Vss+O.3 


V 


display duty cycle = 9.375% 




VdD-0-5 




v D d 


V 


Input Voltage Levels @ A/D, P1-P8 


10 Mil Internal Pull-Down to 










Logical "1" 


vss 


V D D-0.25V 




vdd 


V 


Logical "0" 






Open 






Input Current at Cycle, Set/Display, 


V DD = 3V, V| N = V DD , 




30 


50 


ma 


Hour/Min 


Sink Only 










Input Current at Lamp, Test 


V D D = 3V,V| N = VsS, 

Source Only 




30 


50 


ma 


Input Current @ A/D, P1 , P2, P4, P8 


V DD = 3V, V| N = V DD 










Logical "1" 








350 


nA 


Logical "0" 












Input Capacitance 


f = 1 MHz, V|N = 0V, All Other 
Pads Gnd 










Osc. Out 






8 




pF 


CAP 1 






37 




pF 


CAP 2 






15 




pF 


All Others 








5 


pF 


Output Current Levels at Segment Drivers 


V D D = 2.7V 










"ON," Source 


vout = v D d - o.5v 


7 


10 


15 


mA 


"OFF," Leakage 


vqut = v D d -1-1V 






50 


MA 



2 

00 

-a 
<J1 



7-33 



electrical characteristics (Continued) 



PARAMETER 



CONDITIONS 



MIN 



TYP 



MAX 



UNITS 



Output Current Levels at Digit Drivers 
"ON," Sink (6 or 7-segment display! 
(5 or 4-segment display] 
(1, 2 or 3-segment display) 
"OFF," Leakage 

Output Current Levels at 4 Hz/Test 
Freq, 4096 Hz, 8 Sec. 

Logical "1," Source 

Logical "0," Sink 
Supply Current OddI 



Supply Current (Idd) 



V DD = 2.7V 

v OUT = V S S + 0-6V 

If Colon is "ON," Add 2 mA 

to Digit 4 Sink Current 

VouT = 2V, All Digit Drivers 

Tied in Parallel 



VOUT = V DD -0.6V 

VOUT = V SS + 0.6V 

T A = 25°C, f = 32,768 Hz, 

Unused Inputs Open, Outputs 

Open 

Ta = 25°C, Vss, Osc In, Duty 
Cycle Control at Gnd, VqD = 3V, 
Unused Inputs Open, Outputs 
Open 



50 



70 



mA 



10 
10 



60% of 6 or 7-segment current 
46% of 6 or 7-segment current 
2 nA 



iuA 
MA 



3.5 



0.05 



1.5 



MA 



UA 



functional description 

A block diagram of the MM58115 direct drive digital 
watch is shown in Figure 1. The chip pad layout is 
shown in Figure 2 and package connection diagram 
in Figure 3. 

Time Base: The precision time base of the watch is 
provided by the 32,768 Hz crystal controlled oscillator, 
which consists of quartz crystal, a CMOS inverter/ 
amplifier and the RC network shown in Figure 4. 
Resistor R1 biases the inverter for class A amplifier 
operation. Resistor R2 (a) reduces the voltage sensitivity 
of the network; (b) limits the power dissipation in the 
quartz crystal; and (c) provides added phase shift for 
good start-up and low voltage circuit performance. 
Capacitors C1 and CgFF i n series provide the parallel 

16.0 B3.Z 972 130.0 143 



load capacitance required for precise tuning of the 
quartz crystal. The network shown in Figure 4 provides 
greater than 100 ppm tuning range when used with 
standard X-Y flexure quartz crystals trimmed for C|_ = 
12 pF and a 5—36 pF trim capacitor. If digital tuning 
is used, the tuning range is ±114 ppm and no trim 
capacitor is required. 

Cap 1: This pin is used with Oscillator Out to add more 
capacitance to the oscillator RC network shown in 
Figure 4. 

Cap 2: This pin is used with Oscillator In to form the 
RC network shown in Figure 4 if the digital tuning is 
to be used. 



128.Z B 



95 7 Q 



t-r 



]v ss 

JQIG 3 
3 DIG 1 

H 4096 Hi 
] 8 SEC 



MM58115 

NOT TO SCALE 

DIMENSIONS TO CENTER OF PADS 

ALL PADS ARE 5.0 X 5.0 MIL MINIMUM) 



79.3 QP2 

67.3 Q P4 



31.1 QCAPl 



□ □□□□□ mm □ 

j 17.7 | 35.1 | 52.5 | 97.4 ! 



CYCLE SET LAMP 



VddQ 101-2 

BQ- — S5.B 



F Q 61 



A G- 15. Z 



SEGMENT B 




V D — 




SEGMENT G — 




SEGMENT — 




NC 




NC 




NC — 




SEGMENT C — — 




SEGMENT E — 




SEGMENT 1 




DIGIT2 

ir 

NC — 




DIGIT 1 — 




Vss — 




DIGIT 3 — 

16 
DIGIT 4 




4096 Hi — 




8 SECONDS^ 
19 

PI — 
20 

P2 — 





- SEGMENT F 

- SEGMENT H 

- SEGMENT A 



- SET/DISPLAV 

- CYCLE 

- HR/MIN 

- NC 
-TEST 

- 4HI/TESTFREQ 

- DUTY CYCLE CONTROL 



- CAP 2 

- 0SC OUT 



B9.4 105.4 1266 137-6 151.5 



TOP VIEW 

FIGURE 3. Connection Diagram 



FIGURE 2. Pad Layout 



7-34 



functional description (Continued) 

Display Control: The TIME and DATE display sequence 
is controlled by normally open switches connected to 
SET/DISPLAY, and HOUR/MINUTE (inertial switch) 
inputs. With the display "OFF," depressing the SET/ 
DISPLAY switch will activate the HOUR-MINUTE 
display. This display will remain "ON" for 1.25 seconds 
±0.125 seconds. If the switch is still held in at the end 
of this time out, SECONDS will be displayed blinking 
"ON" for 0.25 seconds and "OFF" for 0.75 seconds 
until the SET/DISPLAY switch is released. If during the 
HOUR-MINUTE display, the SET/DISPLAY switch is 
released and depressed a second time, the date will be 
displayed as DAY-DATE. The DAY-DATE display will 
remain "ON" for 1.25 seconds ±0.125 seconds and turn 
"OFF" automatically if the SET/DISPLAY switch has 
been released. Holding the SET/DISPLAY switch past 
the display time out will cause the watch to display 
MONTH-DATE information until the SET/DISPLAY 
switch is released or until the SET/DISPLAY switch has 
been depressed longer than 2.0 seconds ±0.125 seconds. 
If held longer than 2 seconds, the MONTH-DATE dis- 
play will return to DAY-DATE display. MONTH-DATE 
and DAY-DATE display will continue to alternate 
until the SET/DISPLAY switch is released. DAY- 
DATE will be displayed for 1.25 seconds and MONTH- 
DATE will be displayed for 0.75 seconds before the 
sequence starts to repeat. TIME may also be displayed 
in the MM58115 by activating the HOUR/MINUTE 
input. The HOUR/MINUTE input is used with an 
inertial switch that is normally open. Closing the switch 
activates the HOUR/MINUTE display. This display will 
remain "ON" for 1.25 seconds ±0.125 seconds and then 
turn "OFF" automatically. 

Time Setting: The setting sequence is controlled by a 
normally open switch connected to the Cycle Input. 
Depressing the CYCLE switch will advance the watch to 
the next set mode. Figure 5 is a flow diagram showing 
the display and set functions for the MM581 1 5. 

Set Hour Mode: With the watch in the normal Run 
mode and the display "OFF," depressing the CYCLE 
switch will put the watch into the Set Hour Mode. 
In this mode, HOURS will be displayed in digit positions 
1 and 2 followed by the colon. An A or a P will be 
displayed in digit position 4 to indicate AM or PM, 
respectively. Depressing the SET/DISPLAY switch will 
advance the HOURS counter at a 2 Hz rate. If neither 
the SET/DISPLAY switch nor the CYCLE switch are 



depressed for 5.25 seconds ±0.125 seconds, the watch 
will automatically return to the Run mode. Depressing 
the CYCLE switch while in the Set Hours mode will 
advance the watch to the Set Minutes mode. 

Set Minutes Mode: The Set Minutes mode will display 
minutes in digit positions 3 and 4 preceded by the colon. 
Depressing the SET/DISPLAY switch while still holding 
in the CYCLE switch will enable the hold flag but will 
not allow advancement of the MINUTE counter. Depres- 
sing the SET/DISPLAY switch after the CYCLE switch 
has been released resets and holds the SECOND counter, 
enables the hold flag, and advances the MINUTE 
counter at a 2 Hz rate. If neither switch is depressed for 
5.25 seconds ±0.125 seconds while the watch is in the 
Set Minutes mode, the watch will automatically return 
to the Run mode if minutes have not been set. Depressing 
the CYCLE switch while in Set Minutes mode will 
advance the watch to the Set Day Mode. 

Set Day Mode: The Set Day mode will display DAY- 
OF-THE-WEEK in digit positions 1 and 2. Depressing 
the SET/DISPLAY switch while in the Set Day mode 
will advance the DAY counter at a 2 Hz rate. If neither 
switch has been depressed for 5.25 seconds ±0.125 sec- 
conds while in the Set Day mode, the watch will auto- 
matically return to the Run mode if the hold flag was 
not set or will jump to the Hold mode if the hold flag 
was set. Depressing the CYCLE switch while in the Set 
Day mode will advance the watch to the Set Date mode. 

Set Date Mode: The Set Date mode will display DATE 
in digit positions 3 and 4. Depressing the SET/DISPLAY 
switch while in the Set Date mode will advance the 
DATE counter at a 2 Hz rate. If neither the SET/ 
DISPLAY nor the CYCLE switches have been depressed 
for 5.25 seconds ±0.125 seconds while in the Set Date 
mode, the watch will automatically return to the Run 
Mode if the hold flag was not set. Depressing the CYCLE 
switch while in the Set Date mode will advance the 
watch to the Set Month mode. 

Set Month Mode: The Set Month mode will display 
MONTH in digit positions 3 and 4 and an M in digit 
position 1. Depressing the SET/DISPLAY switch while 
in the Set Month mode will advance the MONTH counter 
at a 2 Hz rate. If neither the SET/DISPLAY nor the 
cycle switches have been depressed for 5.25 seconds 
±0.125 seconds while in the Set Month mode, the watch 




TO COUNTERS 



Note 1 . 32,768 Hz anti-resonant quartz crystal, C[_ = 1 2 pF 




■►to counters 



| »ss 



FIGURE 4(a). Oscillator RC Network 



FIGURE 4(b). Oscillator RC Network If Digital Tuning is Used. 



7-35 



functional description (Continued) 

will automatically return to the Run mode if the hold 
flag was not set, or will advance to the Hold mode if 
the hold flag was set. Depressing the Cycle switch while 
in the Set Month mode will advance the watch to the 
Hold mode if the hold flag was set; otherwise, the watch 
will advance to the Run mode. 

Hold Mode: In the Hold mode the SECOND counter is 
held at 00, and the HOUR-MINUTE display will blink 
"ON" for 0.25 seconds and "OFF" for 0.75 seconds. 
Depressing the SET/DISPLAY switch will place the 
watch in the display HOUR/MINUTE mode for 1.25 
seconds ±0.125 seconds. Depressing the Cycle switch 
while in the Hold mode will advance the watch to the 
Set Hour mode. There is no roll-over of the next higher 
counter while a counter is being set at a 2 Hz rate. 

Month Counter: The MONTH counter provides "smart 
Date." The DATE counter will count 28 days in Feb- 
ruary, 30 in April, June, September and November, 
and 31 in the remaining months. 



Contact Bounce: Debounce circuitry is provided on the 
SET/DISPLAY, CYCLE, and HOUR/MINUTE inputs to 
remove any logic uncertainty upon either closure or 
release of the switches. 100 ms debounce protection is 
provided for SET/DISPLAY and CYCLE inputs and 
200 ms protection is provided for the HOUR/MINUTE 
input. 

Display Multiplexing: The counter data selected to be 
displayed is time-division multiplexed to provide digit- 
sequential presentation to the LED display. This reduces 
the number of outputs required to drive the 4-digit 
display to thirteen (9-segment drivers and 4-digit drivers). 
The display font is shown in Figure S. Figure 8 is a 
schematic diagram of a typical LED watch using the 
MM58115 watch chip. The segment and digit drivers 
are designed to interface directly with the LED display. 
The four digits of the LED display are multiplexed with 
a 23% duty cycle, 1024 Hz signal during the display 
period. The digit drivers are disabled for 32tis at the 
beginning of each digit enable time to allow the segment 




2 COLON 3 



S/0 = SET/DISPLAY 
H/M = HOUR/MINUTE 
C= CYCLE 
= TIME OUT ROUTE 



HOURS 
DAY 






MINUTES (SECONDS) 
DATE (MONTH) 


j; fjr 


- J; 


o 




.''.if 




o 


U Li 






o 








o 




-/ '■: m; 


-ii 














U ^ .w 






i ->; 


- u 






■■ — a 


!: [f 


-? 


o 


HL_ - 


r : n 


tj 


o 


-■ ;: ■ ■ J p 











FIGURE 5(a). MM58115 Flow Diagram 



FIGURE 5(b). Set Display Font 



7-36 



functional description (Continued) 

decoding circuitry adequate time to switch to the next 
digit's information. This eliminates the possibility of 
"ghosting" information between digits. 



Duty Cycle Control: The Duty Cycle Control Input is 
used with the Dim Input to determine the intensity of 
display. The duty cycle range is shown in Figure 7. 



00 



Colon Output: Colon information is present on the 
"h" and "i" segment outputs during digit position 4. 



Dim Input: The Dim Input is a 2 level input. This input 
has a pull-down to VgS to hold it normally at a logical 
"0." In this condition with Duty Cycle Control at Vss 
the display will normally be at maximum intensity. 
With the Dim input at Vqq, the display will be at 
3/7 of the full intensity. If the Dim input is at Vqd 
and the Duty Cycle Control input is at Vss: maximum 
intensity will be 3/7 of full intensity. With the Dim 
input at Vqd, the display intensity will be reduced to 
1/7 of full intensity. Figure 7 shows the switching 
threshold ranges for the Dim Input. 



Digital Tuning: To digitally tune the time base, A/D, 
P1, P2 P4 and P8 inputs are used. A/D input either 
adds or deletes pulses into the counter chain. P1, P2, 
P4 and P8 inputs determine the number of pulses to 
be added or deleted from the counter chain in a specific 
time period. Each pulse added or deleted "tunes" the 
time base by 7.6 ppm. An 8-second output pad is 
provided to easily check the time base frequency. When 
A/D is open (internal pull-down to Vss> or at V SS. 
pulses are deleted. If A/D is tied to Vqd. Pulses are 
added into the counter chain. PI, P2, P4 and P8 inputs 
have internal pull-downs to Vss. which is a logical "0." 
When these inputs are tied to Vqd. tne V are at a logical 
"1 ." Table I shows the tuning range for each input code. 
If the Digital Tuning scheme is not used, leave all inputs 
open. 




FIGURE 6. Display Font 



2t.B75%DUTY CYCLE 

9.375% DUTY CYCLE 

3.125% DUTY CYCLE 
90.5^s — 



J L 

_TL_x 



J~L 



Jl_ 



—I U- 3D 5^s 



213.6.^s -±— ■■ 



DUTY CYCLE CONTROL 


DIM INPUT 


DISPLAY TIME/DIGIT 


DISPLAY CONDITION 


v S s 


> V DD -0.5V 


9.375% 


Low Ambient Light 




< Vss + OSV 


21.875% 


High Ambient Light 


VDD 


> V DD -0.5V 


3.125% 


Low Ambient Light 




< VSS + 0-3V 


9.375% 


High Ambient Light 



FIGURE 7. Dim Input Levels 



7 37 



in 

00 

2 



functional description (Continued) 

Test Points: Five pads are provided for test purposes. 

8 Seconds: This output is used with A/D, PI, P2, P4 
and P8 to digitally tune the time base frequency. 

4096 Hz: This pad outputs a 4096 Hz signal that can be 
used for oscillator tuning. 

4 Hz/Test Frequency: This is an input/output pad 
under the control of the Test input pad. When "Test" 
is at a logical "0," the 4 Hz/Test Freq pad becomes an 
input and any frequency connected to it will replace 
the normal internal 4 Hz signal. This feature is provided 
to allow high speed functional testing of the watch 
system. When "Test" is open or at a logical "1," a 4 Hz 
output will appear on the 4 Hz/Test Freq pad. 

Test: This pad is used as an input to control the 4 Hz/ 
Test Freq pad. An internal pull-up resistor will normally 
hold "Test" at a logical "1." Changing the Test input 
from a logical "1" to a logical "0" will generate a reset 
pulse which will set the internal counters to 1 AM on 
Sunday, January the first. The watch is now in a known 
state for testing. 

Lamp: When the Lamp input is at a logical "0," all 
segments of the display will be forced to an "ON" 
condition under control of the normal 23% duty cycle 
of the digit drivers. An internal pull-up resistor will 
normally hold the Lamp input at a logical "1." 



TABLE 


1. Digital Tuning Table 


PI 


P2 


P4 


P8 


Af (ppm) 

















1 











7.63 





1 








15.26 


1 


1 








22.89 








1 





30.52 


1 





1 





38.15 





1 


1 





45.78 


1 


1 


1 





53.41 













61.04 


1 










68.57 




1 


1 
1 








76.29 
83.92 








1 




91.55 


1 





1 




99.18 




1 


1 
1 


1 
1 




106.81 
114.44 



A/D is 1 to add to frequency 
A/D is to slow down frequency 
Procedure: Monitor 4096 Hz output, 
determine frequency shift desired, 
bond A/D, P1 , P2, P4, P8 to the correct 
code. 8 second pad will be at the correct 
frequency. 



-t 



r- 




w 





^ V DD OR , , 

vss 



DUTY CYCLE CONTROL 
DIM 



0SC OUT SEGMENT ENABLE 

CAP 



W - L 
1"£ 



C D E F G H I 



FIGURE 8(a). System Schematic for MM58115 LED Watch 



7-38 



functional description (Continued) 






V D • 






r-: 






«do v ss 

rd hi 



SET/OISPLAY 

CYCLE 

QUTY CYCLE CONTROL 

CAP2 MM58115 

OSC IN 



DIGIT 

ENABLE ' 



OSC OUT 
L- CAP! 



SEGMENT ENABLE 






17 



A B C D E F G H 



2 

00 



FIGURE 8(b). System Schematic for MM58115 Digitally Tuned LED Watch 



7-39 



o 

CM 

T— 

00 

in 



t— 

00 
IT) 

2 



00 
00 

5 



00 

in 




Watches 



MM58117, MM58118, MM58119, MM 
general description 

The MM58117, MM58118, MM58119, and MM58120 
are low threshold voltage, ion implanted, metal-gate 
CMOS integrated circuits that provide or control all 
signals needed for a 3-1/2 digit LCD watch. The circuit 
time base is a 32,768 Hz crystal controlled oscillator. 
This time base frequency is counted down to provide 
proper signals to display Hours-Minutes information 
continuously with Month-Date or Seconds information 
available upon demand. Time is displayed in 12 hour 
format. 23 phase controlled outputs are available for 
direct drive of a 3-1/2 digit liquid output display (LCD). 
The 32 Hz output serves as the backplane drive for the 
LCD. All four parts operate on a single 1. 3-1. 7V supply. 
An on-chip voltage multiplier using external capacitors 
is used to provide the drive voltage for the display. 
The MM58117 and MM58118 have on-chip voltage 
doublers which provide 2.5V minimum at 1(jA load 
current. The MM58119 and MM58120 have on-chip 
voltage triplers which provide 3.8V minimum at 1,uA 
load current. Alternatively, the MM581 17 and MM581 19 
provide a 256 Hz output pulse and the MM58118 and 
MM58120 provide a 1024 Hz output pulse that can be 
used to drive an inductive up-converter off chip. The 
Regulate input can be used to suppress this output 



58120 LCD watch circuits 

pulse to regulate the voltage generated. The Regulate 
pad is not present on the MM581 17, MM581 19 versions. 
A Test input can be used to convert the 32 Hz output 
into an input for testing the divider circuitry at a higher 
frequency. All four parts are available as unpackaged 
die suitable for hybrid assembly or in 40-lead dual-in-line 
packages for evaluation purposes. 

features 

■ Direct continuous LCD drive capability 

■ 32,768 Hz crystal controlled operation 

■ Single 1.5V battery operation 

■ Low power dissipation 

■ 3-1/2 digit, 12 hour display 

■ 4 year calendar 

■ Seconds, Month, and Date display upon demand 

■ Colon display 

■ Simple 2 button sequential setting 

■ Auto reset feature (MM581 18 and MM58120) 

■ On-chip capackive voltage multiplier 

■ Regulated bipolar drive also available (MM58118, 
MM58120) 



block diagram 



n 
\°*-&- 



TEST 
O 



^BACKPLANE I/O 

o 



r 



DSC IN O ^>0 " • » 

CSC OUTO ' 





► 


DISP & SET 


CYCLEO 


► 


CONTROL LOGIC 



£=f$ 



■:3 CAP1 CAP 2 



mi 



COUNTER 
SELECT 
LOGIC 



OUTPUT 
SEGMENT 
LATCHES 



_ "\ 2? SEGMENT 

/ OUTPUTS 



7-40 



absolute maximum ratings 

Voltage at OSC IN, OSC OUT, 256/1 024 Hz V DD +0.3V to VsS"0-3V 
Regulator, Set/Display, Cycle, Stop, Phase 3 

Voltage at Any Other Pin VQD+0-3V to VeE~0-3V 

Operating Temperature Range ~5 C to +70 C 

Storage Temperature Range — 25 C to +85 C 

vdd-vee 8 - 0V 

Vdd-vss 3 ° V 

Lead Temperature (Soldering, 10 seconds) 300 C 

electrical characteristics 

Ta within operating range, VpD - V SS = 1 - 5V . V DD - V EE = 4 - 5v unless otherwise noted. 



2 
00 



CO 

00 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Oscillator Start Voltage 


Ta = 25°C, (Note 1) 


1.4 






V 


Oscillator Sustaining Voltage 


Ta= -5°C, (Note 1) 


1.3 






V 


Input Voltage Levels 












Set/Display, Cycle 












Logical "1 " 




VDD-0.25 




VDD 


V 


Logical "0" 


Internal Pull Down to VsS 




Open 




V 


BP/32 Hz Input 












Logical "1" 




Vdd-025 




Vdd 


V 


Logical "0" 




v EE 




V EE +0.25 


V 


Test, Stop 












Logical "1 " 


Internal Pull Down to VeE 


V DD -0.25 




vdd 


V 


Logical "0" 






Open 




V 


Input Current Levels 












Set/Display, Cycle 


V|N = V D D 


0.2 




10.0 


UA 


Test 


V|N = V DD 






15 


uA 


Stop 


V|N = V DD , V E E = V S S^0.3V 






0.5 


/uA 


Input Capacitance 


f = 1 MHz, V|N =0V 






5 


pF 


OSC IN, 


All Other Pads GND 










Output Voltage Levels 












Segment Drivers 












Logical "1" 


VOUT = V D D - 0.2V, V DD - V EE = 3V 


4 






/jA 


Logical "0" 


VOUT = VEE + 02V, V DD - V E E = 3V 


4 






HA 


BP/32 Hz Output 












Logical "1 " 


VOUT = V D D - 0.2V, V DD - V E E = 3V 


40 






uA 


Logical "0" 


VOUT = V EE + 0.2V, V DD - V E E = 3V 


40 






flA 


256/1024 Hz 












Logical "1 " 


VOUT = V DD - 0.2V, V DD - V S S - 1 -5V 


30 






!"A 


Logical "0" 


VOUT = V S S + 0.3V, V DD - V S S = 1 5V 


300 






mA 


Output Current Levels 


VDD - VSS = 1 -4V. V DD - V E E = 4.2V 










Phase 3 


Logical "1," Source 


V0UT= Vqd - 0.25V, Phase 2 < 1.5 ms 


7.5 






HA 


Logical "0," Sink 


V0UT = V S S+ 0.25V 


35.0 






HA 


CAP 1 












Phase 1 , Source 


V0UT = V DD - 0-25V 


7.5 






MA 


Phase 2, Sink 


V0UT = V S S + 0.25V 


20.0 






/uA 


Phase 3, Leakage 


V0UT = VDD-3.0V 






0.6 


AiA 


CAP 2 












Phase 1, Sink 


V0UT=V S S+ 0.25V 


35.0 






/*A 


Phase 2, Leakage 


V UT = V EE + 1.5V 






0.6 


HA 


VEE 












Phase 3, Sink 


CAP 2 = Vqd -4.2V, 
v OUT = v DD- 3 - 95v 


250 


| 


MA 



7-41 



o 

CM 

r- 
00 

in 

2 

00 

If) 

2 
2 

00 
00 

in 

2 
2 



oo 

in 

2 
2 



electrical characteristics (o 



Ontinued) T A within operating range, V DD - V s s = 1-5V, V DD - V EE =. 4.5V unless other* 



PARAMETER 



Supply Current ( Iqd' 
Doubler Operation 
Tripler Operation 

Voltage Regulator Input Current 

Voltage Regulator Switching 
Threshold 

256/1024 Hz Pulse Width 

Supply Voltage (Vr£f£) 
Doubler Operation 
Tripler Operation 



CONDITIONS 



ITa = 25 C, Iee = 1^A, f = 32,768 Hz, 
VDD= 15V 

V|N = Vdd-0.75"|MM58118, MM58120 
Ta = 25°C J Only 



Ta = 25°C, C = 0.047/iF, 
IEE = 1^A. f = 32,768 Hz, 
VDD - Vss = 1 5V, (Figure 91, 
(Note 1) 



MIN 



Vdd-0.4 



13 



2.5 
3.8 



TYP 



3.0 
6.0 

0.2 



MAX 



5.0 
8.0 

1.0 



Vdd-1-1 



17 



Note 1: In oscillator network shown in Figure 4. 

functional description 

A block diagram of the Watch Chip is shown in Figure 1. 
A chip pad layout is shown in Figure 2 and a package 
connection diagram in Figure 3. 



UNITS 



/"A 
HA 
|"A 



The MM58117 and MM58118 contain an on-chip 
voltage doubler for display drive and the MM481 19 and 
MM48120 contain an on-chip voltage tripler. 



□ a a a a 

ZG ZF ZA ZB 3G 



O Z56 Hz 
D«EE 

17 

□ Vee 

QOSC OUT 
Q0SC IN 

□ PHASE 3 



□ D 
3F 3A 



□ D 
3B 4G 



□ CAPZ 



8«„ 



B/1C 2E ZD 
D □ D 

i — H- 



'DEVICE NO. MM48117 
MM4B119 
*ALLPAOSAREfl.5xfl.5MIL 
EXCEPT Vss (5.0 nfl.5 MIL) 
•DIMENSIONS TO CENTER OF PAD 



I flAQ 

4BD 

SET/OISP □ 

v S s a 

u D D n 
^s a 

STQPQ 



2C COLON 3E 30 

□ a a a 



TEST Q 

CYCLED 
3C 4E 40 AC 

q □ d a 



42.2 
h- 

□ flA □ 

DIB 4f 

D SET/DISP 

DVss | 
Dv 0D J 

□ V SS 177 MILS 
D STOP 



od 

AG 3B 



a a 

3G ZB 



□ TEST 
D CYCLE 



4C 4D 

D □ 



* DEVICE NO. MM58118 
MM58120 
•ALL PADS ARE 4.5 « fl.b MILS 

EXCEPT V SS (5x5MILS) 
•DIMENSIONS TO CENTER Of PAD 



4E 3C 3D 3E COLON 2C 

an an an 



14^.1 IbH.l 



1024 Hi □ 
BEG □ 

veeD 

OSCOUT G 

osc in a 
VeeD 

PHASE 3 □ 
CAP? n 

capi n 



20 2E 

a a 



114.0 72,9 

FIGURE 2(a) 



FIGURE 2(b) 



MM581 17N, MM581 19N 



MM581 1 8N, MM581 20N 



1 
NC 


• 


2bJ- 




2a 




21 




*'— 




NC — 




256 Hz 




v EE — 




0SCOUT — 




DSC IN — 




PHAST3 

13 

CAP 2 

11 
CAPI — 
15 
K PLANE- 
IB 
Ib/lc — 
17 
2e — 




2d— 




2c — 
20 

COLON — 





TOP VIEW 

FIGURE 3{a) 



-SET/DISPLAY 

-v ss 

"VDD 
-STOP 
-TEST 
-CYCLE 



31 — 


• 


3a 




3b— 




flg 




4f— - 




4a 




flb 




SET/DISPLAY 




vss— 

voo-^ 




vss- 

STOP- 




TEST 

H 
CYCLE — 




4<JI 




4e 

3,-H 




3dJ! 
3,Ji 





-2, 

-m* Hi 

I 

-regulate 

-v E e 

-0SC0UT 

-OSC IN 

I 
-v EE 



-CAP 2 



-32 Hz/BACK PLANE 



TOP VIEW 

FIGURE 3(b) 



7-42 



functional description (Continued) 

Time Base: The precision time base of the watch is pro- 
vided by connecting a crystal controlled RC network to 
the on-chip CMOS inverter/amplifier as shown in Figure 
4. For proper operation, the network should be tuned to 
32,768 Hz. Resistor R1 is used to bias the on-chip in- 
verter for class A amplifier operation. Resistor R2 is 
used to (a) reduce the voltage sensitivity of the network; 

(b) limit the power dissipation in the quartz crystal; and 

(c) provide added phase shift for good start-up and low 
voltage circuit performance. Capacitors CI and C2 in 
series provide the parallel load capacitance required for 
precise tuning of the quartz crystal. The network shown 
in Figure 4 provides greater than 100 ppm tuning range 
when used with standard X-Y flexure quartz crystals 
trimmed for C L = 13 pF. Tuning to better than 2 ppm is 
easily obtainable. 

CMOS INVERTER 



- 36 pF Sj "N 




32761 Hz 
C L -1! P F 



4S»F 

■*- V|)D°» V SS 



FIGURE 4. Crystal Oscillator Network 

The 256/1024 Hz output or the 32 Hz output can be 
used to monitor the oscillator frequency during initial 
tuning without disturbing the network itself. 

DISPLAY CONTROL 






o 
o 





I t 


I I 



HOURS COLON MINUTES (SECONDS) 

MONTH DATE 



FIGURE 5. Time Display 

Leading zero values of month, date, and hours are 
blanked. The circuit contains a 4 year calendar which 
will automatically reset the Date Counter to 1 and 
advance the Month Counter at the end of each month 
(except for February in Leap Year). The character dis- 
play font is shown in Figure 6. 



J, , 

I J 




I I 


] 
] 



FIGURE 6. Character Display Font 

SETTING CONTROL 

A normally open switch connected to the Cycle input is 
used in conjunction with the Set/Display switch to set 
Month, Date, Hour, Minute, and synchronize Second 
information. 

MM58118, MM58120 



00 



2 

Wl 
00 

00 
CO 

a\ 

oo 

_j 

N) 
O 



The Hour:Minute, Month Date, and Second displays are 
controlled by a normally open switch connected to the 
Set/Display input. Month and Hour are displayed in digit 
positions 1 and 2. Date, Minute, and Second are dis- 
played in digit positions 3 and 4. 

The circuit will normally display Hour and Minute with 
the colon flashing at a 1 Hz rate {Figure 5). Depressing 
the Set/Display switch will cause Month and Date to be 
displayed with no colon. The display will automatically 
return to Hour and Minute display 2.25 ±0.25 seconds 
after the Set/Display switch has been released. Depress- 
ing the Set/Display switch a second time while the 
Month and Date are being displayed will cause the 
Second to be displayed until the Set/Display switch is 
again depressed, returning the display to Hour and 
Minute. 

The MM58117 and MM58119 have an additional display 
mode that can be used by depressing the Cycle switch 
while the watch is in the first display mode described 
above. The second display mode will alternately display 
Hour: Minute and Month Date for a period of 2 seconds 
each. Depressing the Set/Display switch will cause the 
Second to be displayed. Depressing the Set/Display 
switch again will return the watch to the second display 
mode. 



Hour: With the watch in the display mode, depressing 
the Cycle switch will put the watch in the Set Hour 
mode. In this mode the Hour will be displayed in digit 
positions 1 and 2 followed by the colon and either an A 
or a P (for AM or PM) displayed in digit position 4. 
While in this mode depressing the Set/Display switch will 
advance the Hour Counter at a 1 Hz rate until the Set/ 
Display switch is released. 

Minute: Depressing the Cycle switch while the watch is 
in the Set Hour mode will advance it to the Set Minute 
mode. In this mode the Minute will be displayed in digit 
positions 3 and 4 preceeded by the colon. Depressing the 
Set/Display switch while still holding the Cycle switch in 
will cause the Hold mode to be activated but will not 
advance the Minute counter. Depressing the Set/Display 
switch after the Cycle switch has been released will cause 
the Hold mode to be activated and will advance the 
Minute counter at a 1 Hz rate as long as the switch is 
held in. 

Month: Depressing the Cycle switch while the watch is 
in the Set Minute mode will advance it to the Set Month 
mode. In this mode the Month will be displayed in digit 
positions 1 and 2 with no colon. Depressing the Set/ 
Display switch will cause the Month counter to be 
advanced at a 1 Hz rate as long as the switch is held in. 



7 43 



functional description (continued) 

Date: Depressing the Cycle switch while the watch is in 
the Set Month mode will advance it to the Set Date 
mode. In this mode the Date will be displayed in digit 
positions 3 and 4 with no colon. Depressing the Set/ 
Display switch will cause the Date counter to be advanced 
at a 1 Hz rate as long as the switch is held in. 

Hold: If the Hold mode was activated while in the Set 
Minute mode, depressing the Cycle switch while in the 
Set Day mode will advance the watch to the Hold mode. 
In this mode Hour:Minute will be displayed flashing at a 
1 Hz rate. The Second counter will be held at 00. 
Depressing the Set/Display switch will advance the 
watch to the normal run mode with Month: Date dis- 
played and release the Second counter to begin normal 
operation. Depressing the Cycle switch will place the 
watch in the Set Hour mode with the Hold mode still 
activated. If the Hold mode was not activated while in 
the Set Minute mode, depressing the Cycle switch while 
in the Set Date mode will advance the watch to the Run 
mode with Hour:Minute displayed. 

While in any of the above set modes if no switches are 
activated for 5.25 ± 0.25 continuous seconds the watch 
will automatically jump to the Hold mode if it was acti- 
vated in the Set Minutes mode or to the Run mode if the 
Hold mode was not activated. There is no roll over of 
the next higher counter while a counter is being set. For 
example, while in the Set Minute mode, advancing the 
Minute counter from 59 to 00 will not advance the Hour 
counter. 



MM58117, MM58119 

The MM58117 and MM58119 setting procedure is 
similar to that of the MM581 18, except that the setting 
sequence is as follows: 

1. Set Month 

2. Set Date 

3. Set Hour 

4. Set Minute/Hold 

There is no 5.25 second time-out while in the setting 
mode and the watch will stay in each set mode until it is 
advanced to the next mode. The Cycle switch is used to 
advance from the Set Minute state to the first display 
state. The colon will blink on and off while time is 
being displayed unless the Hold mode is activated, 
forcing the colon to remain on continuously. During the 
second display mode, the colon will remain on during 
time display. Depressing the Set/Display switch while in 
either one of the two display states will cause the Hold 
mode to be cleared, allowing the watch to begin normal 
operation. 

Control state diagrams for the MM58117, MM58118, 
MM58119 and the MM58120 are provided in Figure 7. 



DISP 
HOUR 
MINUTE 



OISP 
MONTH 
DATE 



OISP 
SECOND 



DISP 
HOUR 



-^T 



h. 



DISP 




SET MINUTE 
SET HOLD 


MINUTE 




' 


' 




OISP 
MONTH 


SET 
MONTH 




1 


' 




OISP 
DAY 


SET 

DAY 




— ► User controlled rr 





1 


4 












OISP 
HOUR 
MINUTE 


DISP 
MONTH DATE 
CLEAR HOLD 




DISP 
SECOND 






«— ► 




i 










DISP 
HOURMINUTE 
MONTH DATE 


DISP 

SECOND 

CLEAR HOLD 






1 








DISP 
MONTH 


SET 
MONTH 






I 








DISP 
DATE 


SET 
DATE 






1 








DISP 
HOUR 


SET 
HOUR 










1 








DISP 
MINUTE 


SET MINUTE 
SETHOLD 






1 







FIGURE 7(a). MM58118, MM58120 Control State Diagram 



FIGURE 7(b). MM58117,MM58119 Control State Diagram 



7-44 



functional description (Continued) 



Stop Input: This input pad has an internal resistor to 
V EE holding it normally at a logical "0." A logical "1" 
at stop will force all of the display segments "OFF" 
and stop the oscillator, placing the watch in a static 
mode to decrease power dissipation during extended 
periods of storage. 

Contact Bounce: Debounce circuitry is provided on the 
Set/Display and Cycle inputs to remove any logic 
uncertainty upon either closure or release of switches 
provided switch bounce settles within 20 ms. 

Segment Outputs: The Segment outputs are designed 
to drive field-effect liquid crystal displays. Each display 
segment has its own output which furnishes the proper 
32 Hz drive signal. By definition, the segment is "OFF" 
when its drive signal is in phase with the display back- 
plane signal (BP/32 Hz). The segment is "ON" when its 
drive signal is 180 out of phase with the display back- 
plane signal. Typical output waveforms are shown in 
Figure 8. 

Colon Output: The Colon output provides a 32 Hz 
phase controlled signal identical to the segment outputs. 
The colon will blink at a 1 Hz rate during time display 
mode (except for display mode one with the Hold 
mode activated, and display mode two in the MM581 17, 
MM581 19) and remain on continuous while displaying 
time (Hours or Minutes) during the setting operation. 

VOLTAGE MULTIPLIER OUTPUTS: 

256/1024 Hz: The 256/1024 Hz pad is provided to 
drive a bipolar transistor which, in conjunction with a 



coil or transformer, generates the higher voltage needed 
for the display. A typical circuit is shown in Figure 9. 
The output waveform is shown in Figure 10. The 
MM58118, MM58120 provides a 1024 Hz output pulse 
while the MM58117, MM58119 provides the 256 Hz 
output pulse. 

Voltage Regulator: The Regulator input is used in con- 
junction with a zener diode to shut-off the 1024 Hz 
output to regulate the level of the V EE supply voltage. 
The Regulator input is provided on the MM58118 and 
MM58120only. 

Test Pads: Two pads are provided for test purposes. 

BP/32 Hz: This input/output pad is under the control of 
Test. When Test is open or at a logical "0," a 32 Hz 
signal is provided on BP/32 Hz which can be used to 
drive the backplane of the LCD unit or to monitor the 
oscillator frequency without affecting the oscillator cir- 
cuitry. If Test is at a logical "1," the BP/32 Hz pad is 
converted into an input and any frequency connected to 
it will replace the normal internal 32 Hz signal. This 
feature is provided to allow high speed advancement of 
the internal counters for testing purposes. 

Test: This input pad is used to control the BP/32 Hz pad 
as described above. When the Test pad is at a logical "1 ," 
the phase-control is disconnected from the segment drive 
outputs and the segment information will be referenced 
to a logical "0" backplane. Switching the Test pad from 
a logical "0" to a logical "1" generates a reset pulse that 
will reset the watch counters to 1 AM on January the 
first. This places the watch into a known state for testing 
purpose. 



Vdd 



r 



FIGURE 8. Common and Segment Output Signals 



7-45 



o 

00 

in 

5 

CO 
00 

in 

CO 

5 
in 

2 

2 



oo 
in 



functional description (Continued) 




=j 


1 1 


D 

D 


1 1 




l l 






f 9 b 

1 1 




>— ' 

















3-1/2 
DIGIT 
LCD 



*(For doubler, connect 
single 0. 05mF c apacitance 
between Phase 3 and Cap 2) 



MINUTES 
(SECONDS) 



"0N"CHIPTRIPLER 




- 




1 1 


D 
D 


1 1 




1 1 








*." 






= i i 


1 1 




T T 




e c 
d 

1 1 











3-1/2 

DIGIT 

LCD 



MINUTES 
(SECONDS) 



"OFF" CHIP MULTIPLIER 
FIGURE 9. Tvpical Application of MM58117, MM58118, MM58119 and MM58120 in LCD Watch System 



Vss 



1024H2(MM58118.MM58120) 
256H!(MM5«117,MM58119I 



FIGURE 10. 1024 Hz Output 



7-46 




Watches 



MM58127. MM58128. MM58129, 
general description 

The MM58127, MM58128, MM58129, and MM58130 
are low threshold voltage, ion implanted, metal-gate 
CMOS integrated circuits that provide or control all 
signals needed for a 3 1/2-digit LCD watch. The circuit 
time base is a 32,768 Hz crystal controlled oscillator. 
Oscillator RC network components are included on 
the circuits. The time base frequency is counted down to 
provide proper signals to display Hours-Minutes informa- 
tion continuously with Month-Date or Seconds informa- 
tion available upon demand. Time isdisplayed in 12-hour 
format. 23 phase controlled outputs are available for 
direct drive of a 3 1/2-digit liquid output display (LCD). 
The 32 Hz output serves as the backplane drive for the 
LCD. All 4 parts operate on a single 1.3— 1.7V supply. 
An on-chip voltage multiplier using external capacitors 
is used to provide the drive voltage for the display. 
All circuits have an on-chip voltage doublers which 
provide 2.5V minimum at 1 /iA load current or voltage 
triplers which provide 3.8V minimum at 1 /iA load 
current. A Test input can be used to convert the 32 Hz 



MM58130 LCD watch circuits 



output into an input for testing the divider circuitry at 
a higher frequency. All 4 parts are available as unpackaged 
die suitable for hybrid assembly or in 40-lead dual-in- 
line packages for evaluation purposes. 



features 

■ Direct continuous LCD drive capability 

■ 32,768 Hz crystal controlled operation 

■ Single 1.5V battery operation 

■ Low power dissipation 

■ 3 1/2-digit, 12 hour display 

■ 4 year calendar 

■ Seconds, Month and Date display upon demand 

■ Colon display 

■ Simple 2 button sequential setting 

■ On-chip oscillator RC network 

■ On-chip capacitive voltage multiplier 



2 

2 
w 

00 

-I 

NJ 
»J 

2 

2 

Ul 
00 

M 
00 

2 
2 

Ul 
00 

to 

2 
2 

Ul 
00 

w 
o 



block diagram 



f outO— 



STOPO 
DSC IN 



TEST 

Q 



a/BACKPLANE I/O 




1 X 1 ll i 



OUTPUT 
PHASE 
CONTROL 



V EE TRIPLE CAP 2 



I 9 I ? 



COUNTER 
SELECT 
LOGIC 



OUTPUT 
SEGMENT 
LATCHES 



- r 



•>. Z2-SEGMENT 

~ / OUTPUTS 



absolute maximum ratings 






Voltage at Osc. In, Osc. Out, FouT VdD + 3V to VsS"03V 






Regulator, Set/Display, Cycle, Stop, Double, Triple 






Voltage at Any Other Pin VQD+0.3V to VeE~0\3V 






Operating Temperature Range -5°C to +70°C 






Storage Temperature Range -25" C to +85 C 






Vdd-Vee 8.0V 






V D D - v S s 3 ° v 






Lead Temperature (Soldering, 10 seconds) 300 C 






electrical characteristics 






Ta within operating range, Vrjo — Vss = 1.5V, Vqd — Vee = 4.5V unless otherwise noted. 




PARAMETER 


CONDITIONS 


M1N 


TYP 


MAX 


UNITS 


Oscillator Start Voltage 


Ta = 25°C, (Note 1) 


1.4 






V 


Oscillator Sustaining Voltage 


T A = -5°C, (Note 1) 


1.3 






V 


Input Voltage Levels 












Set/Display, Cycle 












Logical "1 " 




VDD-0.25 




VDD 


V 


Logical "0" 


Internal Pull Down to Vss 




Open 




V 


BP/32 Hz Input 












Logical "1" 




VDD-0.25 




VDD 


V 


Logical "0" 




vee 




Vee+0.25 


V 


Test, Stop 












Logical "1" 


Internal Pull Down to V EE 


VDD-0.25 




VDD 


V 


Logical "0" 






Open 




V 


Input Current Levels 












Set/Display, Cycle 


V|N = V DD 


0.2 




10.0 


A<A 


Test 


V|N = V D D 






15 


pA 


Stop 


Vin- v D D, v E e = v ss * o.3v 






0.5 


HA 


Input Capacitance 


f = 1 MHz, V|N =0V 






5 


pF 


Osc. In, 


All Other Pads Gnd 










Output Voltage Levels 












Segment Drivers 












Logical "1 " 


VOUT = V DD - 0.2V, V DD - V EE = 3V 


4 






MA 


Logical "0" 


vout = v EE +o.2v, v DD - v EE = 3V 


4 






ma 


BP/32 Hz Output 












Logical "1 " 


VOUT = V DD - 0.2V, V DD - V E E = 3V 


40 






ma 


Logical "0" 


VOUT = V E E + 0.2V, V DD - V EE = 3V 


40 






/"A 


F OUT 












Logical "1" 


VOUT = V DD -0.2V, V DD - V S S = 1-5V 


30 






liA 


Logical "0" 


VOUT = V S S + 0.3V. V DD - V SS = 1 5V 


300 






MA 


Output Current Levels 


VDD -Vss=1.4V,V DD - V E E = 4.2V 










Double, Triple 












Logical "1," Source 


VOUT = V DD - 0.25V, Phase 2 < 1.5 ms 


7.5 






MA 


Logical "0," Sink 


V0UT = V S S + 0.25V 


35.0 






^A 


Cap. 1 












Phase 1 , Source 


V0UT = V DD - 0.25V 


7.5 






ma 


Phase 2, Sink 


V0UT = V SS + 025V 


20.0 






n* 


Phase 3, Leakage 


VOUT = V DD -3.0V 






0.6 


>lA 


Cap. 2 












Phase 1 , Sink 


V0UT = V SS + 0.25V 


35.0 






,uA 


Phase 2, Leakage 


v ut = vee + 1-5V 






0.6 


HA 


VEE 












Phase 3, Sink 


Cap. 2 = Vqd -4.2V, 
v OUT = V DD - 3.95V 


250 






MA 



748 



electrical characteristics (Continued) 

Ta within operating range, Vqd - Vss = 1.5V, V DD - Vf_e = 4.5V unless otherwise noted. 



PARAMETER 



Supply Current (Idq) 
Doubler Operation 
Tripler Operation 

256/1024 Hz Pulse Width 

Supply Voltage (Vee) 
Doubler Operation 
Tripler Operation 



CONDITIONS 



JT A = 25° C, l£ E = IfA, f = 32,768 Hz, 
|V D D= 1-5V 



Ta = 25°C, C = 0.047iiF, 
lEE = 1^ A . f = 32,768 Hz, 
VDD - VSS = 1 5V, (Figure 9), 
(Note 1) 



Note 1 : In oscillator network shown in Figure 4. 

functional description 

A block diagram of the Watch Chip is shown in Figure 1 . 
A chip pad layout is shown in Figure 2 and a package 
connection diagram in Figure 3. 



65 208 31 a 12 

n- — I — I — I- 

1SI-0--B tl 

F 0UT ?% 
37 8 - £] OSC CAP 



HS4--E] 



74 — 



33.9 - -FJ 



D 



□ 5 5 5 □ r#4-isi 



f£] OSC OUT 



Q CSC IN 
65 9- -[£] DOUBLE 
58.9-' £] TRIPLE 
58 9- -ED CAP 2 



MMS8127.MM58129 

NOT TO SCALE 

ALL PADS 5 6 X 5 MIL 

DIMENSIONS TO CENTER OF PAD 



Q8P3ZH, 



4b Q- -141.8 

SET OISP Q - 1294 

v SsQ ~113 4 

"ddQ 

v SsQ-96. 



STDPQ- - 50 9 
TEST Q -48 9 
CYCLE Q-31 J 



l' 1 !c 2* 2^ 2c COLON 3c 3d 3c 4c 4d 

j-g cp cp an □ □ □ □ □ 



B3--65 



! 188.5 92.8 80.6 670 55.0 43 31.0 23 2 

FIGURE 21a) 
MM58127N, MM58129N 



32 Hz BACK PLANE- 



-SET DISPLAY 
~ V SS 



-TEST 
-CYCLE 



TOP VIE'Y. 

FIGURE 3(a) 



MIN 



13 



2.5 
3.8 



TYP 



3.0 
4.0 



MAX 



5.0 
7.0 



UNITS 



MA 
HA 



The MM58127 and MM58128 contain an on-chip 
voltage doubler for display drive and the MM58129 and 
MM58130 contain an on-chip voltage tripler. 



4- 



538 428 318 20.B 



-& □ c □ □ fi i 

ta If 4i] 3b 3a 3f 3 g 

141.0- £] ah 

QSETDISP — -— 1SBMIL! 

-■QV 0D 
9 6.4-E) V SS 



□ □ \h a BfiBio 

2b 2 a Zf 2 g F QlJT 

OSC CAP Q- 

VeeQ-- 115.4 



MM58128 MM58130 

MOT TO SCALE 

ALL PA0S5DX 5.0 MIL 

□ IMENSIOiMSTQ CENTER OF PAD 



50 9 -£] STOP 

40 9- -QtEST 
31.? -£J CYCLE 



OSC OUT [3 

oscinQ- - 

DOUBLEQ- -65.9 
TRIPLE Q- — 51 
CAP2Q - 



\l 



mi Hz Q - 26.9 



n » i 



a □ □ a a 



COLON 2c 

— £-?- 

232 31.0 430 550 67 80 92.0 

FIGURE 2(b) 
MM58128N, MM58130N 



2d 2c 



J. 




32 Hz BACK PLANE 



FIGURE 3(b) 



2 

2 
<ji 

oo 

—a 

IS} 

Ul 
00 

00 

2- 

Ol 
CO 

(0 



2 
01 

00 

w 
o 



7-49 



o 

CO 

00 

un 

2 
S 

o> 

CM 

03 
IT) 

CO 

CM 

00 

in 

CM 

So 
in 

2 



functional description (Continued) 

Time Base: The precision time base of the watch is pro- 
vided by connecting a crystal controlled RC network to 
the on-chip CMOS inverter/amplifier as shown in Figure 
4. For proper operation, the network should be tuned to 
32,768 Hz. Resistor R1 is used to bias the on-chip in 
verter for class A amplifier operation. Resistor R2 is 
used to (a) reduce the voltage sensitivity of the network; 

(b) limit the power dissipation in the quartz crystal; and 

(c) provide added phase shift for good start-up and low 
voltage circuit performance. Capacitors C1 and C2 in 
series provide the parallel load capacitance required for 
precise tuning of the quartz crystal. The network shown 
in Figure 4 provides greater than 100 ppm tuning range 
when used with standard X-Y flexure quartz crystals 
trimmed for C L = 13 pF. Tuning to better than 2 ppm is 
easily obtainable. 



CMOS >NVEf!TER 




C2 _ L. 32.1S1 Hz 

,-31pF<7^> C L -I2„r 



FIGURE 4. Crystal Oscillator Network 

The 256/1024 Hz output or the 32 Hz output can be 
used to monitor the oscillator frequency during initial 
tuning without disturbing the network itself. 

DISPLAY CONTROL 

The Hour:Minute, Month Date, and Second displays are 
controlled by a normally open switch connected to the 
Set/Display input. Month and Hour are displayed in digit 
positions 1 and 2. Date, Minute, and Second are dis 
played in digit positions 3 and 4. 

The circuit will normally display Hour and Minute with 
the colon flashing at a 1 Hz rate [Figure 5). Depressing 
the Set/Display switch will cause Month and Date to be 
displayed with no colon. The display will automatically 
return to Hour and Minute display 2.25 ±0.25 seconds 
after the Set/Display switch has been released. Depress- 
ing the Set/Display switch a second time while the 
Month and Date are being displayed will cause the 
Second to be displayed until the Set/Display switch is 
again depressed, returning the display to Hour and 
Minute. An option is available to display Minutes unit 
and Seconds in this mode. 

All versions have an additional display mode that can be 
used by depressing the Cycle switch while the watch is 
in the first display mode described above. The second 
display mode will alternately display Hour:Minute and 
Month Date for a period of 2 seconds each. Depressing 
the Set/Display switch will cause the Second to be 
displayed. Depressing the Set/Display switch again will 
return the watch to the second display mode. 



o 
o 



FIGURE 5. Time Display 

Leading zero values of month, date, and hours are 
blanked. The circuit contains a 4 year calendar which 
will automatically reset the Date Counter to 1 and 
advance the Month Counter at the end of each month 
(except for February in Leap Year). The character dis- 
play font is shown in Figure 6. 

LJ 



H I 1 

i — iL 



FIGURE 6. Character Display Font 

SETTING CONTROL 

A normally open switch connected to the Cycle input is 
used in conjunction with the Set/Display switch to set 
Month, Date, Hour, Minute, and synchronize Second 
information. 

Month: Depressing the Cycle switch while the watch is 
in the Alternating Display mode will advance it to the 
Set Month mode. In this mode the Month will be dis- 
played in digit positions 1 and 2 with no colon. Depres- 
sing the Set/Display switch will cause the Month counter 
to be advanced at a 1 Hz rate as long as the switch is 
held in. 

Date: Depressing the Cycle switch while the watch is in 
the Set Month mode will advance it to the Set Date 
mode. In this mode the Date will be displayed in digit 
positions 3 and 4 with no colon. Depressing the Set/ 
Display switch will cause the Date counter to be advanced 
at a 1 Hz rate as long as the switch is held in. 

Hour: With the watch in the Set Date mode, depressing 
the Cycle switch will put the watch in the Set Hour 
mode. In this mode the Hour will be displayed in digit 
positions 1 and 2 followed by the colon and either an A 
or a P (for AM or PM) displayed in digit position 4. 
While in this mode, depressing the Set/Display switch will 
advance the Hour Counter at a 1 Hz rate until the Set/ 
Display switch is released. 

Minute: Depressing the cycle switch while the watch is 
in the Set Hour mode will advance it to the Set Minute 
mode. In this mode the Minute will be displayed in digit 
positions 3 and 4 preceeded by the colon. Depressing the 
Set/Display switch while still holding the Cycle switch in 
will cause the Hold mode to be activated but will not 
advance the Minute counter. Depressing the Set/Display 
switch after the Cycle switch has been released will cause 
the Hold mode to be activated and will advance the 
Minute counter at a 1 Hz rate as long as the switch is 
held in. 



7-50 



functional description (continued) 

Hold: The Cycle switch is used to advance from the Set 
Minute state to the first display state. The colon will 
blink on and off while time is being displayed unless the 
Hold mode is activated, forcing the colon to remain on 
continuously. During the second display mode, the 
colon will remain on during time display. Depressing the 
Set/Display switch while in either one of the two display 
states will cause the Hold mode to be cleared, allowing 
the watch to begin normal operation. 



Colon Output: The Colon output provides a 32 Hz 
phase controlled signal identical to the segment outputs. 
The colon will blink at a 1 Hz rate during time display 
mode (except for display mode one with the Hold 
mode activated, and display mode two in the MM58117, 
MM58119) and remain on continuous while displaying 
time (Hours or Minutes) during the setting operation. 

TEST PADS 



Control state diagrams for the watch are provided in 
Figure 7. 

Options are available for 1 or 2 Hz setting rate. In addi- 
tion, a further option allows a fast set at 4 times the 
normal rate by pushing both Set/Display and then the 
cycle switch. 

Stop Input: This input pad has an internal resistor to 
V EE holding it normally at a logical "0." A logical "1" 
at stop will force all of the display segments "OFF" 
and stop the oscillator, placing the watch in a static 
mode to decrease power dissipation during extended 
periods of storage. 



Three pads are provided for test purposes. 

F0UT : The 256/1024 Hz pad is provided for oscillator 
tuning. 

BP/32 Hz: This input/output pad is under the control of 
Test. When Test is open or at a logical "0," a 32 Hz 
signal is provided on BP/32 Hz which can be used to 
drive the backplane of the LCD unit or to monitor the 
oscillator frequency without affecting the oscillator cir- 
cuitry. If Test is at a logical "1," the BP/32 Hz pad is 
converted into an input and any frequency connected to 
it will replace the normal internal 32 Hz signal. This 
feature is provided to allow high speed advancement of 
the internal counters for testing purposes. 



Contact Bounce: Debounce circuitry is provided on the 
Set/Display and Cycle inputs to remove any logic 
uncertainty upon either closure or release of switches. 

Segment Outputs: The Segment outputs are designed 
to drive field-effect liquid crystal displays. Each display 
segment has its own output which furnishes the proper 
32 Hz drive signal. By definition, the segment is "OFF" 
when its drive signal is in phase with the display back- 
plane signal (BP/32 Hz). The segment is "ON" when its 
drive signal is 180° out of phase with the display back- 
plane signal. Typical output waveforms are shown in 
Figure 8. 



Test: This input pad is used to control the BP/32 Hz pad 
as described above. When the Test pad is at a logical "1," 
the phase-control is disconnected from the segment drive 
outputs and the segment information will be referenced, 
to a logical "0" backplane. Switching the Test pad from 
a logical "0" to a logical "1" generates a reset pulse that 
will reset the watch counters to 1 AM on January the 
first. This places the watch into a known state for testing 
purpose. 

Options: Various mask options of the basic part type 
are available as standard parts. These are described in 
Table I. Other combinations of these options can also 
be made upon special request. 



1 


«-- 








1 


DISP 
HOUR 
MINUTE 


DISP 
MONTH DATE 
CLEAR HOLD 


DISP 
SECOND 









DISP 
HOUR MINUTE 
MONTH DATE 



0ISP 

SEC0N0 

CLEAR HOLD 



!_X^J IS\J~ 



FIGURE 7. Control State Diagram 



FIGURE 8. Common and Segment Output Signals 



7-51 



functional description (Continued) 



TABLE I. Standard Available Options 



PART NO. 


MOUNTING 


F OUT 


DEBOUNCE 
FREQUENCY 


SETTING 
RATE 


RUN 2 
RATE 


MIN/SEC 


MM48127 


Front 


1024 


8 Hz 


2 Hz/8 Hz 


1/4 Hz 


Yes 


MM48128 


Back 




TO BE DETERMINED 




MM48129 


Front 


256 


16 Hz 


1 Hz 


1/4 Hz 


No 


MM48130 


Back 


1024 


8 Hz 


2 Hz/8 Hz 


1/4 Hz 


Yes 



-H.o 5ijF *J°^ 

T T 



T 

"00 



20M 
C L »12pF 



Dh 



—f~ «PF 



VOQOBVSS 



OSCIN 
TRIPLE 
CAP 2 



SET/DISP 
CYCLE 



(For doubler, connect single 
0.05 mF capacitance between 
double and Cap 2) 



Ural 






3 1/Z-DIGIT 
LCD 



COLON MINUTES 

(SECONDS) 



"0N"CHIPTRIPLER 



FIGURE 9. Typical Application in LCD Watch System 



Vdd- 
vss 



1024 Hz (MM5B128, MM58130) 
256Hz(MM58127,MM58129} 



FIGURE 10. 1024 Hz Output 



7-52 







SECTION 8 
CALCULATORS 






CO 
If) 



a 



Calculators 



MM5734 8-function accumulating memory calculator 



general description 

The single-chip MM5734 calculator was developed using 
a metal-gate P-channel enhancement and depletion mode 
MOS/LSI technology with a primary object of low end- 
product cost. A complete calculator as shown in Figure 1 
requires only the MM5734 calculator chip, an X-Y matrix 
keyboard, an NSA1198 or NSA1298 LED display and a 
9V battery. 

Keyboard decoding and key debounce circuitry, all 
clocks and timing generators, power-on clear, and 7- 
segment output display decoding are included on-chip, 
and require no external components. Segments and digits 
can usually be driven directly from the MM5734, as the 
segments typically source 8 mA of peak current and the 
digit drivers sink 20 mA min. 

Leading zero suppression and a floating negative sign 
allow convenient reading of the display and conserve 
power. The MM5734 is capable of sensing a low battery 
voltage and indicates this by displaying a decimal point 
in digit eight. Up to 8-digits for positive numbers and 7 
for negative numbers can be displayed, with the negative 
sign displayed in the 8th position. Typical current drain 
of a complete calculator displaying five "5's" is 25 mA. 



The MM5734 is capable of decoding a keyboard matrix 
as shown in Figure 1. Three possible models are shown 
in Figure 2. Figure 2(c) illustrates a keyboard scheme 
which includes all 8 functions with only 23 keys by 
using a function key (F). 

features 

■ 8-digit, (7-negative), capacity 

■ 8 functions (+, -, X, +, X 2 , \/x, 1 /X, %) 

■ Convenient algebraic notation 

■ Fully protected accumulating memory (M+, M-) 

■ Automatic constant independent of memory 

■ Floating input/floating output 

■ Power-on clear* 

■ On-chip oscillator* 

■ Direct 9V battery compatibility 

■ Low system cost 

■ Direct digit drive of LED display 

■ Low cost X-Y keyboard matrix 

* Requires no external components 



connection diagram 

Dual-ln-Line Package 



osc - 

V 

IN1 - 

S DP"" 

Sf' 

»ss- 



1 


28 ■ 


2 


27 - 


3 


26 ■ 


4 


25 " 


5 


24 


6 


23 


7 


22 


6 


21 


9 


20 


10 


19 


11 


18 


12 


17 


13 


16 


14 


15 



► D9 



keyboard outline 



Pin Description 



K1-K4 Keyboard Inputs 
" V 0D IN1.IN2 Genera! Purpose Inputs 
kn OSC Programmable as 

External Oscillator 

► S a D1— D9 Digit Outputs 

S a — S g Segment Outputs 
*" s t> SDP Decimal Point Segment 

-nc 0utput 

O General Purpose Output 

► s c Vqq -9 Volts 

V s s Volts 





F* 


cs* 


%* 




F* 


X 2 * 


EX* 


v"* 


M+* 


M-* 


• * 


!«♦ 


MR* 


MC* 


■/.* 


1/X 


v'~ 


X 2 


-r 


7 


8 


9 


X 


4 


5 


6 


- 


1 


2 


3 


+ 


c 

CF 





• 


= 



K4 K3 K2 K1 

Double Function Key 



Order Number MM5734N 
See Package 23 



absolute maximum ratings operating voltage range 




Volume at Any Pin Relative to Vgs Vgs +0.3V to V ss -12V 6.5V <V SS - 

( All Other Pins Connected to Vgg} 

Ambient Operating Time 0°Cto+70°C 

Ambient Storage Time -65°C to +150°C 

Lead Temperature (Soldering, 10 seconds) 300°C 


V DD <9.5V 




dc electrical characteristics 






PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Iqd Operating Supply Current 


V D D = V SS -9.5V,T A = 25°C 




8 


15 


mA 


Keyboard Scan Input Levels* 












CK1 K4 












V|H Logical High Level 


VDD= V SS -6.5V 


V S S -4.0 




vss 


V 




VDD = V SS 9.5V 


Vss-40 




vss 


V 


V|L Logical Low Level 


VDD = V SS -6.5V, l| L <--80juA 


VDD 




Vss-6.0 


V 




VDD = VSS-9-5V, l| L <-80|uA 


VDD 




Vss-63 


V 


Segment Output Current 


VOUT = V S S -10V, V DD = V S S -6.5V 


-2.5 






mA 




VOUT = V S S -5-OV, V DD = V SS "8 0V 




-8 




mA 




VOUT = V S S -6.5V, V DD - V S S "9-5V 






-12 


mA 


Digit Output Current 












lOH Logical High Leve 


V0UT = V SS - 2.0V, V DD = V SS 6.5V 


-300 






i"A 


'OL Logical Low Level 


V0UT = V SS -3.0V 


20 






mA 


Ready Output 


VDD = V S S -65V 










Voh Logical High Level 


l(0UT = -550jl/A 


Vss-10 






V 


Vol Logical Low Level 


lOUT -"- 5mA 






VDD+60 


V 


Keyboard Resistance 












K1, K4 








5 


K 


ac electrical characteristics 


PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Display Word Time 


(Figure 3) 


2.9 






15.4 




ms 


Display Digit Time 


/Figure 3) 


0.32 






1.71 




ms 


Interdigit Blanking Time (Segment 


(Figure 3 J 






175 






MS 


Outputs) 
















Ready Transition Times 
















High-to-Low 


VDD = V S S -6-5V 








20 




Ms 


Low-to-High 


C L = 50 pF 








1 




MS 


Digit Output Transition Times 
















High-to-Low 


Cl= 100 pF 






8 






Ms 


Low-to-High 








3 






Ms 


Keyboard Inputs 


C L = 25pF 






6 






Ms 


High-to-Low Transition Time After Key Release 
















Key Bounce-Out Stability Time 




11.7 






61.7 




ms 


(The time a keyboard input must be 
















continuously lower than the maximum 
















logical low level to be accepted as a key 
















closure, or higher than the minimum 
















logical high level to be accepted as a 
















key release.) 
















Worst-Case Calculation Time 










0.56 




s 



functional description 

The MM5734 is a calculator chip which contains five 
data registers: (1) entry, (2) accumulator, (3) 2 working 
and (4) memory, each consisting of 8 digits, sign, and 
decimal point. The entry register is always displayed. It 
contains digit entries from the keyboard, and results of all 
functions except M+ and M— . The accumulator is used in 
all arithmetic functions and stores a copy of the entry 
register on all results. This allows another number to be 
entered without losing an intermediate result. Multiply 
and divide requires three registers to perform the function 
and save the divisor, or multiplier. The working register 
is provided to perform these functions in conjunction 
with the entry and accumulator registers. A second 
working register is used to store the constant in chain 
operations while performing X or 1/X. This allows 
chain operation using X , 1/X and vX- 

The memory register is used only to store a number to be 
used later. It is fully protected during all operations, 
and is only modified by depressing a "MS," "M+," or 
"M— " key. Power-on clears all of the registers including 
the memory register. 



The MM5734 performs the "+," "-," "X" and "V 
functions using algebraic notation. This requires the use 
of a mode register and a terminate flag. The mode 
register directs the machine to the proper function (add, 
subtract, multiply or divide) with each new key entry. 
After the function has been performed, the key entered 
is used to modify the mode register. 



The terminate flag is set on "=" and sometimes on "%" 
and "C." This signifies the end of the problem. The 
MM5734 allows for full floating entries and intermediate 
results. 



If the terminate flag is set, a "+," "-," "X" or "V key 
signals the beginning of a new problem. The number 
being displayed is copied into the accumulator register 
and the mode register assumes the mode of the key 
entered. The terminate flag is always reset by the "+ ( " 
"— ," "X" and "^" keys. 




K4 K3 K2 Kl 



FIGURE 1A. Complete Calculator Schematic 

K4 K3 K2 

















s>± 















LCS/X 2 ' 


s^ x 


iM+'MR , 


iM-/MC i 













FIGURE 11b). Optional Keys 



FIGURE 1(c). Optional Keys 



8-4 



OPERATION IN THE ADD AND SUBTRACT MODE 



Operation in the Multiply Mode 





F 


x z 


% 
EX 


Vx 


MR 


M- 
MC 


-f 







CS 


•/. 


as 

D5 


1/X 


MR 


MC 


•/. 


1/X 


^" 


X 2 


-f 


n" 


M+ 


M- 


-^ 



7 


8 


9 


X 


4 


5 


6 


- 


i 


2 


3 


+ 


C 
CF 





• 


= 



If the terminate flag is set, an "=" key will result in a 
constant add/subtract. The number in the accumulator 
will be added to (or subtracted from) the number being 
displayed. The result is right justified and displayed in 
the entry register. Accumulator and mode registers are 
not altered, allowing for constant operations. 

If the terminate flag is not set and a number has been 
entered from the keyboard, or memory register, a "+," 
"— ," "X" or ' ,J r" key will result in an addition or sub- 
traction. The entry register will be added to or subtracted 
from the accumulator and the new running total will be 
displayed in the entry register and copied into the 
accumulator register. The mode will be altered according 
to which key is entered. 

If the terminate flag is not set, and a number has not 
been entered from the keyboard, or memory, a "+," 
"— ," "X," "^" key will only change the mode register 
to the new key entry. 

If the terminate flag is not set, an "=" key will add/ 
subtract the number being displayed to/from the number 
in the accumulator register. The number being displayed 
is transferred to the accumulator, and the result of the 
operation is displayed in the entry register. The terminate 
flag is set, conditioning the calculator for constant, add/ 
subtract operation. The number being displayed previous 
to the "=" key is stored in the accumulator as the 
constant. 

Operation of the "%" key in add/subtract mode, with 
the terminate flag reset, will multiply the accumulator 
by the last entry, divide the result by 100, and display it 
in the entry register. The mode register remains as it 
was in the add/subtract mode. All of the above is re- 
quired to perform the percent add on or discount 
problems. Depression of an "=" key after the "%" key 
will either tax or discount the original number as a 
function of the mode register and the last entry. 

Operation of the "%" key in add/subtract mode, with 
the terminate flag set, will shift the decimal point of the 
number being displayed two places to the left and copy 
it into the accumulator register. The mode is set to 
multiply and the terminate flag remains set. 



If the terminate flag is set, an "=" key will result in a 
constant multiply operation. The number being displayed 
is multiplied by the constant stored in the accumulator 
register. The result is displayed in the entry register and 
the accumulator and mode registers are not altered, 
allowing for constant operation. Repeated depressions of 
the "=" key can be used to raise a number to an integer 
power, i.e., "C," "C," "5.2," "X," "=," "=," "=," 
computes 5.2 . 

The constant in multiplication, as well as in addition, 
subtraction and division is the last number entered. For 
the sequence: "C," "C," "3," "V "4," "X," "2," 
"=" the constant multiplier for future problems is 2. 

If the terminate flag is not set, an "=" key will signal 
the end of a problem. The number in the display will be 
multiplied by the contents of the accumulator, and the 
results will be displayed in the entry register. The number 
previously in the entry register is stored in the accumu- 
lator register and the terminate flag is set. 

If the terminate flag is not set, and a number has been 
entered from the keyboard or memory register, a "+," 
"— ," "X" or "^" key will result in a multiplication. 
The number being displayed will be multiplied by the 
number residing in the accumulator register. The result 
will be copied into the accumulator and displayed in the 
entry register. The mode register is updated as a function 
of the key depressed. 

Operation of the "%" key while in multiply mode looks 
exactly the same as an "=" key except the decimal point 
of the display is shifted two positions to the left before 
the multiplication takes place. 

Operation in the Divide Mode 

If the terminate flag is set, an "=" key will result in 
constant divide operation. The number being displayed 
is divided by the constant stored in the accumulator 
register. The accumulator and mode registers are not 
altered allowing for constant operations. Repeated de- 
pressions of the "=" key will result in repeated divisions 
by the constant. Thus, it is possible to raise a number to 
a negative power using the sequence "C," "C," "1," 
"V "No.," "=," "=," etc. 

If the terminate flag is not set, an "=" key will signal 
the end of a problem. The number in the accumulator 
register will be divided by the number being displayed. 
The result is transferred to the entry register and dis- 
played. The terminate flag is set and the divisor is stored 
in the accumulator register. 

If the terminate flag is not set, a "+," "— ," "X" or "r" 
key will result in a division. The number in the accumu- 
lator register will be divided by the number being 
displayed. The results are displayed in the entry register, 
and a copy of the result is stored in the accumulator. The 
mode register is modified to reflect the latest key entry. 

Operation of the "%" key while in divide mode looks 
exactly the same as the "=" key except the decimal 
point of the display is shifted two positions to the left 
before division takes place. 



Error Conditions 



Function of Keys 



If any of the operations mentioned above generates a 
number larger than 99999999, an error will occur. An 
error is indicated by displaying the 8 most significant 
digits and sign with all 9 decimal points. The first de- 
pression of the "C" key will clear the error condition, 
and all registers except the memory register. 



It is not possible to generate an error during number entry. 
The ninth and subsequent digits entered are ignored. 



Leading Zero Suppression and Negative Sign 

In order to conserve battery power, the MM5734 blanks 
leading zeros on all numbers displayed. No more than 7 
decimal digits are permitted. The MWI5734 displays 8 
digits for positive numbers, and 7 digits negative, allowing 
the 8-digit position for a negative sign. The negative 
sign floats to the left of the most significant digit on 
numbers containing less than 7 digits. 



Power-On Condition 

The MM5734 has an internal power-on clear circuit 
which clears all registers to zero, places the mode to 
add and sets the terminate flag. A zero and decimal 
point are displayed. 



Keyboard Bounce and Noise Rejection 

The MM5734 is designed to interface with most low cost 
keyboards, which are often the least desirable from a 
false or multiple entry standpoint. A simple X-Y key- 
board matrix can be used with all the necessary decoding 
accomplished within this MM5734. 



Some of the keys operate differently when in the data or 
number entry condition. The MM5734 switches to entry 
condition when entering numbers and leaves this condi- 
tion after most function keys. The following paragraphs 
which discussed the action of "+," "— ," "X," "^" and 
"%" keys and the examples given in later sections will 
act in further explaining these actions. 

Clear Key, "CE/C" 

While in the number entry condition, one depression 
will clear the entry register to zero. The machine then 
leaves the number entry state. 

If the error condition is displayed, one depression will 
clear the error, and all registers except the memory 
register. The machine could not be in the number entry 
condition with the error flag set. 

If the error flag is not set and the machine is not in the 
number entry condition, one depression of "CE/C" key 
will clear the entry and accumulator registers. It also 
places the machine in the add mode and sets the terminate 
flag. The memory register remains unchanged. 

Number Keys 0-9 

If not in the number entry condition, a number key will 
clear the display and then enter the value of the key into 
the LSD. The digits are displayed as they are entered 
and the machine assumes the number entry condition. 

If in the number entry condition, the entry register is 
shifted left one position and the key depressed is entered 
into the LSD. Digits entered after 8 digits positive, or 7 
digits negative, will be ignored. Digits entered after 7 
decimal digits are displayed will also be ignored. 



A key closure is sensed by the calculator chip when one 
of the key inputs, K1, K2, K3, K4, is forced more 
negative than the logical low level specified in the 
electrical specifications. An internal counter is started 
as a result of the closure. The key operation begins after 
11 word times if the key input is still at a logical low 
level. As long as the key is held down (and the key input 
remains low) no further entry is allowed. When the key 
input changes to a logical high level, the internal counter 
starts an 11 word timeout for key release. During both, 
entry and release timeouts, the key inputs are sampled 
during every display period for valid levels. If they are 
found invalid, the counter is reset and the calculator 
resumes scanning the keyboard. 

The "Ready" signal indicates calculator status. When the 
calculator is in an "idle" state, the output is at a logical 
high level (near Vgs)- When a key is closed, the internal 
key entry timer is started. "Ready" remains high until the 
timeout is completed and the key entry is accepted as 
valid, then goes low. It remains at a logical low level 
until the function initiated by the key is completed and 
the key is released. The low-to-high transition indicates 
the calculator has returned to an idle state and a new key 
can be entered. 



Square Root Key "y/X" 

The square root key extracts the square root of the 
absolute value of the number being displayed in the 
entry register. 

The mode of the calculator remains unchanged. This 
enables square root operations in the middle of chain 
calculations. For example: 



KEY DISPLAY KEY DISPLAY 



KEY DISPLAY 



A 


A 


A 


A 


11 


11 


sT 


Va 


X 


A 


+ 


11 


+ 


Va 


B 


B 


5 


5 


B 


B 


V~ 


V§ 


= 


16 


V~ 


Vb 


= 


aV§ 


V" 


4 




Va+Vb 






6 
9 

V" 


6 
11 
9 
3 
8 



8-6 



Square 

Depression of the "X 2 " key squares the number in the 
display register, and displays the results. The mode of 
the calculator remains unchanged. This enables square 
operations in the middle of chain calculations. 



Inverse 

Depression of the "1/X" key takes the inverse of the 
number in the display register and displays the results. The 



mode of the calculator remains unchanged. This enables 
inverse operations in the middle of chain calculations. 

F Key (Function Key) 

The "F" key translates the following key depressed to 
this code of the key below it, Figure 2, if it is a DOUBLE 
FUNCTION KEY. If the CLEAR KEY is the following 
key, the FUNCTION CONDITION is removed leaving 
the calculator in its previous mode. 



2 
w 



SQUARE PROBLEMS 
KEYS DISPLAY 



COMMENTS 



72 
X 2 


7 2. 
5184. 


Squares display 


7 


7 . 




CS 


-7 . 




X 2 


49. 


Squares minus numbers 


+ 


49 . 


Chain capabilities 


8 
X 2 


8. 
64. 


Squares display (mode 
unchanged) 




113. 


Completes addition, term 
nates problems 



INVERSE PROBLEMS 


KEY 


DISPLAY 


5 


5. 


1/X 


0.2 


4 


4 . 


1/X 


0.25 


+ 




8 


8 


1/X 


0.125 


= 


0.375 



COMMENTS 

Takes inverse of display 
Takes inverse 



Takes inverse (mode 
unchanged) 

Completes addition, termi- 
nates problem 



CO 



& 



Calculators 



MM5737 calculator— 8-digit, 4-function, 
general description 

The MM5737 single-chip calculator was developed using 
a metal gate, P-channel, enhancement and depletion 
mode MOS process with low end-product cost as the 
primary objective. A complete calculator, as shown in 
Figure 1 , requires only a keyboard, DM8864 digit driver, 
nine digit LED display and a 9V battery with appro- 
priate hardware. 

Keyboard decoding and key debounce circuitry, all 
clock and timing generation and output 7-segment dis- 
play decoding are all included on-chip and require no 
external discrete components. LED segments can be 
driven directly from the MM5737 as it typically sources 
8.0 mA of peak current. [Note: The typical duty 
cycle of each digit is 0.111; average LED segment 
current is therefore approximately 0.111 (8.0 mA), or 
0.89 mA. Correspondingly, the worst-case average seg- 
ment current is 0.111 (5.0 mA), or 0.555 mA.] The 
ninth digit is used for the negative sign of an eight digit 
number, and as an error indicator. Negative results less 
than eight digits will have the negative sign displayed one 
digit to the left of the most-significant-digit (MSD). The 
DM8864 digit driver is capable of indicating a low 
battery voltage condition by turning on the ninth digit 
decimal point-which does not hinder the actual calcu- 
lator operation. 

Leading and trailing zero suppression allows convenient 
reading of the right justified display and conserves 
power. Battery life is estimated to be 10 to 20 hours, 
depending on battery quality, operating schedule and 
the average number of digits displayed. 



floating decimal point 



The Ready output signal is used to indicate when the 
calculator is performing an operation (Table I). It is 
useful in testing of the device or when the MM5737 is 
used as part of a larger system and is required to inter- 
face with other logic. (Another feature that is important 
in such applications is the ability to reduce the key 
debounce time from seven word times to four word times 
by forcing the Digit 7 output high during Digit 9 time.) 



features 

■ Full 8-digit entry and display capacity 

■ Four functions (+, -, x, ^) 

■ Floating negative sign indicator is always displayed 
one digit to left of MSD 

■ Convenient algebraic key entry notation 

■ Floating point input and output 

■ Chain operations 

■ Direct 9V battery compatibility; low power 

■ Direct interface to LED segments 

■ No external components are required other than 
display digit driver, keyboard and LED display for 
complete calculator 

■ Overflow and divide-by-zero error indication 

■ Right justified entry and results, with leading and 
trailing zero suppression 



connection diagram 



Dual-ln-Line Package 




Order Number MM5737N 
See Package 22 



absolute maximum ratings 










Voltage at Any Pin Relative to V ss . (All 

other pins connected to V ss ). V ss + 0.3V to V ss - 12.0 
Ambient Operating Temperature C to +70 C 
Ambient Storage Temperature -55°C to +150°C 
Lead Temperature (Soldering, 10 seconds) 300 C 










operating voltage range 

6.5V <V SS - V DD <9.5V 

(V ss always defined as most positive supply voltage.) 










dc electrical characteristics 










PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Operating Supply Current (l D D ) 


Vdd = V ss -9-5V 
T A = 25°C 




8.0 


14.0 


mA 


Keyboard Scan Input Levels 

(K1, K2and K3) 

Logical High Level (V, H ) 
Logical Low Level (V lL ) 


V ss -65V < V DD < V ss -9.5V 
Vdd = V ss "6.5V 
Vdd = V ss -9.5V 


Vss -2 -5 




V ss -5.0 
V ss -6.0 


V 
V 
V 


Digit Output Levels (Note 1 ) 
Logical High Level (V 0H ) 
Logical Low Level (V OL ) 


V S s -6.5V <V DD <V SS -9.5V 
Vdd =V ss -6.5V 
Vdd = V ss -9.5V 


Vss-1-5 




V ss -6.0 
V ss -7.0 


V 
V 
V 


Segment Output Current 

(Sa through Sg and Decimal Point) 


T fl =25°C 

Vout = V S s -3.8V, V DD = V ss -6.5V 
Vout = V S s -50V, V DD = V ss "8.0V 
Vout = V ss -6.5V, V DD = V ss -9.5V 


-5.0 


-8.0 
-10.0 


-15.0 


mA 
mA 
mA 


Ready Output Levels 

Logical High Level (V OH ) 
Logical Low Level (V 0L ) 


Iqut = -0.4 mA 
l OUT = 10uA 


Vss-1-0 




Vdd + 1-0 


V 
V 


Note 1: With digit connected through key to K-line and to DM8864. 










ac electrical characteristics 










PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Word Time (Figure 21 




0.63 


1.5 


5.2 


ms 


Digit Time {Figure 2) 




70 


170 


580 


MS 


Interdigit Blanking Time (Figure 2) 






4 




MS 


Digit Output Transition Times 
('rise and t FALL ) 


Cload = 100 pF 




2 




MS 


Keyboard Inputs High to Low 
Transition Time After 
Key Release 


C l oad = 100 pF 




4 




Ms 


Ready Output Propagation Time 

(Figure 3) 

Low to High Level (t PDH ) 
High to Low Level (t POL ) 


Cload = 100 pF 
Cload = 100 pF 


60 
0.06 


140 
0.5 


480 
1.5 


MS 
ms 


Key Bounce-out Stability Time 
(The time a keyboard input must be 
continuously higher than the 
minimum logical high level to be 
accepted as a key closure, or con- 
tinuously lower than the maximum 
logical low level to be accepted as a 
key release.) 




4.2 


10.5 


35 


ms 


Calculation Time for 
99999999 + 1 = 99999999 




90 


220 


760 


ms 



2 
w 



89 



CO 

r* 

IT) 




Sa Sb Sc Sd Se SI So. dp 
MM5737 
Dl 02 03 DA D5 D6 07 OB D9 



-^i 



dp Sy Sf Se Sd Sc Sb Sa NSA198 

/-/ /-/ o o o o o o o 
o. o. /_/. /_/. /_/. /_/. /_/. /_/. /_/. 

m D8 D7 D6 D5 D4 03 D2 D1 



I 

'ER \ 



CALCULATOR CHIP 



DISPLAY DRIVER 



FIGURE 1 . Complete Calculator Schematic 



TABLE I. Ready Signal Description 



CALCULATOR FUNCTION 


READY SIGNAL 


Idle 

Key Entry and Functional Operation 

Key Release and Return to Idle 


READY is quiescently at a Logical High Level (^-V ss ). 

When a key is depressed, the bounce-out stability timer is initiated. 
READY remains high until the bounce-out time is completed and the 
key is entered, at which time it changes to a Logical Low Level (M/ DD ). 

READY remains low until key release is debounced and the calculator 
returns to the idle state. The low to high transition signals the return to 
idle. (The display may lag the READY by up to eight word times.) 



KEY INPUT BOUNCE AND NOISE REJECTION 

The MM5737 calculator chip is designed to interface 
with low cost keyboards, which are often the least 
desirable from a noise and false entry standpoint. 

A key closure is sensed by the calculator chip when one 
of the Key Input Lines, K1, K2 or K3 is forced more 
positive than the Logical High Level specified in the Elec- 
trical Specifications. At the instant of closure, an internal 
"Key Bounce-out Stability Time" counter is started. 
Any significant voltage perturbation occurring on the 
switched key input during timeout will reset the timer. 
Hence, a key is not accepted as a valid entry until noise 



or ringing has stopped and the stability time counter has 
timed out. Noise that persists will inhibit key entry 
indefinitely. Key release is timed in the same manner. 

One of the popular types of low cost keyboards 
available, the elastomeric conductor type, has a key 
pressure versus contact resistance characteristic that can 
generate continuous noise during "teasing" or tow pres- 
sure key depressions. The MM5737 defines a series 
contact resistance up to 50 kfi as a valid key closure, 
providing an optimum interface to that type of keyboard 
as well as more conventional types. 



8-10 



ERROR CONDITIONS 



Decimal Point 



In the event of an overflow, the MM5737 will display 
an "E" in the leftmost digit and at least seven of the 
significant digits of the answer. Division by zero results 
in an "E" with eight trailing zeroes. Once in an error 
condition, all keys except the clear key are ignored. 

KEY OPERATIONS 

Clear Key 

Operation after a number entry clears the entry and 
displays a previous result. Second depression clears all 
registers and displays a zero without decimal point in 
the LSD. Operation after a function key ( + , - x, 4- or =) 
clears all registers and displays a zero without decimal 
point. Two depressions are always required after power 
is applied. 

Number Entries 



First depression of this key in a number entry will enter 
a decimal point in the LSD position of the display 
register. Subsequent depressions of the decimal point 
key before any function key will be ignored. 

Add, Subtract, Multiply or Divide Keys 

First depression after a number entry will terminate the 
entry, perform the previously recorded operation, if 
any, and record the function key depressed as the next 
operation to be performed after another number entry. 
Subsequent depressions of any function key, without an 
interceding number or decimal point entry will supersede 
the previous function as the next to be performed. After 
an equal key, the displayed result of the equal operation 
will be re-entered and the function key depressed will 
become the next operation to be performed after a 
number entry is followed by another function key 
(including equal). 



First entry clears the display register and enters the 
number into the least significant digit (LSD) of the 
display register. Second through eighth entry shifts the 
display register left one digit and enters the number into 
the LSD. The ninth, and subsequent entries, are ignored 
and no error condition is generated. Because only seven 
positions are allowed to follow the decimal point, the 
eighth and subsequent entries after a decimal point 
entry are ignored. 



Equal 

First depression after a number entry will terminate the 
entry, perform the previously recorded operation and 
record the fact that an equal key has been depressed. 
Depression after the add, subtract or divide keys, with- 
out an interceding number or decimal point entry, will 
be ignored. After a multiply key, the number being 
displayed will be squared. 



DIGIT 
OUTPUTS 


" -i 


— INTERDIGIT BLAN 


- WORD TIME 

KING TIME 








D1 


i 






— ( 


-— DIGIT 


IME 






D2 




L 




i 














D3 


L 






i 










D9 


i 


1 1 


I 




, 




1 






DECIMAL POINT 






SEGMENTS 














u- 




i 




1 
















Sh I ' 


1 1 


















Sd i 


' 


1 
























1 1 1 












: 1 




Se i J 






1 1 1 




1 














Sf 

S9 

A 
DIS 








1 1 1 










' 






i i i 


7- 


01 
TUAL 

PLAV: 


02 03 09 ?5 

n 1 C C U D D / 
/_/ / /_/ _/ / _/./_ / 


DE D7 DB 09 

SEGMEN 
DESIGNATION 


D1 

i/T 

•c. 



FIGURE 2. Display Timing Diagram 



8-11 



CO 

in 




FIGURE 3. Ready Output Timing 



sample problems 

I. Single Calculations 

5 x 3.14 = 15.7 

Key 

C 
C 
5 



Display 



Comments 

Two clears are required after power-up. 





5 

5 

3 

3. 

3.1 

3.1 4 

1 5.7 



II. Chain Calculations 
A. 23.37 + 243.00-489.16= -222.79 
Key 

c 
c 

23.37 

+ 
243 

x 
(Wrong Function Key) 



489.17 

C 
489.16 



Display 





2 3.3 7 

2 3.37 

2 4 3 

2 6 6.3 7 

2 6 6.3 7 

48 9.1 7 
2 6 6.37 
4 89.1 6 
2 2 2.7 9 



Comments 



Function key completes previously recorded "+" operation. 
Wrong "X" function key is updated to "- ." 



Number entry error is cleared and corrected. Note the 
floating negative sign. 



8. Find square root of 169 using a modified Newton approximation method. Let N represent the squared number and X 
the initial estimate. The first approximation, X, , is 

X, = (N/X + X )/2 
If X is 15, 

X, = (169/15+ 151/2 
X 2 = (169/X, + X,)/2 
X 3 = (169/X 2 + X 2 )/2, etc. 



Key 

C 
C 
169 

15 

+ 
15 

2 

169 

13.13 



Display 





1 69 

1 69 

1 5 

1 12 66 666 

1 5 

26.2 666 66 

2 

1 3.1 3 33 33 

1 69 

1 69 

1 3.1 3 



Result is X, 



Four digits are conveniently remembered 



12 



sample problems (con't) 

II. Chain Calculations (continued) 

Key 

+ 
13.13 

2 



III. Auto Squaring 

A. 5.25 2 = 27.5625 

Key 

C 

C 

5.25 

x 

B. 5.25 5 = 3988.379 

Key 

C 

C 

5.25 



5.25 



Display 

12 8 7 1287 

1 3.1 3 

2 6.00 1 28 7 

2 

1 3.00 064 3 



Display 




5.2 5 
5.2 5 

2 7.56 25 



Display 




5.2 5 
5.2 5 

2 7.5 62 5 

2 7.5 62 5 

7 5 9.69 1 4 

7 59.69 1 4 

5.2 5 

39 88.3 7 98 



CJI 
W 



Result is X 2 , which is usually adequate. If more 
accuracy is required, continue the iteration 



Number in display register is squared. 



Comments 



Auto square = 5 25*" 
Auto square -= 5.25 4 

Result is 5 25 5 



8 13 




Calculators 



MM5758 scientific calculator 
general description 

The single-chip MM5758 Scientific Calculator is another 
MOS/LSI product from National Semiconductor using a 
metal-gate, P -channel enhancement/depletion mode tech- 
nology to achieve low system cost. A complete calculator 
performs a wide range of complex scientific problems, 
yet consists of only the MM5758, two display driver ICs, 
the NSA5101 LED display, a keyboard and power 
supply (Figure 1). No discrete components are required. 



An internal power-on clear circuit automatically clears 
all registers, including the storage memory and four- 
register operational stack, when power is initially applied 
to the chip. 



l Y 
IX 



The contents of the storage register M are replaced with 
the contents of the X-register by using the "STO" key. 
The memory recall key, "RCL," copies M into register X 
without disturbing the value of M. M is cleared auto- 
matically at power-on or by storing a zero. All registers 
contain eight mantissa digits, two exponent digits and 
the sign information for each. 



The MM5758 performs trigonometric, logarithmic, 
exponentiation, power and square root functions simply 
by pressing a key. It computes and displays numbers 
over a range of ±9.9999999 x 10'". A four-register 
operational stack simplifies computation of problems 
with multi-nested terms and reverse polish entry notation 
provides a logical and consistent method of keying in 
even the most complex problems. 

The displayed output has an eight digit mantissa with 
a two digit exponent; both the mantissa and exponent 
display an additional sign digit. Sign information is 
presented to the display by the calculator chip during a 
single digit time, but the NSA5101 display physically 
separates the two as shown in Figure 2. 

All computed results greater than 99999999. or le s 
than 0.1 are automatically converted to scientific 
notation. Trailing zero suppression of the mantissa 
allows convenient reading of the ieft justified display 
and conserves power. The exponent digits are blanked 
if no exponent is displayed. The most-significant-digit 
of the exponent is not blanked, even if it is a zero, when 
an exponent is being displayed. A low battery indication, 
activated by sensing circuitry in the DS8868, is included 
in the mantissa sign digit. 

A Ready output signal is used to indicate calculator 
status. It is useful in providing synchronization informa- 
tion during testing and when the MM5758 is used with 
other logic; e.g., with the MM5766 Programmer. 

Thirty-six keys are arranged within a four-by-eleven 
matrix (Table 1 and Figure 2). Dual function keys are 
not required. 

The user has access to five registers designated X, Y, Z, 
T and M. X is the display and entry register and the 
bottom of a "push-up" operational stack that includes 
registers Y, Z and T. 



features 

■ Enters, computes and displays numbers as large as 
±9.9999999 x 1 99 and as small as ± 1 x 1 0~" 

■ Complete slide-rule capability 

• Arithmetic functions: +, - x, +, 1 /x , Vx 

• Logarithmic functions: In x, log x, e", 10 x 

• Power function: Y* 

• Trigonometric functions: sin x, cos x, tan x, 
arc sin x, arc cos x, arc tan x 

• Other functions: 7r, exchange, change sign 

■ Reverse polish notation 

■ Four-register operational stack with roll capability 

■ Independent two key storage register 

■ Floating point input and output 
" Power-on clear 

■ Designed-in low system cost 

■ Automatic display cutoff 



sample keyboard 



arc 


sin 


COS 


tan 


■| 


log 


10 ' 


In 

m 


e x 


yX 


m 


1t 


*~> 


MR 


MS 






7 8 9 -i- 
4 5 6 x 
12 3- 


ROLL! 




EE 




CHS 







H 




+ 


ENTf 



8-14 



operating voltage range 



Vss is always the most positive supply voltage. 



absolute maximum ratings 

Voltage at Any Pin Relative to V ss V ss + 0.3V to V ss - 12V 7.2 V<V SS -V DD < 8.8V 

(All other pins connected to V^) 

Ambient Operating Temperature 0°C to +70°C 

Ambient Storage Temperature -55° C to +150°C 

Lead Temperature (Soldering, 10 seconds) 300°C 

dc electrical characteristics 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Operating Supply Current (l DD ) 


v OD "" v ss -8.8V. T A - 25°C 




12.0 


20.0 


mA 


Keyboard Scan Input Levels 












IK1 through K4) 












Logical High Level 




Vss 2 5 






V 


Logical Low Level 








V DD -1.5 


V 


Display Reset Input Levels 












Logical High Leve 




Vsa-1.5 






V 


Logical Low Level 








V DD + 1.5 


V 


Encoded Digits Output Current 












iD A through D D ) 












Logical High Level (Iqh) 


Vout -V D= • 1 0V 


--0.5 




-250 


mA 


Logical Low Level o i ) 


Voot =V DD 






-50 


PA 


Low Voltage Indicator Level (V IH ) 




Vqd-2-8 




v ss 


V 


(Digit D A must be forced to a V. H 












voltage level during the IDLE digit 












time to cause Segment S b to be turned 












"ON" at digit time D1. 












Segment and Decimal Point Output 












Current (Sa through Sg, DP} 












Logical High Leve! (i OH 1 


Volt = V DD t 5.4V 


550 






pA 


Lcgical Low Level o . ) 


Vout *■ V DD • 1 5V 






-10 


.a A 


Ready Output Levels 












Logical High Level !V OH ) 


Iqijt - 0.4 mA 


V cc 1 






V 


Logical Lov.< Level (V . ) 


out " 10pA 






V DD + 1.0 


V 



ac electrical characteristics 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Word Time (Figure 3) 




5 


13 


2.2 


ms 


Digit Time (Figure 3) 




42 


108 


183 


Ps 


Interdigit Blanking Tims (Figure 3) 




3 5 


8.0 


14.0 


PS 


Keyboard Scan Inputs (K1 through 


C.OAD ' IMP' 






14.0 


PS 


K4) Low to High Transition T,me 












(during Interdigit Blanking Time), 












<t PDH > 












Ready Output Propagation Time 












(Figure 4! 












Low to High Level (t PDH ) 


Cload - 100 oF 


30 




115 


ps 


High to Low Level (tp DL ) 


Cload " 100 pF 


30 




120 


ps 


Key Bounce-out Stability Time 




3 5 


9.1 


15.4 


ms 


(The time a keyboard scan input. 












K1, K2, K3or K4, must be continu- 












ous y connected to a digit to be 












accepted as a key closute, or lower 












than the maximum Logical Low 












Level to be accepted as a key 












release.) /Figure 5j 












Display Cutoff Time 






50 




second 


(The time after the last valid key 












closure at which all digits except 












the most-significant digit of the 












mantissa will be blanked.) 












Calculation Times 












Square Roof 






0.50 


0.90 


second 


LOG X or LN X 






0.85 


1.50 


second 


10" or e x 






1.00 


1 75 


second 


Y' 






1.80 


3.10 


second 


SIN X, COS X or TAN X 






1.30 


2.20 


second 


ARC SIN X or ARC COS X 






1.40 


2.40 


second 


ARC TAN X 






0.85 


1.50 


second 



(OPTIONAL) / 



DISPLAY V^ SEGMENTS 

RESET 
K MM575B 

INPUTS 

V, )D D -D B C a 



KEYBOARD 

MATRIX 

(SEE FIGURE 2 

AND TABLE 1] 



"j. O O O O O CI O O <•> O '/T/b 

I.) /_/. /_/. /_/. /_/. /_/. /_/. /_/. /_/. " /_/ 'l±l< 



D1 D2 D3 



DB D9 DID DM D12 



DECODED DIGITS 



DIGITS 
DS8BG8 



3EA- 
MALLORV 

MN15DD - 
OR EOUIV - 



^o- 



FIGURE 1 . Block Diagram of Complete Handheld Scientific Calculator Using MM5758. 



/■ 



' S>1 ' S>^ K ' S^ ' SA ' 



' S>1 ' S>i ' S>^ c ' S>1 



-^=» 



-i»- 



Dl D2 03 D4 D5 



D8 D9 D1D DM D12 



1 2 3 4 6 8 10 12 14 18 20 21 



[) Dl D2 D3 D4 05 D6 



FIGURE 2, Digits Interconnection Detail For Scientific Calculator. 



-16 



SCALING OF DISPLAYED NUMBERS 



AUTOMATIC DISPLAY CUTOFF 



Computed results are displayed in either floating point 
or scientific notation. Answers in the range between 0.1 
and 99999999. are displayed in floating point format; 
otherwise scientific notation is used. For example: 123.4 
is displayed as written; whereas, 123.4 million would 
appear as 1.234 x 10 8 . The smallest magnitude displayed 
is ±1.0 x 10"", and the largest ±9.9999999 x 10 99 . 
Number entries are always displayed in the manner 
entered until "ENT" is depressed, after which they 
appear scaled. 

KEYBOUNCE AND NOISE REJECTION 

The MM5758 is designed to interface with most low-cost 
keyboards, which are often the least desireable from a 
false or multiple entry standpoint. 



If no key is depressed for approximately 50 seconds, an 
internal automatic display cutoff circuit will modify the 
encoded digit output sequence sent to the DS8868 
Decoder'Driver to be the blanking input code (Table II) 
during all digit times except the most-significant of the 
mantissa (D2). Thus, in the cutoff power saving mode, 
only one digit is displayed. The blanking code has been 
selected to also be the minimum power case for the 
DS8868. 

Any of the D1 1 ("CS," "it" or "TAN") keys will restore 
the display; to restore the display without modifying 
the status of the calculator use the "CS" key twice, or 
momentarily force the Display Reset high. The auto- 
matic display cutoff feature can be disabled by hardwiring 
the Display Reset pin to V ss . 



When a key closure is sensed by the calculator, an 
internal timeout is started. Any voltage perturbations 
of significant magnitude which occur on the Key Input 
Lines (K1, K2, K3 or K4) during the timeout will reset 
the timer to zero. A key is accepted as valid after a 
noise-free timeout period; noise that persists indefinitely 
will inhibit key entry. Key releases are checked in the 
same manner. 

The internal timeout period (Key Bounceout Stability 
Time) is normally seven word times. By forcing digit D B 
to a Logical High State during Digit Timing State D12 
time (Table II), the Stability Time is reduced to four 
word times. 



READY SIGNAL OPERATION 

The Ready signal indicates calculator status. When the 
calculator is in an "idle" state the output is at a Logical 
High Level (near V ss ). When a key is closed, the internal 
key entry timer is started. Ready remains high until the 
time-out is completed and the key entry is accepted as 
valid, then goes low as indicated in Figures 4 and 5. It 
remains at a Logical Low Level until the function 
initiated by the key is completed and the key is released 
and timed out. The low to high transition indicates the 
calculator has returned to an idle state and a new key 
can be entered. 



TABLE I. Keyboard Matrix 



SWITCH 
INPUTS 


DIGIT TIMING STATES 


D1 


D2 


D3 


D4 


D5 


D6 


D7 


D8 


D9 


D11 


D12 


K1 







9 


8 


7 


6 


5 


4 


3 


2 


1 


K2 


- 


CS 


STO 


1 X 


~- 


C 


EN 


\'X 


+ 


X 


- 


K3 




T 






RCL 


ARC 


ROL 








EEX 


K4 




TAN 


SIN 


COS 




LOG 


V" 


LN 


e' 




10" 



TABLE II. Digits Timing State Truth Table 



ENCODED DIGITS 


DECODED DIGIT STATES IDS8868) 


Do 


Dr 


Dr 


Da 


D1 


D2 


D3 


D4 


D6 


D6 


D7 


D8 


D9 


D10 


D11 


D12 


H 


H 


L 


L 


ON 
























H 


H 


H 


H 




ON 






















L 


H 


H 


H 






ON 




















H 


L 


H 


H 








ON 


















L 


H 


L 


H 










ON 
















H 


L 


H 


L 












ON 














H 


H 


L 


H 














ON 












L 


h 


H 


L 
















ON 










L 


L 


H 


H 


















ON 








H 


h 


H 


L 




















ON 






L 


L 


L 


H 






















ON 




H 


L 


L 


L 
























ON 


L 


L 


L 


L 



























ON DS8868 output buffer will sink ^ 110 mA @ VquT _-. ° 4V 
H Logical High State ( - Vgg) 
L " Logical Low State ( "^ Vqq! 



8-17 




BATTERY ,j ,. ... 

LOW VOLTAGE Sa J M M I 

iiunirflTno. * 



ACTUAL DISPLA' 



r LOW BATTERY VOLTAGE INDICATOR 

/ 3 3 U C C ~U3 _ no 
1 1 / /._//_/ /_/ /_//_/ 

FIGURE 3. Display Timing Diagram 



«— —. MANTISSA MEG 

SEGMENT S, /S g /Sh *Gli S 5 

DESIGNATION: s # I EXPONENT NEG 

/__/ SIGN-Sa 



ANY DIGIT 

IGNAl CONNECTED 

THROUGH KEY 

TO K LINE 



FIGURE 4. Ready Timing 





1 


- - 


7 WORD 


TIMES- 






i 






ANY 
SWITCH 


IP'" 


II 


|| 


|| 


II 


II 




I' 


U \ 


INPUT 


"x 


u 

NOISE 


u 


u 


u 


u 

"NOISF" 


" 




7 WORD TIMES 
AFTER KEY 
RELEASE 0(1 : 
CALCULATION : 

IS COMPLETED. 

WHICHEVER IS 



NEW KEY HAS BEEN ACCEPTED j 
BY CALCULATOR. THE KEY- 
MAY BE RELEASED 



FIGURE 5. Functional Description of Ready Signal and Key Entry. 



ERROR INDICATION 

In the event of an operating error, the MM5758 will 
display all zeros and decimal points. Improper operations 
or calculations are summarized in Table III. All square 
root computations are of the absolute value of X; 
therefore, the square root of a negative number is not 
considered an invalid operation. 

An error condition is reset by pressing "C." All registers 
in the stack are lost and replaced with zeros. M is saved. 



TABLE HI. Conditions for Error Indication 



FUNCTION 


CONDITION (REGISTER X - 


X) 


^ or 1/X 


X! - 




Y* 


Y < 0, X LOG Y > 99 




e" 


X > 230 




10" 


IX l> 99 




LOG X or LN X 


X < 




SIN X. COS X, TAN X 


X < or X > 90 




ARC SIN X or ARC COS X 


X < or X > 1 




ARC TAN X 


X< 





KEY OPERATIONS 



Enter Exponent Key, "EEX" 



Clear Key, "C" 

Clears X, pushes Y down to X, Z to Y, T to Z and places 
a zero in T. Subsequent depressions perform the same 
operation; thus, four "C" depressions will clear a 
completely full stack. If the display indicates an error 
condition exists, the "C" key clears X, Y, Z and T. 
Storage memory M is not affected by any "C" operation. 

Number Entries 

The first numeral of a number entry following any 
function, other than "EN," raises the stack and T is lost. 
Numerals are entered and displayed from left to right. 
Following "EN" the first number entry is placed in X 
without affecting the rest of the stack. Ninth and 
subsequent entries of the mantissa are ignored; third 
and subsequent entries of the exponent are entered as a 
new least-significant-digit, and the previous most-signifi- 
cant-digit is lost. 

Decimal Point, "." 

Places a decimal point on the right side of the least- 
significant-digit being displayed during entry of the 
mantissa. It is invalid during exponent entry and clears 
the X-register to zero (starting a new number entry). 

Change Sign Key, "CS" 

Changes the sign of X. In the exponent entry mode, it 
changes the exponent sign. It does not terminate entry 
and therefore can be depressed at any time during the 
entry mode. Multiple depressions are allowed. 

Enter Key, "EN" 

Register T is lost, Y and Z are pushed up and X is copied 
into Y. 

THE FOUR FUNCTION KEYS, "+," "-," "x," and 



Add key, "+" 
Subtract key, "— " 
Multiply key, "x" 
Divide key, "^" 

Pi Key, "rr" 



Register T is lost; X, Y and Z are pushed up in the stack 
and the constant 3.1415927 is placed in X. 

Exchange Key, "<— >" 

Registers X and Y are exchanged; other registers are not 
affected. 

Inverse Trigonometric Key, "ARC" 

Preceding one of the three trigonometric keys, "SIN," 
"COS" or "TAN," it conditions the calculator to 
determine the angle in degrees of the value in register X. 
"ARC" followed by any key other than one of the 
trigonometric keys will be ignored. 




Puts calculator in exponential entry mode. "EEX" must 
be preceded by a number (mantissa), or it will be 
ignored. A decimal point is an invalid entry that changes 
X to zero. 

Trigonometric Keys, "SIN," "COS," and "TAN" 

Assumes the value of X is an angle in degrees and 
computes the indicated trigonometric function, replacing 
X with the result. Register T is replaced by a zero; 
M, Z and Y are not affected. Following "ARC," the 
trigonometric keys determine the angle represented by 
the function in X, and replace X with that value in 
degrees. T is replaced by a zero; M, Zand Y are unchanged. 

Reciprocal Key, "1/X" 

A non-zero value of X is replaced by its reciprocal. 
Registers Y, Z, T and M are unaltered. 

Square Root Key, "\/X " 

The absolute value of X is replaced by its square root. 
Registers Y, Z, T and M are not altered. 

Logarithmic Keys, "LN" and "LOG" 

These keys replace the value of X by its natural or 
common logarithm, respectively. Registers Z and T 
become zero. Registers Y and M are not affected. 

Power Key, "V" 

Determines the value of Y raised to the power of X and 
replaces X with that result. Registers Y, Z and T become 
zero. M is not affected. 

Exponential Keys, "e x " and "10 x " 

The constants 2.7182812 or 10.0 are raised to the 
power of X, respectively, and placed in X. Register T 
becomes zero; Y, Z and M are not affected. 

Memory Keys, "STO" and "RCL" 

The memory store key, "STO," copies the value of X 
(including sign) into storage register M, without altering 
the stack. The recall key, "RCL," transfers Z to T, 
Y to Z and X to Y, then copies M into X. Storage 
register M is not changed and T is lost. Both "STO" 
and "RCL" terminate an entry mode. 

Roll Stack Key, "ROL" 

Repositions the data within the operational stack by 
transferring X to T, Y to X, Z to Y and T to Z. After 
four successive depressions each of the four data posi- 
tions has been viewed and returned to its original location. 

Range and Accuracy of Functions 

The smallest magnitude that can be displayed is ±10"" 
and the total rang 



:9.9999999 x 10". Table IV 
summarizes range and accuracy of the MM5758 functions. 



8 19 



00 
Mi 

in 



FUNCTION 


RANGE 


ACCURACY 


+ , -, X,+, 1/X 


± 1 x 10 " < X < ±9.9999999 x 10" 


±1 in first non-zero digit from 


LSD 


V^<" 


±1 x 10 99 !< X< I+9. 9999999 x 10 99 l 


±2 in first non-zero digit from 


LSD 


LOG X 


< X < +9.9999999 x 10" 


7 digits 




LN X 


< X < +9.9999999 x 10" 


7 digits 




10* 


+ 1 x 10^ 9 <X<+99 


5 digits 




e x 


±1 x 10^ 9 <X < +230 


5 digits 




yx 


Y > 0, with X and Y values such that the 
results will be +1 x lO^ 59 < X< 
+9.9999999 x 10 99 


5 digits 




SIN, COS, TAN 


< X < +90 


7 digits 




ARC SIN, ARC COS 


0<X<+1 


5 digits 




ARC TAN 


< X < 9.9999999 x 10 99 


5 digits 





*Error in last useable digit is less than 5 



| t" | / »- LOST 


/ 
/ 


*- 2 

*- Y 





m 







\ 


T 


^^_ 


— V 


\ 


^ »- LOST 



Summary of Stack Operations 

| | | 1 | | 2 | ... | 9 j | * | | - | AFTER FUNCTION KEY 






q.cilII"- ran □ a™ ^ 

t ^ T OR FIRST NUMBER 



ED 



Q 



yz 



■ LOST 

- LOST 

LOST 



| SIN | | COS | [TAW I | „■ | | 10» | 8, 
| ARC| FOLLOWED BY | SIN | | COS | | TAN | 

o w *- L0ST 

t A _ T 



E.GU 



lzhzhzilzi 




8-20 







Summary of Stack Operations (con't) 






r^i 




[ScT] 






t »- T 




, »- LOST 






y »- Y 




, / -Z 

V ' , »- v 






. ^ ^X 








r ■— ■■> NOTE; IF AFTER EEX THEN 
I CS I CS OF EXPONENT. 




m * ^- M 

| E E X | AFTER FUNCTION 






I »- T 

i m- Z 




1 fc- T 

i »- Z 






x _csx ^ x 




x »- X (EEX IS IGNORED! 










[ EEX [ AFTER NUMBER ENTRY 

t »- T 

« »- Z 






x : ,; 




x "»- X (READY FOR 

^ M EXPONENT) 






ERROR CONDITION 




| LN | | LOG | 

' L. 

i . ^_ LOST N »- t 

z *- LOST ^ — »— Z 

V- *- Y 


t — m~ LOST 
' — »- LOST 
V — "- LOST 


h *"" T 

' »- Z 

* »- Y 






x fc- LOST *• •»- X 

m »~ M 




f ^x 

m »^ ivi 

fix) ' 


SAMPLE PROBLEMS 








Problem No. 


1 1.345 + 7120 


- 14251 = ? 

STACK REGISTERS 






KEY ENTRY 


DISPLAY X 


Y Z 




T MEMORY M COMMENTS 


POWER ON 
1 


0. 

1 








Power on clears all registers and 
memory 


3 


1. 
1.3 








4 


1.34 








5 


1.345 








ENTER 


1.345 


1.345 




Copy X in Y 


7 
1 


7 
71 








2 


712 











7120 








+ 
1 


7121.345 

1 



7121.345 




Add X and Y 


7 


17 








CLR 
1 


7121.345 
1 



7121.345 




Clear entry, pushes down stack 


4 


14 








2 


142 








5 


1425 








1 


14251 


7121.345 










-7129.655 








Subtract X from Y 

Note: It is not necessary to clear 
calculator for the next problem. 



2 
w 

00 



ED 



8-21 



Problem 


No 


2 (3.73x1CT 7 )x 


(-15 x 10 24 K 


27357.3 = ? 
















STACK REGISTERS 






KEY ENTRY 


DISPLAY X 




Y 


Z T 


MEMORY M 


COMMENTS 


3 




3 
3. 




7129.655 








The new number entry pushes the 
answer of the last problem up in 
the sleek 


7 




3.7 












3 




3.73 












EEX 




3.73 










Prepare for exponent entry 


7 




3.73 


07 










CHS 




3.73 


-07 








Change sign of exponent 


ENTER 




3.73 


-07 


3.73 07 


-7129.655 






1 
5 




15 












CHS 




-15 










Change sign of mantissa 


EEX 




-15 












2 




■15 


02 










4 




-15 


24 










x 




5.595 


18 


-7129.655 








Multiply X and Y 


2 




2 




-5.595 18 


-7129.655 







7 




27 












3 




273 












5 




2735 












7 




27357 
27357. 












3 




27357.3 












V 




-2.0451579 


14 


-7129.655 







Divide Y by X 


CLR 




-7129.655 











Clear Answer 


CLR 




0. 













Clear answer from problem 1 
Note: This is not necessary. It is 
done here to avoid confusion of 
stack operation in the next problem. 


Problem 


No 


3 Vl0.3(3 2 +4 2 


) (5 2 +6 2 ) 


















STACK REGISTERS 






KEY ENTRY 


DISPLAY X 


Y 


Z T 


MEMORY M 


COMMENTS 


10.3 




10.3 















ENTER 




10.3 




10.3 






The "Roll" key can be used 
to examine the stack. It is not 
necessary for the solution. 


3 




3 




10.3 








ENTER 




3. 




3 


10.3 




Register contents displayed: 


ROLL 




3. 




10.3 


3 




Y 


ROLL 




10.3 







3 3 




Z 


ROLL 









3 


3 10.3 




T 


ROLL 




3. 




3 


10.3 




X 


X 




9. 




10.3 







3 2 


4 




4 




9 


10.3 






ENTER 




4 




4 


9 10.3 






X 




16. 




9 


10.3 




4 2 


+ 




25. 




10.3 







!3 2 t 4 2 ) 


x 




257.5 













10.3 (3 2 i 4 2 l 


5 




5 




257.5 










ENTER 




5 




5 


257.5 






X 




25. 




257.5 







5 2 


6 




6 




25. 


257.5 






ENTER 




6 




6 


25 257.5 






x 




36. 




25 


257.5 




6 2 


+ 




61. 




257.5 







(5 2 +6 2 ) 


x 




15707.5 











10.3 (3 2 + 4 2 | (5 2 +6 2 ) 


Vx" 




125.32956 













v'10.3 (3 2 f 4 2 ) (5 2 +6 2 ) 



822 



Problem 


No 


1 
4 1 + — X 
2! 


3 


-X 2 = ?, X 


= -0.15 

STACK REGISTERS 




KEY ENTRY 


DISPLAY X 




Y 


Z 


T 


1 




1 




125.32956 








ENTER 




1. 




1 


125.32956 




2 




2 










1 

X 
0.15CHS 




0.5 
-0.15 




0.5 


1 


125.32956 


STO 




-0.15 










X 




-7.5 


02 


1 


125.32956 





-f 




0925 




125,32956 







3 




3 




0.925 


125.32956 




ENTER 




3 




3 


0.925 


125.32956 


2 




2 










X 




6. 




0.925 


125.32956 





1 

X 
RCL 




0.1666666 
-0 15 




0.925 
0.1666666 


125 32956 
0.925 




125 32956 


ENTER 




-0.15 




-0 15 


01666666 


0.925 


X 




2.25 


02 


1666666 


0.925 





X 




3.7499985 


-03 


0925 








MEMORY M 



COMMENTS 



•J 
00 



Store X for use later in the problem 



1 + -X 
2' 



CLR 
RCL 



0.9287499 


-0.15 



-0.15 


3 






-0.15 


X 








Answer 


to last problem 


s lost he 




X 2 








3! 








i-lx 

21 


3! 





Notice that the clear does not affect 

the memory register. Memory is changed 
only by storing another value or by power 
off. 



Problem No. 5 tt{21) 



21 2 [rr) = ? 









STACK REGISTERS 




KEY ENTRY 


DISPLAY X 


Y 


Z 




7T 


3.1415927 


-0.15 








21 


21 


3.1415927 


-0.15 




X 


65.973446 


-0.15 







21 


21 


65.973446 


0.15 




ENTER 


21 


21 


65973446 


-0.15 


X 


441. 


65.973446 


-0.15 





T, 


3.1415927 


441 


65.973446 


-0.15 


X 


1385.4423 


65.973446 


-0.15 






MEMORY M 

-0.15 



COMMENTS 



-(21) 
21 2 

21 2 (7Ti 



01 



Problem No. 6 Example using Exchange and Reciprocal ke\s. 

STACK REGISTERS 
KEY ENTRY DISPLAY X Y 



5 
ENTER 



EXCH 
EXCH 



5 
5. 
1 

5. 
0.2 



0.2 
0.2 
0. 



1385.4423 
5 



1385.4423 
2 



0.2 
2 
1385.4423 



z 


T 


MEMORY M 


COMMENTS 


65.973446 


-0.15 


-0 15 




1385.4423 


65.973446 







65.973446 
13854423 



1385.4423 
1385.4423 
65 973446 



X 
CLR 



0.0.0.0.0.0.0.0. 
0. 



65.973446 
65.973446 

65.973446 
65.973446 





8-23 



Compare the answers obtained by 
exchanging X and Y. In this case, 
they are identical. 



Compare by subtracting zero error 
Divide by zero. Error clears all registers 



After clearing an error, all registers are 
zero. Memory is not disturbed. 



Problem No. 7 Example using "10 x " and "LOG" keys 

STACK REGISTERS 

Y Z 



KEY ENTRY DISPLAY X 



1.2345678 

STO 

10* 

LOG 

RCL 

EXCH 

EXCH 

4 

ENTER 

3 

ENTER 

2 

ENTER 

1 



ENTER 

3 

ENTER 

2 

ENTER 

1 



1.2345678 
1.2345678 
17 161995 
1.2345678 
1.2345678 
1.2345678 
1.2345678 







MEMORY M 




COMMENTS 


-0.15 






1.2345678 


Store c 


riginal value 



2 
2 
2 

10. 



1.2345678 



3 
3 
3 
2 
10. 



Problem No. 8 Example using "e x " and "LN" keys 



STACK REGISTERS 



KEY ENTRY 


DISPLAY X 


Y 






8.7654321 


8.7654321 


2.2 


-07 


2 


STO 


8.7654321 








e* 


6408.8309 








LN 


8.7654321 









RCL 


8.7654321 


8.7654321 




2 




0.0 


2.2 


-07 






Problem No. 9 2 



10 



KEY ENTRY 

2 

ENTER 
10 



DISPLAY X 

2 

2. 

10 

1024.0037 



STACK REGISTERS 

Z 



8.7654321 
2 



Problem No. 10 Trigonometric computations 



KEY ENTRY DISPLAY X 



STACK REGISTERS 

Z 



30 

SIN 

ARC 

SIN 

4 

ENTER 

3 

ENTER 

2 

ENTER 

1 



4 
ENTER 



30 

0.5000002 
0.5000002 
29.999556 



1024.0037 
29.999556 



1.7452415 -02 



3 4 

2 3 

2 3 

1.7452415 02 2 



1024.0037 

29.999556 

4 





1.7452415 02 2 



1.2345678 
1.2345678 



1.2345678 



2.2 -07 

8.7654321 



MEMORY IV! 

8.7654321 



8.7654321 
8.7654321 



Compare answer to original value 
Fill the stack 



Notice that "T" is lost (same for 10", e 



Notice that "Z" and "T" are lost (same fo 
LOG, LN) 



1.2345678 

8.7654321 Store original value 



s. 7654321 Compare answer to 

original. Error is 0.0 



MEMORY M 

8.7654321 



COMMENTS 



Notice that "Y," "Z" 
and "T" are lost 



COMMENTS 

Enter X in degrees 

Sine of 30' is computed 

ARC sine is computed 



Notice that "J" is lost (same for SIN, 
COS, TAN) 



824 



Problem No. 10 (con't) 



KEY ENTRY DISPLAY X 

3 3 

ENTER 3, 

2 2 

ENTER 2. 



1 



1 



ARC 1. 

SIN 89.999997 



STACK REGISTERS 

Z 



MEMORY M 



1.7452415 -02 



-J 

Ul 

oo 



Notice that "T" is lost (same for 
ASIN, ACQS, ATAN) 



Problem No. 11 

KEY ENTRY DISPLAY) 

30 30 

COS 0.8660252 

ARC 0.8660252 

COS 29.999569 



STACK REGISTERS 

Z 



MEMORY M 

8.7654321 



Problem No. 12 

KEY ENTRY DISPLAY > 

45 45 

TAN 09999991 

ARC 

TAN 45.000629 



STACK REGISTERS 
Z 



MEMORY M 

8.7654321 



connection diagram 



Dual-ln-Line Package 



SWITCH 
INPUT 
LINES 



-READY 
-DISPLAY flESFT 
-SEGMENT F 
-SEGMENT B 
-SEGMENT G 
-SEGMENTD 

- SEGMENT E 

- SEGMENT A 

- DECIMAL POINT 
-SEGMENT C 



01 



Order Number MM5758N 
See Package 22 



825 




Calculators 



MM5760 slide rule calculator 
general description 

The single-chip MM5760 Slide Rule Calculator was 
developed using a metal-gate, P-channel enhancement 
and depletion mode MOS/LSI technology with the 
primary objective of low end-product cost. A complete 
calculator as shown in Figure 1 requires only the 
MM5760, a keyboard, DM8864 digit driver, NSA298 
LED display and a 9V battery with appropriate hardware. 

Keyboard decoding and key debounce circuitry, all 
clock and timing generation and 7-segment output dis- 
play encoding are included on-chip and require no 
external components. Segments can usually be driven 
directly from the MM5760, as it typically sources about 
8.5 mA of peak current. (Note: the typical duty cycle 
of each digit is 0.104; average LED segment current is 
therefore approximately 0.89 mA.} The left-most digit 
is used for the negative sign or the decimal point of a 
number less than unity. 

An internal power-on clear circuit clears all registers, 



including the memory, when V DD 
applied to the chip. 



and V ss are initially 



Trailing zero suppression allows convenient reading of 
the left justified display, and conserves power. The 
DM8864 digit driver is capable of sensing a low battery 
voltage and providing a signal during Digit 9 time that 
can be used to turn on one of the segments as an 
indicator. Typical current drain of a complete calculator 
displaying five "5's" is 30 mA. Automatic display cutoff 
is included. If no key closure occurs for approximately 
35 seconds, all numbers are blanked and all decimal 
points displayed. 

The Ready output signal is used to indicate calculator 
status. It is useful in providing synchronization informa- 
tion during testing and when the MM5760 is used with 
other logic or integrated circuits; e.g., with the MM5765 
Programmer {Figure 3). 

Thirty-two keys are arranged in a four-by-nine matrix 
{Figure 1). In addition to seven arithmetic functions 
plus logarithmic, trigonometric and accumulating mem- 
ory functions, the calculator is capable of calculating Y x , 
adding the square of X to memory, automatically 
entering tt and providing degrees/radian conversions. 

The user has access to four registers designated X, Y, Z 
and M. X is the display and entry register, and is the 
bottom of a "push-up" stack that also includes registers 
Yand Z: 



features 

■ Full 8-digit entry and display capacity 

■ Complete electronic slide rule capability 



1/x, 



• Arithmetic functions: +, -, x, +, 

• Logarithmic functions: In x, log x, e x 

• Trigonometric functions: sin x, cos x, tan x, arc 
sin x, arc cos x, arc tan x 

• Other functions: Y x , tt, change sign, exchange, 
x 2 + memory -*■ memory, radians to degrees, 
degrees to radians 

Three-register operational stack 

Independent accumulating storage register with store, 

recall, memory plus and memory minus functions 

Floating point input and output 

Direct 9V battery compatibility; low power 

Power-on clear 

No external components required other than display 

digit driver, keyboard and LED display for complete 

calculator 

Error indication for over range, overflow and invalid 

operations 

Left justified entry and results with trailing zero 

suppression 

Automatic display cutoff 

Reverse polish notation 



connection diagram 



Dual-ln-Line Package 



digit 3 - 

DIGIT2- 



SEGMENT G - 

1 
SEGMEMT B - 

SEGMENT F- 



- DIGIT 4 

- DIGIT 5 

- DIGIT 6 

- DIGIT 7 

- DIGIT B 
L DIGIT 9 
-READY 



-DECIMAL POINT 
- SEGMENT C 



Note: Lower case letters designate the data in the register 
identified by a capital letter. 



TOP VIEW 

Order Number MM5760N 

See Package 22 



826 



12V 



absolute maximum ratings 

Voltage at Any Pin Relative to V ss V ss + 0.3V to V ss ■ 
(All other pins connected to V ss ) 

Ambient Operating Temperature 0°C to +70°C 

Ambient Storage Temperature -55°C to +150°C 

Lead Temperature (Soldering, 10 seconds) 300°C 



dc electrical characteristics 



operating voltage range 

6.5V < V ss -V DD <9.5V 

V ss is always defined as the most positive supply voltage. 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Operating Supply Current (i DD l 


V DD - V ss 9.5V, T a -25°C 






16.0 


mA 


Keyboard Scan Input Levels 












IK1, K2, K3 and K4) 












Logical High Level 


V SS -6.5V < V nD < V ss 9.5V 


Vss 2.5 






V 


Logical Low Leve 


V DD = V ss 6.5V 






Vss -5-0 


V 




V DD - V ss -9.5V 






Vss-6.0 


V 


Digit Output Levels 












Logical High Level IV OH ) 


Rload = 3.2 kf> to V DD 












V ss -6.5V < V DO < V SS -9.5V 


Vss-1-5 






V 


Logical Low Level (V OL ) 


Vod = V SS -6.5V 






V ss 6.0 


V 




Vdd = V ss -9.bV 






V S s-70 


V 


Segment Output Current 


T A =25'C 










(Sa through Sg and Decimal Point) 


Vout = V SS -3.6V, V DD = V SS -6.5V 


5.0 


-8.5 




mA 




Vout = V SS -5V, V DD - V SS -8V 




-10.0 




mA 




Vout = V SS -6.5V. V DD -- V SS -9.5V 






-15.0 


mA 


Ready Output Levels 












Logical High Level (V OH ) 


Iout = -0.4 mA 


Vss 1-0 






V 


Logical Low Leve) |V OL ) 


l OUT = 10/jA 






V DD + 1.0 


V 



ac electrical characteristics 



PARAMETER 



Word Time (Figure 2) 

Digit Time (Figure 2) 

Segment Blanking Time (Figure 2) 

Digit Output Transition Times 
Urise and t FALL ) 

Keyboard Inputs High to Low 
Transition Time After 
Key Release 

Ready Output Propagation Time 

(Figure 3) 

Low to High Level (t PDH ) 
High to Low Level (t PDL ) 

Key Input Time-out 
Key Entry 
Key Release 

Display Cutoff Time 

(The time after the last valid key 

closure that all numbers will be 

blanked and all decimal points 

displayed.) 



CONDITIONS 



Cload = 100 pF, R LOflD =9.6kH 
Cload = 100 pF 



Cload = 100 pF 
Cload = 100 pF 



MIN 



0.32 

36 

2 



TYP 



0.65 
70 
4.5 
2 



6.0 
10.4 



MAX 



13 
145 
9 



50 
1 



11.7 
20.5 



)JS 

Ms 



ms 
ms 



01 

o 



3-27 



o 

(0 

in 

2 
5 



READY 

Sb Sc Sd Se Sf Sg DP 
MM5760 
K4 Q1 02 03 D4 D5 D6 GJ 1 



o n o o o o o o o 
/_/. o. /_/. /_/. /_/. /_/. /_/. /_/. /_/. 



□9 08 D7 06 



-f 9V 
-±" MALLQRY 
-^- MM604 
— — OR 
T- EttUIV. 

,ER \ 

y 



FIGURE 1. Complete Calculator Schematic 



OUTPUTS 
01 


— .- 




























— 


--DIGIT! 


IME 












D2 










1 




















03 






f 




















D9 




1 






















J 
























Sa 


J 


J 


1 


J 


J 


II 1 




J 


1 




^ 


|— SEGMENT BLAPJKING TIME 








Sb 




LI 


u 


1 1 


1 


II 1 


J LI 


II 


















Sc 




1 J u 


U 


J 


II 1 


1 


1 














Sd 


1 


J 


il 


J 


1 1 




i 


II 














1 






Sp 


J 


tJ 


,1 1 


i 


i 


















Sf 




J u 


U 


,1 1 










(- ! 












Sg 


J LI LI U 


U 


1 1 




i 

h 


II 


ACTUAL 01 


PLAY: J 






/ -/ Zl 1 
-i.i- i 




SEGMENT 
OESlGNIXTlQfv 


'/i 





FIGURE 2. Display Timing Diagram 



The contents of the accumulating storage register M are 
replaced with the contents of the X register by using the 
"STO" key. Preceding "+" or "-" with the "ARC" key 
sums X into M, or subtracts X from M. "ARC" followed 
by "STO" squares X and sums it into the memory 
without changing the value of X. The memory recall 
key, "RCL," copies M into X without disturbing the 
value of M. Storage register M is cleared automatically at 



power-on or by storing a zero. All registers contain eight 
digits and sign information. 

Inputs are entered and outputs displayed in floating 
point. The output results are truncated. Data entry 
always precedes the operation keys that operate on 
them; this is referred to as Reverse Polish notation. 
(See examples.) 



















1 1 






















(7) 






SLIDE RULE 
CALCULATOR 










1 


DISPLAY 








(4) 


INPUTS 


SEGMENT 
OUTPUTS 
MM5760 
DIGIT 
OUTPUTS 


DECIMAL 
POINT 

READY 


PROGRAM^ 


\run 


DECIMA 

n 


POINT SEGMENT INPUTS 

o a n n n 
u.u.u.u.o. 

DIGIT 


NSA298 

o o n 












MOOE 
SWITCH 










m 












!'■• r 
































1 

4— 


(9) 










r 
i 

L 




9> 


OUTPUt V cc 

INPUT OM8861 
GND 


9V _"^ 


7 


i 


OAT 


4 




!8I 














4 X9 


(4) 


K I/O'! 


MM 57 65 


READY 
RUN LOAD 

ALARM 








1- 






DATA 
KEYBOARD 


CONTROL 






LEO 
' ALARM 
~ INDICATOR 




DIGIT 
DRIVER 


1 X 4 

PROGRAMMER 

CONTROL 

KEYBOARD 






1 


LEA 
PRO 


RN MODE 
GRAMMER 








— — 






SWITCH 





FIGURE 3. Low Cost Hand Held Programmable Electronic Slide Rule Using the MM5760 Calculator and MM5765 Programmer 



KEY SEQUENCE EXAMPLES 
KEY 



1 




LOG 
EN 

10 

C 

C 
10 
EN 

2 

Y* 
50 

+ 

4 

Vx 

EN 
7 

2 
X 

9 
STO 

3 
ARC 
SIN 

1 

LN 
RCL 
1/X 

9 



ARC 
ARC 
SIN 
SIN 



o 



DISPLAY 



COMMENTS 



Power-On Clear 



Copy X into Y 



0. 

1 

1 

1 00 

2. 

2. 

1 

2. 

0. 

1 

1 0. 

2 

9 9.9 9 99 3 

50 

1 4 9.9 9 9 93 

4 

2. 

2. 

7 
-5. 

2 
-1 0. 
-1 4.9 999 9 3 

9 

9. 

3 

3 
.0.0.0.0.0.0.0.0 Error indication (X > 1 ) 

No clear needed 
.1 
-2.3 2 5 8 5 Typical calculation time = 260 ms 



Clear X, stack pushes down 
Stack cleared 



6 digit accuracy. Typical calculation time =1.7 seconds 



Typical calculation time = 90 ms 



"STO" terminates data ent 



ry 



.11111111 

9 
.11111111 

1.276517 1 9 V9~ = 9 1/9 



Exchange X and Y 



• 8 Second "ARC" ignored 

5 3.1 30 1 SIN -1 in degrees 

■8 SIN of 53.1301° 

829 



o 

CO 
IT) 



KEY SEQUENCE EXAMPLES (Con't) 


KEY 


DISPLAY 


ARC 


.8 


COS 


3 6.8 699 


COS 


.8 


ARC 


.8 


TAN 


3 8.6 598 1 


TAN 


.8 


LOG 


-.09691 


LN 


.0.0.0.0.0.0.0.0 


TT 


3.1 4 1 59 2 6 


C 


1. 


C 


1.27 65 1 7 


c 


0. 


LN 


.0.0.0.0.0.0.0.0 


cs 


-1 


STO 


-1. 


ARC 


-1. 


COS 


1 80 



COMMENTS 



COS in degrees 
COS of 36.8699 

TAN"" 1 in degrees 
TAN of 38.65981 



e* for X = 



ARC 
TAN 
RCL 

e* 
RCL 
ARC 
SIN 
ARC 

ARC 

+ 
RCL 



1 80 

8 9.6 8 1 6 9 
-1. 

.3678796 
-1. 
-1. 
-9 0. 
-9 0. 

-1.570 7963 
-1.5707963 
-1.5707963 
-2.5707963 



EXAMPLE DEMONSTRATING STACK OPERATIONS 



90 in radians 

Accumulate X- in M 
Recall M 



14 + 26 



KEY 

14 
EN 
26 

+ 

6 
EN 

4 



LOG 
25 

EN 

5 

+ 
SIN 





Evaluate: 


6-V4 
SIN (25 + 5) 




STACK REGISTERS 




X 


Y 


Z 


14 


? 


? 


14. 


14 


? 


26 


14 


? 


40. 


? 





6 


40 


? 


6. 


6 


40 


4 


6 


40 


2. 


6 


40 


4. 


40 





10. 








1. 








25 


1 





25. 


25 


1 


5 


25 


1 


30. 


1 





.5 


1 





2. 








0. 









COMMENTS 



Y and Z are unknown 



14 + 26 = 40 



\/4 =2 

6 - V 4 = 4 

(14 + 26)/6-v^ = 10 

LOG[(14 + 26)/(6-v4")] = 1 



SIN (25 + 5) = 0.5 
LOG [(14-26)/(6-v'4))_ 
SIN(25 + 5) 



I-30 



KEYBOARD BOUNCE AND NOISE REJECTION 

The MM5760 is designed to interface with most low cost 
keyboards, which are often the least desirable from a 
false or multiple entry standpoint. 

A key closure is sensed by the calculator chip.when one 
of the key inputs, K1, K2, K3 or K4 is forced more 
positive than the Logical High Level specified in the Elec- 
trical Specifications. An internal counter is started as a 
result of the closure. The key operation begins after nine 
word times if the key input is still at a Logical High Level. 
As long as the key is held down (and the key input re- 
mains high) no further entry is allowed. When the key 
input changes to a Logical Low Level, the internal counter 
starts a sixteen word time-out for key release. During 
both entry and release time-outs the key inputs are 
sampled approximately every other word time for valid 
levels. If they are found invalid, the counter is reset and 
the calculator assumes the last valid key input state. 

One of the popular types of low-cost keyboards avail- 
able, the elastomeric conductor type, has a key pressure 
versus contact resistance characteristic that can generate 
continuous noise during "teasing" or low pressure key 
depressions. The MM5760 recognizes a series contact re- 
sistance up to 50 kf2 as a valid key closure, assuring a 
reliable interface for that type of keyboard. 

AUTOMATIC DISPLAY CUTOFF 



READY SIGNAL OPERATION 

The Ready signal indicates calculator status. When the 
calculator is in an "idle" state the output is at a Logical 
High Level (near V ss ). When a key is closed, the internal 
key entry timer is started. Ready remains high until the 
time-out is completed and the key entry is accepted as 
valid, then goes low as indicated in Figures 4 and 5. It 
remains at a Logical Low Level until the function initiated 
by the key is completed and the key is released. The low 
to high transition indicates the calculator has returned to 
an idle state and a new key can be entered. 

ERROR INDICATION 

In the event of an operating error, the MM5760 will 
display all zeros and all decimal points. In addition to 
normal calculator overflow situations which occur as a 
result of adding, subtracting, multiplying or dividing and 
including division by zero, the error indication is dis- 
played for the conditions of Table I. 

The Z-register is automatically cleared and the Y- and 
M-registers are saved. An error condition is cleared by 
depressing any key except "1/X," "+," "LOG X" or 
"LN X." Operation on the X register with an error 
displayed will be performed as if X contained a zero. 

KEY OPERATIONS 

(Note: Register X is always displayed.) 



2 

o 



If no key is depressed for approximately 35 seconds, an 
internal automatic display cutoff circuit will blank all 
segments and display nine decimal points. Any key de- 
pression will restore the display; to restore the display 
without modifying the status of the calculator, use two 
change sign, "CS," depressions. 



Clear Key, "C" 

After any key except "ARC," it clears X, pushes Y 
down to X, Z to Y and places a zero in Z. Subsequent 
depressions perform the same function; thus, three "C" 
depressions after a number entry will clear a completely 



"!_/ h 



J t 



V 



FIGURE 4. Ready Timing 



NEW 

KEY IS 

DEPRESSED 



ANY 
SWITCH 
INPUT 



9 WORDS 



KEY IS 
RELEASED 



jUULJLla 



16W0ROS AFTER 
KEY RELEASE OR 

AFTER CALCULATION _ 

IS COMPLETE, 

WHICHEVER iS 

LONGER. 



r 



NEW KEY HAS 
BEEN ACCEPTED 
BY CALCULATOR. 
THE KEY MAY 
BE RELEASED. 



NEXTKEY 

CAN BE 
ENTERED. 



FIGURE 5. Functional Description of Ready Signal and Key Entry 



8-31 



TABLE I. Conditions for Error Indication 



FUNCTION 


CONDITIONS (REGISTER X = X) 


+, -, x, ^ 


Result > 99999999. 


^or 1/X 


iX I < 0.00000001 


V* 


X <0 


Y x 


Y<0 

fen 99999999 < X tn Y < -28 


log X or In X 


X< 0.00000001 


e x 


fen 99999999 < X < -28 


Sin X or Cos X 


X > 7 radians or ^401° 


ARC Sin X or ARC Cos X 


X> 1 


Tan X 


X = ±90°, or X> 7 radians 



Note: tn 99999999 = 18.420680 



full stack. This is also the method used to gain access to 
the Z register. Memory register M is not affected by "C." 
Pressing "C" after "ARC" resets the ARC function with- 
out affecting any of the data registers. 

Number Entries 

First entry after "EN" clears X and enters the number 
into Digit 8 (the second digit from the left of the display) 
of X. Second through eighth entry (excluding a decimal 
point) enters the number one digit to the right of the 
last number entered. The ninth, and subsequent entries, 
are ignored. The first number key after any key other 
than "EN" loses Z, pushes Y up to Z, X to Y, clears X 
and enters the number in Digit 8 of X. 

Decimal Point, "." 

After an ENTER key, it clears X and displays a decimal 
point in the left-most digit position. Following a number 
entry, it places a decimal point to the right of the last 
number entered. Subsequent depressions without an 
interceding number entry are ignored; subsequent de- 
pressions after interceding number entries will replace 
the previous point with one to the right of the last 
entered number. 

Change Sign Key, "CS" 

Changes the sign of X. 

Enter Key, "EN" 

Register Z is lost; Y is pushed up to Z and X is copied 
into Y. 

Addition Key, "+" 

X is added to Y and the result is placed in X. Z is 
transferred to Y and cleared. Following an "ARC" key, 
"+" adds the contents of X to M without changing X, 
Y or Z. 



Subtraction Key, "-" 

X is subtracted from Y and the result is placed in X. 
Z is copied into Y, then cleared. Following an "ARC" 
key, "— " subtracts the contents of X from M without 
changing X, Y or Z. 

Multiplication Key, "X" 

X is multiplied by Y and the result is placed in X. Z is 
transferred to Y and cleared. Following an "ARC" key, 
"X" converts the value of X from radians to degrees 
without changing M, Y or Z. 

Division Key, "^" 

X is divided into Y and the result is placed in X. Z is 
transferred to Y and cleared. Following an "ARC" key, 
"+" converts the value of X from degrees to radians 
without changing M, Y or Z. 

Pi Key, "77" 

Register Z is lost; Y is pushed up to Z and X to Y. The 
constant 3.1415926 is placed in X. 

Exchange Key, "*—*" 

Registers X and Y are exchanged. Z and M are not 
affected. 

Inverse Trigonometric and Multifunction Key, "ARC" 

When used as a prefix to one of the trigonometric keys 
it conditions the calculator to determine the inverse 
function of the value in X. For example "ARC" followed 
by "SIN" computes the angle that has a sine equal to the 
value of X, replacing X with that angle in degrees. See 
key descriptions of "+," "-," "X," "V "vX," "STO" 
and "C" for secondary functions assigned to those keys 
by preceding them with "ARC." "ARC" followed by 
any key other than one of the above or one of the trig 
functions will be ignored. 



8-32 



Reciprocal Key, "1/X" 

A non-zero value of X is replaced by its reciprocal. 
Registers M, Y and Z are not altered. 

Square Root Key, "\/X" 

A positive value of X is replaced by its square root. 
Registers Y and Z are not altered. Following an "ARC" 
key, "\/x" replaces the value of X with its square. 
Registers M, Y and Z are not affected. 

Logarithmic Keys, "LN" and "LOG" 

These keys replace the value of X by its natural or 
common logarithm, respectively; register Z is lost. M is 
not altered. 

Exponential Key, "e x " 

Determines the value of 2.7182818 raised to the power 
contained in register X, and places that value in X. The 
contents of Z are lost and Z is cleared. M is not altered. 

Power Key, "Y x " 

Determines the value of Y raised to the power of X and 



replaces X with the result. The contents of Z are lost, Y 
retains the exponent and Z is cleared. M is not affected. 

Memory Keys, "STO" and "RCL" 

The memory store key, "STO" copies the value of X 
(including sign) into storage register M without altering 
the stack. "STO" following "ARC" squares the value 
of X and accumulates the result into M. Registers X, Y 
and Z are not affected. The recall key, "RCL," transfers 
Y to Z and X to Y, then copies M into X. Storage 
register M is not changed and Z is lost. Both "STO" 
and "RCL" terminate the entry mode. 



MEMORY OPERATIONS RESULTING IN 
ERROR CONDITIONS 



Any operation in which the storage register M is involved 
that results in an error condition, will not affect the 
previous contents of M. For example, if by accumulating 
X into M("ARC," "+") the contents of M will become 
greater than 99999999., an error indication will occur 
and the original contents of M are protected. As a result 
of the overflow, registers X and Z will be lost an shown 
in Table II. 



TABLE II. Summary of Stack Operations 



SINGLE FUNCTION OPERATIONS 



. — LOST 


/ 




/ 



lxi, m. m.- m. □ 



AFTER [EN J 
OR OTHER 
NUMBER. 
AFTER ANY 
FUNCTION KEY 



CD 



m, CD, CD, □ 



~\_ 




Q 



j SIN [ [COS J JTAnJ { LN | [log] [ <■* | 



CD 



JC 



H, CD 




, 






, 



H™] 



[rcl] 




— LOST 




/ 


L 




I 




/ '.'. 



cd 




— LOST 




/ 




: / 




/ 


" 



8-33 



o 
to 

2 



TABLE It. Summary of Stack Operations (Cont'd) 



SECOND FUNCTION SEQUENCES 

| ARC | FOLLOWED 6V [ + j | - | 



I arc) FOLLOWED BV ] x | | j | 



-A »-M 



| ARC | FOLLOWED BV | v x | 



IANST0 DEGREES 1 - " ^" LOST 

OR \ 

DEGREES TO RADIANS ) 



n/- 



[arc 1 


FOLLOWED BV 


[STO j 






v 





JARCJ 


FOLLOWED BV 


m 








m 



| ARCJ FOLLOWED 6V |"siM j | COS [ OR pTA^ 



ERROR INDICATION 



RANGE AND ACCURACY OF FUNCTIONS 

The smallest magnitude that can be displayed is 
+0.00000001 and the total range is from -99999999 to 
+99999999. The arithmetic functions (+, -, x, +, 1/X, 



VX, X 2 ) have eight digit accuracy. All results are 
truncated. Table III summarizes range and accuracy of 
the other functions. Arithmetic calculations will be 
completed in less than 0.5 second; all others except 
Y* in less than 2.5 seconds and Y* in less than 5 seconds. 



TABLE III. Digit Accuracy for Various Functions 



FUNCTION 


RANGE 


APPROXIMATE 
ACCURACY (Note 1) 


SIN, COS, TAN 


"o -90° to -v 90° 


7 Digits 




-v -360° to 'v 360° 


6 Digits 


ARC SIN and ARC COS 


-v-1 to ^ +1 


6 Digits 


ARC TAN 


-99999999 to 99999999 


6 Digits 


LOG 


X>0 


6 Digits 


e x 


-28 < X < Ir, 99999999 


6 Digits 


LN 


X>0 


6 Digits 


Vx 


X>0 


8 Digits 


Y* 


Y>0 

X Bn Y < 6n 99999999 


5 Digits 



Note 1: Six digit accuracy, as an example, would be: 
1 2 3 4 5 6 X X 



th 



u 



n digit accuracy has the n digit from the MSD being displayed accurate within ±1. 



1-34 



a 



Calculators 



MM5762 financial calculator 
general description 

The single-chip MM5762 Business and Financial Calcu- 
lator was developed using a metal-gate, P-channel 
enhancement and depletion mode MOS/LSI technology 
with low end-product cost as a primary objective. A 
complete calculator as shown in Figure 1 requires only 
the MM5762,a keyboard, DS8864 digit driver, NSA1298 
LED display, 9V battery and appropriate hardware. 

Keyboard decoding and key debounce circuitry, all 
clock and timing generation and 7-segment output 
display encoding are included on-chip and require no 
external components. Segments can usually be driven 
directly from the MM5762, as it typically sources 
about 8.5 mA of peak current. [Note: The typical 
duty cycle of each digit is 0.104; average LED segment 
current is therefore approximately 0.104 (8.5 mA), or 
0.9 mA average. Correspondingly, the worse-case average 
segment current is 0.104 (5.0 mA), or 0.52 mA.] The 
ninth digit (left-most) is used for the negative sign, or 
the decimal point of a number less than unity. 

An internal power-on clear circuit is included that clears 
all registers, including the memory, when V DD and 
V ss are initially applied to the chip. 

Trailing zero suppression allows convenient reading of 
the left justified display, and conserves power. The 
DS8864 digit driver is capable of sensing a low battery 
voltage and providing a signal during Digit 9 time that 
can be used to turn on one of the segments as an 
indicator. Typical current drain of a complete calculator 
displaying five "5's" is 30 mA. Automatic display 
cutoff is included. If no key closure occurs for approxi- 
mately 35 seconds, all numbers are blanked and all 
decimal points are displayed. 

The Ready output signal is used to indicate calculator 
status. It is useful in providing synchronization informa- 
tion for testing or applications where the MM5762 is 
used with other logic or integrated circuits; e.g., with 
the MM5765 Programmer (Figure 31. 

Thirty-two keys are arranged in a four-by-nine matrix 
as shown in Figure 1. There are the standard four function 
keys (+, — , ^, x). Change Sign, Exchange, three accumu- 
lating memory control keys plus ten unique business or 
financially oriented computation keys: three keys for 
entering interest rate per period, number of periods and 
amount, three keys for computing present and future 
values, sinking funds, saving and loan payments and 
other time/money factors, two keys for computing 
per cent and delta per cent, a sum-of-digits key and a 
power key. There is an automatic constant feature. 

The user has access to six registers designated X, Y, A, I, 
N and M. The X-register is used for keyboard entry and 
display. The Y and A-registers are used in multiply/ 
divide and add/subtract calculations, respectively. Interest 
values are held in the l-register and the N-register stores 






the number of time periods in financial calculations. 
M is an accumulating storage memory and is completely 
independent of the others. 

Data is entered into the calculator in floating point 
business notation. All entries and results are displayed 
left justified with insignificant zeros to the right of the 
decimal point suppressed. All intermediate results of a 
chain calculation are floating point. Terminating keys 
(such as equal, per cent, etc.) round the displayed result 
to two decimal positions. 

features 

■ Complete business and financial capability 

• Arithmetic functions: +,-, x, -^ 

• Power function: Y* 

• Percent: both live percent and delta percent keys 

• Sum-of-digits capability for computing deprecia- 
tion or "Rule of 78's" loan costs 

• Financial functions: 

* "n" key, enters number of periods 

* "i" key, enters interest rate per period 
A "AMT" key, enters given amount 

A "VAL" key, computes PV or FV 
A "SAV" key, computes deposit or sinking fund 
amounts 

* "LOAN" key, computes payment or loan 
amounts 

■ Accumulating memory 

■ Automatic constant 

■ Convenient business (adding machine) entry notation 

■ Eight full digits 

■ Power-on clear 

■ Automatic display cutoff 

■ Low system cost 

connection diagram (dip Top view) 



DIGIT3 




24 
DIGIT 4 


DIGIT? 




23 
DIGIT 5 


DIGIT 1 




DIGITS 




1 
K 4 




— DIGIT? 


IVITCH 


K3-L 




20 
DIGIT 6 


YPUTS 


K2-1 




— DIGIT 9 




. K 1 




IB 
REA0Y 


8 




17 
SEGMENT D 


9 
SEGMENT G — 




— SEGMENT E 


SEGMENT fi- 




— SEGMENT A 


ll 
SEGMENT F 




— DECIMAL POINT 




v„-!i 




— SEGMENT C 



Order Number MM5762N 
See Package 22 



1-35 



absolute maximum ratings 










Voltage at Any Pin Relative to V ss . V ss + 0.3V to V ss - 12V 










(All other pins connected to V ss .) 










Ambient Operating Temperature 0°C to +70°C 










Ambient Storage Temperature -55°C to +150°C 










Lead Temperature (Soldering, 10 seconds) 300°C 










operating voltage range 










6.5V <V SS - V DD <9.5V 










V ss is always defined as the most positive supply voltage. 










dc electrical characteristics 










PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Operating Supply Current (l DD ) 


V DD = V ss -9.5V,T fl =25°C 




8.0 


16.0 


mA 


Keyboard Scan Input Levels 












(K1, K2, K3 and K4| 












Logical High Level 


V ss -6.5V < V DD < V SS -9.5V 


V SS "2-5 






V 


Logical Low Level 


Vdd = V SS -6.5V 






V ss -5.0 


V 




V DD = V SS -9.5V 






Vss-6.0 


V 


Digit Output Levels 












Logical High Level (V OH ) 


Rload = 3.2kJ2toV DD 












V SS -6.5V < V OD < V SS -9.5V 


V SS -15 






V 


Logical Low Level (V Q l) 


Vdd = V SS -6.5V 






V ss -60 


V 




Vdd = V SS -9.5V 






Vss- ? 


V 


Segment Output Current 


T A = 25°C 










(Sa through Sg and Decimal Point) 


Vout = V SS -3.6V, V DD = V SS -6.5V 


-5.0 


-8.5 




mA 




Vout = V SS -5V, V DD = V SS -8V 




-10.0 




mA 




Vout = V SS -6.5V, V OD = V SS -9.5V 






-15.0 


mA 


Ready Output Levels 












Logical High Level (V OH ) 


lour =-0 4 mA 


Vss-10 






V 


Logical Low Level (V OL ) 


lout = 10mA 






Vdd + 1-0 


V 


ac electrical characteristics 










PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Word Time {Figure 2) 




0.32 


0.75 


2.0 


ms 


Digit Time {Figure 2) 




36 


83 


220 


us 


Segment Blanking Time [Figure 2) 




2 


4.5 


14 


Ms 


Digit Output Transition Times 


Cload = 100 pF, R L oad = 9-6 kS2 




2 




Ms 


(Irise and t FALL ) 












Keyboard Inputs High to Low 


C LO ad = 100 pF 




4 




Ms 


Transition Time After 












Key Release 












Ready Output Propagation Time 












(Figure 4) 












Low to High Level (t PDH ) 


Cload = 100 pF 


10 




50 


Ms 


High to Low Level (t PDL ) 


Cload = 100 pF 






1 


ms 


Key Input Time-out (Figure 51 












Key Entry 




2.8 


7.0 


18 


ms 


Key Release 




5.1 


12 


32 


ms 


Display Cutoff Time 




15 


35 


92 


sec 


(The time after the last valid key 












closure that all numbers will be 












blanked and all decimal points 












displayed.) 













3-36 



MR* 



AMT 



K1 Sa Sb Sc Sd Se Sf Sg OP 

K3 MM5762 

K4 0) D2 D3 D4 D5 D6 07 DB 09 



DP Sg Sf Se Sd St Sb Sa NSA129B 

O O O O O O O O CI 
/_/. /_/. U. /_/. /_/. /_/. /_/. /_/. /_/. 

09 08 07 06 D5 D4 D3 D2 D1 






FIGURE 1 . Complete Calculator Schematic 



OUTPUTS 
0, 


h- — 






WORD TIME 


























-1 


— — DIGIT "T 


1ME 












DZ ! 








1 


















03 | 




1 






















D9 




1 






















Pfiiwr 


1 1 




SEGMENTS 
















Sa 


1 

h— SEGM 


1 1 1 


J 


J 


II 1 


1 








— 


ENT BLANKING TIME 








Sb 




"J 


1 II 1 


1 


II 1 


1 


1 


1 


Sc 








! 
















1 u u 

1 


U 


U 


II 1 


1 




1 








! 1 






Sd 


1 


1 1 1 


1 


1 1 


1 


1 


















Se 


J 


1 


1 1 


1 
















: 






Sf 1 


1 II 


J 


1 1 








i 












Sg 


J J u u 


J 


1 1 




I 


1 


ACTUAL OIS 


PLAY: 


L 


1/ ~\ r 
.1 //_ 


' r i i ~i ~i i 
i _/ / _/./_ / 




SEGMENT 
DESIGNATION 


•u 


b 

c 





FIGURE 2. Display Timing Diagram 



8-37 













1 


i 






■ I i 




























(7) 


LED 
DISPLAY 






FINANCIAL 
CALCULATOR 












i 








14) 


K 

INPUTS 


SEGMENT 
OUTPUTS 
MM5762 
DIGIT 
OUTPUTS 


DECIMAL 
POINT 
Vdd 

READY 


PROGRAM*- 


\RUN 


DECIMAL POINT SEGMENTS 

/-/ /-/ n o o o 

DIGIT 


MSA1298 

/-/ o o 

/_/. /_/. /_/. 












SWITCH \ 














(9) 










f 








r - 


I 












r , 








+ 


1 


(9) 


(9) 


OUTPUT V cc 
IMPUT DS8864 
GND 


9V 


~ZT 


i 


~- 


_i 


DAT 


A 


' 




' ' 










'- 


/ 

4X9 
DATA 
KEYBOARD 
AND 
1 X4 




14) 


Vss 
K l/D's 

K5 


MM5765 


READY 
RUN/LOAD 

ALARM 








, 








CONTROL 






LED 


DRIVER 
POWER 








| , 




PROGRAMMER 
CONTROL 
KEYBOARD 


le; 

PRC 


RNM 
GRAA 


ODE 

flMER 




-.. 1 


f ALARM 
r- INDICATOR 


^ 


SWITCH 





FIGURE 3. Low Cost Hand Held Programmable Financial Computer using the MM5762 Calculator and MM5765 Programmer 



KEYBOARD BOUNCE AND NOISE REJECTION 

The MM5762 is designed to interface with most low 
cost keyboards, which are often the least desirable from 
a false or multiple entry standpoint. 

A key closure is sensed by the calculator chip when 
one of the key inputs, K1, K2, K3 or K4 are forced 
more positive than the Logical High Level specified in 
the electrical specifications. An internal counter is 
started as a result of the closure. The key operation 
begins after nine word times if the key input is still at a 
Logical High Level. As long as the key is held down 
(and the key input remains high) no further entry is 
allowed. When the key input changes to a Logical Low 
Level, the internal counter starts a sixteen word time-out 
for key release. During both entry and release time-outs 
the key inputs are sampled approximately every other 
word time for valid levels. If they are found invalid, the 
counter is reset and the calculator assumes the last valid 
key input state. 

One of the popular types of low-cost keyboards available, 
the elastomeric conductor type, has a key pressure 
versus contact resistance characteristics that can generate 
continuous noise during "teasing" or low pressure key 
depressions. The MM5762 defines a series contact 
resistance up to 50 kil as a valid key closure, assuring 
a reliable interface for that type of keyboard. 



AUTOMATIC DISPLAY CUTOFF 

If no key is depressed for approximately thirty-five 
seconds, an internal automatic display cutoff circuit 
will blank all segments and display nine decimal points. 
Any key depression will restore the display; to restore the 
display without modifying the status of the calculator, 
use two Change Sign key depressions. 

READY SIGNAL OPERATION 

The Ready signal indicates calculator status. When the 
calculator is in an "idle" state the output is at a Logical 
High Level (near V ss ). When a key is closed, the internal 
key entry timer is started. Ready remains high until the 
time-out is completed and the key entry is accepted as 
valid, then goes low as indicated in Figures 4 and 5. It 
remains at a Logical Low Level until the function initiated 
by the key is completed and the key is released. The low 
to high transition indicates the calculator has returned 
to an idle state and a new key can be entered. 

ERROR INDICATION 

In the event of an operating error, the MM5762 will 
display all zeros and all decimal points. The error indica- 
tion occurs if division by zero is attempted or either 
a result or intermediate value exceeds 99999999. 



838 



t 



7 t 



\ 



2 

IS) 



-I .»» h- 



FIGURE 4. Ready Timing 



NEW 

KEY IS 

DEPRESSED 



ANY 

SWITCH 

INPUT 



jUUULJLJU 



\ 



16W0RDS AFTER 

KEY RELEASE OR 

AFTER CALCULATION 

IS COMPLETE, 

WHICHEVER IS 

LONGER 



r 



NEW KEY HAS 
BEEN ACCEPTED 
BY CALCULATOR. 
THE KEY MAY 
BE RELEASED. 



NEXT KEY 

CAN BE 
ENTERED 



FIGURE 5. Functional Description of Ready Signal and Key Entry 



The indication is cleared by depressing any key. 

If an error results from a "+" or "— " key, the X-register 
is cleared and the last entry is saved in the A-register; 
all other registers are not effected. An error condition 
during "x" or "V operations clears X without changing 
any of the other registers. 

Overflow as a result of the "Y x ," "VAL," "SAV" or 
"LOAN" keys clears the X-register and destroys the 
values in N, I and A. Y is not changed. 

An attempt to raise a negative number to a power will 
cause the error indication to appear, the X-register will 
be cleared and the exponent will be stored in Y. The 
other registers are not changed. 

Overflow as a result of "M+" destroys the value stored 
in M, clears X and displays the error indication. Calcu- 
lations are immediately stopped and other registers are 
not cleared. 

AUTOMATIC CONSTANT 

The MM5762 retains as a constant the first factor of 
a multiplication calculation or the second factor of a 
division calculation, when that calculation is terminated 
by an "=" key, "%" key or "= +" key. Subsequent 
calculations using the stored constant are made by 
entering a number and operating upon it with the 



appropriate terminator ("=," "%" or "= +" key). The 
Y-register is used to store the constant in the constant 
mode of operation. 

The calculator automatically changes to the chain mode 
when an "x" or "V key occurs in the calculation. In the 
chain mode, the result of each "x" or "-r" key is stored 
in both X and Y-registers. A new entry replaces X with- 
out altering Y. At the completion of a chain calculation, 
the Y-register will contain the value used as first factor 
of the last multiply, or the latest entry if the last 
operation was a divide. 

Table I summarizes the four modes. 

KEY OPERATIONS 

(Note: Register X is always displayed.) 

Clear Key, "C" 

Following a number entry or a "MR" key, it clears the 
X-register only (clear entry). Following any other key 
it clears registers X, Y and A. 

Number Entries 

The first entry clears the X-register and enters the 
number into the LSD of X. Second through eighth 
entries (excluding a decimal point) are entered one 



339 



digit to the right of the last number. The ninth, and 
subsequent entries are ignored. First entry after a "+," 
"-," or "M+" following a "+" or "-" key causes the 
number in the X-register to be transferred to the 
A-register before clearing and placing the new entry 
in X. 



Decimal Point, "." 

As the first depression of a number entry, it clears the 
X-register and places a point in the leftmost digit. If 
the previous key was a number, it enters a decimal 
point to the right of the last number entered. Following 
a "+," "-," or those keys preceding a "M+" key, the 
X-register is transferred to A, cleared and a decimal 
point entered in the leftmost digit. The last decimal 
point depression in a single number entry is accepted 
as the valid point. 



Change Sign Key, "CS" 

Changes sign of register X. 

Addition Key, "+" 

If the previous key was not a "+" or "-" key, the number 
in the A-register is added to the X-register, X is trans- 
ferred to A, and the sum is stored in X. When the last 
key was a "+" or "— " key, the number in A is added to 
the number in X without destroying the value of A. 
The sum is stored in X. 



Subtraction Key, "— " 

If the previous key was not a "+" or "— " key, the 
number in the X-register is subtracted from the number 
in the A-register, X is transferred to A, and the difference 
is stored in X. When the last key was a "+" or "— " key, 
the number in A is subtracted from X without destroying 
the value of A. The result is stored in X. 

Multiplication Key, "x" 

If there has not been a "x" or "•:-" key since the last 
terminator key ("=," "= +" or "%"), the value of the 
X-register is copied into the Y-register and the calculator 
is set to the chain multiply mode. In a chain calculation 
in which there has been a "x" key since the last termina- 
tor or ,,J r" key, X is multiplied by Y and the resulting 
product is stored in both X and Y; if a "+" key has 
occured since the last terminator or "x" key, depression 
of "x" will divide the Y-register by the X-register, with 
the quotient stored in both X and Y. 

Division Key, "^" 

If there has not been an "x" or "+" key since the last 
terminator key ("=," "= +" or "%"), the value of the 
X-register is copied into the Y-register and the calculator 
is set to the chain divide mode. In a chain calculation 
if an "x" key has occured since the last terminator or 
"^" key, X is multiplied by Y and the product is stored 
in both X and Y; if a ,,J r" key has occured since the last 
terminator or "x" key, depression of "-r" will divide 
the Y-register by the X-register, w.th the quotient stored 
in both X and Y. 



TABLE 1. Mode Summary 



MODE 


KEYS THAT 
SET MODE 


DESCRIPTION 
{See Calculation Examples) 


CONSTANT 
MULTIPLY 


CLEAR 

= + 
% 

yx 

SOD 
VAL 
SAV 
LOAN 


Depression of an "--," "~- +" or "%" key will multiply 
the X-regisier by the Y-register and replace X with the 
product- Y remains unchanged. 


CHAIN 
MULTIPLY 


Following a terminator or "+-" 
or "x" operation 


Depression of an "-," "= t" or "%" key will multiply 
the X-register by the Y-register and place the product in 
X. Y remains unchanged. 


CONSTANT 
DIVIDE 


= + 


With calculator 
previously in chain 
divide mode. 


Depression of an "~," "" *" or "%" key will divide the 
X-register by the Y-register and replace X with the 
quotient. Y is unchanged. 


CHAIN 
DIVIDE 


Following a terminator or - 
or "x" operation 


Depression of an "=," "^ +" or "%" key will divide the 
Y-register by the X-register, transfer X to Y, and place 
the quotient in X. 



Equal Key, "=" 



Power Key, "Y x " 



In the chain multiply mode, the value in the X-register 
is multiplied by the Y-register with the product stored 
in X. Register Y remains unchanged. In the chain 
divide mode, depression of "=" will divide Y by X, 
transfer X to Y, and place the quotient in X. If the 
calculator is in constant multiply, "=" will multiply X 
by Y, place the product in X and retain Y. For constant 
divide, the X-register is divided by Y, the quotient is 
stored in X; Y is unchanged. 



The "=" key always rounds the answer stored in X to 
two places to the right of the decimal point, and clears 
register A. 



When the calculator is in either the chain or constant 
multiply modes, depression of "Y*" raises the number 
in the Y-register to the power of the X-register and 
replaces X with the result. (Thus, to raise two to the 
fifth power, use the sequence: "2," "x," "5," "Y x .") 
If the calculator is in the constant or chain divide modes, 
the value of Y is raised to the inverse of X power; i.e., 
the key sequence "5," "V "2," "Y* ," results in the 
calculation of 5 raised to the 1/2 power. The original 
value of X is retained in Y and register A is cleared. 
The calculator is set to the constant multiply mode. 
Results computed with the "Y*" key are rounded to 
five places. 



Exchange Key, 



Percent Key, "%" 

This key acts exactly like the "=" key except the value 
of X is divided by 100 and copied into register A 
before performing the required operation. Register A is 
not cleared. The result stored in the X-register is 
rounded to two decimal positions. 



Automatic Accumulation Key, "= +" 

It acts just like the "=" key in all modes. After the 
result is stored in X, the value of X is added to the 
number in the M-register. The result stored in X and 
accumulated into M is rounded to two decimal places. 
Register A is cleared. 



Memory Plus Key, "M+" 



The X and Y-registers are exchanged. No other registers 
are effected. 



Interest Entry Key, "i" 

If the sign of the number in the X-register is positive, 
"i" divides the number by 100 and stores the quotient 
in X and the l-register. If the value of X is initially 
negative, "i" changes the sign, divides by 1200 and 
stores the quotient in both X and I; i.e., the interest 
will be compounded monthly. 



Number of Periods Entry Key, "n" 

If the sign of the number in the X-register is positive, 
X is copied into register N. A negative value of X is 
changed to a positive number, multiplied by 12 and the 
product stored in N and X. 



The number in the X-register is accumulated into the 
M-register. Registers X and A are not changed, so the 
repeat addition or subtraction conditions that existed 
before accumulation to memory are still valid. 



Amount Entry Key, "AMT" 

The value of the X-register is copied into the Y-register. 
No other registers are effected. 



Memory Recall/Memory Clear Key, "MR" 

Following any key except "MR," the value of the M- 
register is copied into the X-register. If the preceding 
key was "+," "-" or "M+" following "+" or "-," the 
number in the X-register is transferred to the A-register 
before M is recalled. Following another "MR" key, the 
M-register is transferred to X, then cleared. 



Delta Percent Key, "A" 

The value of X is subtracted from the Y-register, the 
difference is divided by the value of X and placed in X. 
The new value of X is multiplied by 100 and rounded to 
two digit places. Y retains the difference between the 
original values of X and Y; register A is unchanged. 
Calculator mode is set to constant multiply. 



Value Key, "VAL" 

If the number in the X-register is positive, the "VAL" 
key will compute future value: the sum of money 
available at the end of n periods from the present date 
(N-register) that is equivalent to the present amount 
(Y-register) with interest i (l-register). When the sign of 
the number in X is negative, the "VAL" key will compute 
present value: the sum of money necessary today to 
accumulate the future amount contained in Y over the 
n periods of N at the interest rate per interest period that 
is stored in I. Thus, to compute future value, simply 
enter i, n and amount in any order and press "VAL." 
For present value, precede "VAL" with "CS," setting 
a negative sign in X. Registers Y, N and I are not altered; 
X is replaced by the computed value and register A is 
cleared. The calculator is set to the constant multiply 
mode. The result is rounded to two decimal places. 



8-41 



Savings Deposit Key, "SAV" 

If the number in the X-register is negative, the "SAV" 
key will compute the amount to be deposited at the 
end of each period in a sinking fund for the number of 
periods, n, contained in register N, at an interest rate, i, 
contained in register I, compounded each time period, 
to accumulate the desired amount, contained in register 
Y. When the sign of the number in X is positive, the 
"SAV" key will compute the amount in a sinking fund 
if the number in Y is deposited at the end of n time 
periods (N-register) at an interest rate per time period i 
(l-register), compounded each time period. Thus, to 
compute the required sinking fund deposit to accumulate 
a desired amount over a given period of time, enter i, n 
and the amount in any order using the "i," "n" and 
"AMT" keys, then "CS" and "SAV," To find the 
amount in the sinking fund, simply enter i, n and the 
periodic amount of deposit and press "SAV." Registers 
N, I or Y are not altered by the calculation, register A 
is cleared and register X contains the computed value. 
The calculator is set to the constant multiply mode. 
Results are rounded to two decimal places. 



depreciation and depreciable value amounts using the 
original value of N and present values stored in N and A. 
N is decremented by one after each computation. The 
number to be depreciated (or the loan amount in a 
"Rule of 78's" interest calculation) is always entered 
with a "+" or "~" key and the number of periods with 
the "n" key, without regard to key order. If the key 
preceding "SOD" is not " V or "— ," the sum-of-digits 
computation is performed on the number in the A-register 
without the number in X first being transferred to A. 
The result will be rounded to two decimal places; cal- 
culator mode is set to constant multiply. 



EXAMPLES 



1. Addition or subtraction 



2.0 

3.2 

-12.3 



Loan Installment Key, "LOAN" 

If the number in the X-register is negative, the "LOAN" 
key will compute the end-of-period payment or receipt 
required over the number of time periods contained in 
the N-register at an interest rate per time period equal 
to the value in the l-register to support a loan equal to 
the amount stored in the Y-register. When the sign of 
the X-register is positive, "LOAN" computes the amount 
that can be loaned for a given end-of-period payment 
stored in Y over the number of time periods contained in 
N at the interest rate per time period of I, compounded 
each time period. Thus, to compute the required install- 
ment on a given loan, enter the amount of the loan 
using the "AMT" key, the interest rate using "i" and 
the number of periods with "n," press "CS" to enter a 
negative sign in register X, then "LOAN." To compute 
how much can be borrowed given a fixed payment, 
enter the payment amount, number of periods and 
interest rate, then "LOAN." "AMT," "\" or "n" can 
always be entered in any order. Registers N, I or Y are 
not altered by the calculation; register A is cleared and 
register X will contain the computed value. The calculator 
is set to the constant multiply mode. The result is 
rounded to two decimal places. 



Sum-of-Digits Key, "SOD" 

Following a "+" or "— " key, it transfers the number in 
register X to register A and computes a first sum-of-digits 
depreciation on that number by multiplying it by the 
ratio of the number in the N-register to the sum-of-digits 
of N. The result is rounded to two decimal places and 
stored in X; the difference between the initial and final 
values of X, the depreciable value, is stored in registers Y 
and A. N is decremented by one. (Therefore, to find 
depreciable value, simply use the "■<—>" key.) Subsequent 
depressions of the "SOD" key will compute successive 



KEYS 


DISPLAY 


2 


2 


4 


2. 


3 


3 




3. 


2 


3.2 


* 


5.2 


2 


1 2 




1 2. 


3 


1 2.3 



COMMENTS 



Note adding machine notation 



2. Repeat add or subtract 



KEYS 


DISPLAY 


3 


3 




3. 


1 


3.1 


+ 


3.1 


+ 


6.2 


+ 


9.3 




6.2 



COMMENTS 



3. Chain multiplication or division 



COMMENTS 



4. 
4.2 
2 604 



8-42 



EXAMPLES (continued) 




3. (continued 






KEYS 


DISPLAY 


COMMENTS 


b) 1 


1 







1 




4- 


1 0. 




2 


2 




+ 


5. 







1 




^ 


.5 




2 


2 




= 


.2 5 




c) 2 


2 







20 




x 


2 0. 




4 


4 
8 0. 




8 


8 




- 


1 0. 




7 


7 




X 


1,4 285 7 1 4 




4 


4 




= 


5.7 1 


"=" rounds to two 
decimal places 



4. Constant multiplication or division. 



KEYS 


DISPLAY 


3 


3 


x 


3. 


2 


2 


= 


6. 


4 


4 


= 


1 2. 


5 


5 




5. 


2 


5.2 


= 


1 5.6 


= 


4 6.8 


5 


5 


^ 


5. 


2 


2 


= 


2.5 


4 


4 


= 


2. 


5 


5 




5. 


2 


5.2 


= 


2.6 


= 


1.3 



COMMENTS 



First factor m constant multiply 



15.6 is re-entered and 
multiplied by constant 



Second factor in constant divide 



2.6 is re-entered and 
divided by constant 



5. To perform products of sums. 
(5 + 4) x (3 + 2)/(6 + 7) ■---? 



KEYS 

5 
4 



DISPLAY 



9. 

9. 

3 

3. 

2 

5. 

4 5. 

6 

6. 

7 

1 3. 

3.4 6 



Chain multiply mode 



(5 + 4) x (3 + 2) is executed 



45 - (6 + 7) is executed 



6. Calculate percentage. 

KEYS DISPLAY 



COMMENTS 



3 

300 
300. 

2 3 00 2 

5 3 0.25 

x 3 0.25 

5 5 

1 5.0 1 "Liu 

7. Perform add on and discount 

KEYS DISPLAY 

al Add-On. S125 plus 5% 

1 1 



COMMENTS 



2 


1 2 




5 


1 2 5. 




X 


1 2 5. 




5 


5 




s 


6.2 5 


5% of 125 is displayed 


* 


13 12 5 


125 * 5% Is displayed 


b) Discount 


S532.10 by 6% 




5 


5 




3 


5 3 




2 
1 


5 32 
5 3 2 
5 3 2.1 




X 


5 3 2.1 




6 


6 






3 19 3 


6% of 532.1 is displayed 


- 


500.1 7 


532.1 -6% is displayed 



8. Perform change sign. 

KEYS DISPLAY 



COMMENTS 



2 


1 2 


CS 


1 2 


3 


-1 2 3 




12 3. 


CS 


1 2 3 


5 


1 2 3.5 


CS 


1 2 3.5 


6 


-1 2 3.5 



( Change sign does not 
\ terminate entry. 



9. Perform exchange registers (X 



KEYS 

5 



Y). 

COMMENTS 



5. 
2 0. 



5 is initially constant multiplier 
4 is now constant multiplier 



I are 



nerator and denominator 
exchanged 



10. Accumulate in memory, recall and clear memory 



5 
t.'.H 
VR 
MR 



DISPLAY 


COMMENTS 


3 




3. 


Accumulate in memory 


4 




4. 


Accumulate in memory 


5 




7. 


Recall memory 


7. 


Recall and clear memory 


0. 


Recall and clear memory 



I-43 



EXAMPLES (continued) 




13 


Raising a 


number to a f 


actional power. 










KEYS 


DISPLAY 


COMMENTS 


10. (continu 


ed) 




a) 


5 1 ' 2 - 2.2361 






KEYS 


DISPLAY 


COMMENTS 




5 


5 
5 




b) 5 


5 






2 


2 




+ 


5. 






y* 


2.2 3 6 1 


Rounded to five digits 


6 


6 
1 1. 




b) 


6 ,/3 = 1.8171 






Mi 


1 1. 


Accumulate in memory 




6 


6 




7 


7 
1 8. 






3 


6. 
3 




Ml 


1 S, 

2 5. 


1 1 + 18 is accumulated in M 
Repeat add 




V 


1.8 1 7 1 


Rounded to five digits 


3 


3 












2 


3 2 




FINANCIAL 


EXAMPLES 






3 2. 












2 
CS 


3 2.2 
3 2.2 




1. 


Future Va 


ue Computations 


Ml 


3 2.2 


29-32.2 is accumulated in M 










9 


9 




To find the 


accumulated amount in a savings account 


+ 


3 4. 




at 


the end 


3f 9 years wh 


en a) $2500.00 is deposited 


MR 


-3.2 
3 0.8 


Accumulated value of M is recalled 


at 


5.25% interest compounded monthly, b) $3000. 


MR 


-3.2 


Accumulated value of M is recalled 





$3000 at 


5.00% interest 


. d) $3000 at 5.00% interest 


MR 


3.2 


M is cleared 


fo 


r 10 years 






MR 


0. 






KEYS 


DISPLAY 


COMMENTS 


11. Accumu 


ate in memory with the use of the "=+" key. 


al 


9 


9 


Number of years 










CS 


-9 
1 8. 


Compounded monthly 
Store 9x12 in N 


KEYS 


DISPLAY 


COMMENTS 




5.25 


5.2 5 


Interest 


5 


5 






CS 


-5.25 


Compounded monthly 




5. 






i 


.004375 


Store 5.25/1200 in 1 


3 


3 






2500 


2 500 


Original deposit 




1 5. 


5x3= 15 is added to M 




AMT 


2 500 


Store in Y 


4 


4 






VAL 


4 00 5.8 7 


Rounded to two decimal places 


2 


4. 

4.2 

4.2 




b) 


3000 


3000 








AMT 


3000. 


New deposit stored in Y 


3 


3 






VAL 


4 80 7.0 4 






1 2.6 


12.6 is added to M 


c) 


5 


5 




6 


6 






CS 


-5 






6. 






i 


.00416666 


New interest rate in 1 


7 


7 
.8 6 


f Rounded to 2 decimal places 
\ and added to memory 




VAL 


4 700.5 3 




9 


9 


/ Note method of multiplying 
\ negative number 


d) 


10 


1 




CS 


-9 




CS 


•T 




x 


9. 






n 


1 2 0. 


Enter 10 x 12 in N 


4 


4 






VAL 


494 1.0 2 




= + 


-3 6. 


-3 6. added to memory 










MR 


-7.5 4 


















2. 


Present Ve 


lue Computat 


ons 


12. Raising a 


number to a 


power. 


To 


find the amount to be 


deposited to accumulate a) 








$5000 in 7 years at 4.5% interest compounded monthly. 


KEYS 


DISPLAY 


COMMENTS 


b) $10,000. c 


$10,000 in 7.5 years. 


a) 2 5 = 32 








KEYS 


DISPLAY 


COMMENTS 


2 


2 
2. 




a) 


7 


7 


Number of years 


Y* 


5 






CS 


-7 


Compounded monthly 


3 2. 






n 


8 4. 


Enter 7 x 12 in N 










4.5 


4.5 


Interest 


b) 5 1 5 - 11.18 








CS 


4.5 

.0 03 7 5 


Compounded monthly 
Enter 4.5/1200 in I 


5 


5 






5000 


5000 


Future value 


1 


5. 
1 

1. 






AMT 
CS 
VAL 


50 0. 
5 0. 
36 5 1.1 


Enter amount in Y 
Present value required 


5 


1.5 












Y" 


1 1.1 8 


Rounded to five digits; trailing 


b) 


10000 


10000 








zero is suppressed 




AMT 
CS 


100 00. 
-1 000 0. 


New future value in Y 


c) 3 5 -0.00412 








VAL 


73 02.1 9 


Present value required 


3 


3 




c) 


7.5 


7.5 




x 


3. 






CS 


-7.5 




5 


5 






n 


9 0. 


New time period in IM 


CS 


5 






CS 


9 0. 




Y" 


.004 12 


Rounded to five digits 




VAL 


7 1 4 0.0 3 


Present value required 



S-44 



FINANCIAL EXAMPLES (continued) 

3. To find the amount that a) must be deposited 
monthly in a savings account at an interest rate of 
5.5% compounded monthly for 5 years to accumulate 
SI 5,000. b) compounded, and deposited quarterly. 



KEYS 


DISPLAY 


COMMENTS 


5.5 


5.5 


Interest 


CS 


-5.5 


Compound monthly 


i 


.0 0458333 


Enter 5.5 '1 200 


5 


5 


Number of years 


CS 


5 


Compound monthly 


n 


6 0. 


Ent 5 x 12 in N 


15000 


1 50 00. 


Future value 


AMT 


1 5000. 


Entered in Y 


CS 


-1 500 0. 




SAV 


2 1 7.7 7 


Monthly deposit required 


5.5 


5.5 


Interest 


- 


5.5 




4 


4 


Compound quarterly 


- 


1.3 7 5 


Use instead of -■ 

for maximum accuracy- 




.01375 


Enter 5.5/400 


C 




T errr:inate chain calcu'a 
tion 


5 


5 


Number of years 


4 


< } 


Compound quarterly 


= 


2 0. 




n 


2 0. 


Enter 5 x 4 in N 


15000 


15000 


Re-enter FV in Y 


AMT 


1 5000. 


Amount 


CS 


-1 5000. 




SAV 


6 5 6.7 1 


Quarterly deposit require 



4. To find the amount accumulated a) if S100 is 
deposited at the end of each month for 6 years in a 
savings account at an interest rate of 4.75%, com- 
pounded monthly, b) at 7.5%, c) at 4.75% for 9 years. 



4.75 

CS 

6 
cs 

n 
100 
AMT 
SAV 

7.5 
CS 



DISPLAY 


COMMENTS 


4.7 5 


Interest 


4.75 


Compounded monthly 


0039583 3 


4.75 1200 entered in 


6 




6 




7 2. 




1 00 




1 0. 




83 1 1.93 


Accumulated sinking f 



5. (continued) 

KEYS 

b) 12 

CS 



DISPLAY 

1 2 
- 1 2 



COMMENTS 






cs 

LOAN 



-.0 1 
1 1 1.22 



New interest entered in I 
New monthly installment 



6. To find the amount of a loan with monthly payments 
of $125, and an interest rate of 9% for 3 years, b) 4 
years, c) S120 for 4 years. 



KEYS 

9 
CS 

3 
CS 

125 
AMT 
LOAN 



LOAN 

120 
AMT 
LOAN 



DISPLAY 

9 
9 

.00 7 5 
3 
3 

3 6, 
1 25 
1 2 5. 
3 930.8 5 



4 8. 
502 3.1 

1 20 
1 2 0. 
4 8 2 2.1 7 



COMMENTS 

Interest 

Compounded monthly 
9 1200 entered in I 
Number of years 
Compounded monthly 
3x12 entered in N 

Payment amount entered in 
Loan amount is computed 



(New number 
entered in N 

i New payment 
(entered in Y 



of periods 



7. To find the amount of change and the percent change 
of a house now valued at $56,500 which was previously 
purchased for $49,750. b) present value of $30,000. 



KEYS 

a) 56500 

AMT 
49750 

b) 3O000 

AMT 
49750 



66 500 

5 6 5 0. 
4 97 50 
1 3.5 7 

6 7 50. 

30000 

3 000 0. 

4 9 7 50 
-3 9.7 
-19 7 50. 



COMMENTS 

Present value 
Enter in Y 
Past value 
% change 
Amount change 

New present value 



Negative % change 
Amount change 



Performing a sum-of-digits depreciation. Find the 
depreciation and depreciable value for each year, on 
an item with an initial cost of $3,500.00 and a salvage 
value at the end of 8 years of S675.00 



4.75 
CS 



4.7 5 
-4.7 5 
.0 0395833 



1 8. 

1 34 4 3.1 7 



5. To find the monthly payments of a loan of $5,000 
at an annual percentage rate of a) 18% for 5 years, 
b) 12%. 



5 


5 


CS 


-5 


n 


6 0. 


>000 


5000 


^MT 


5000. 


CS 


-5 0. 


OAN 


1 2 6.9 7 



COMMENTS 

Interest 

Compounded monthly 
18/1200 entered in I 
Number of years 
Compounded monthly 
5x12 entered in N 
Loan amount 
Entered in Y 

Required monthly installment; 
rounded to two decimal places 



KEYS 


DISPLAY 


COMMENTS 


3500 


3 500 




- 


3 500 


Enter initial value 


675 


6 7 5 


Enter salvage value 


- 


2825. 


Calculate change 


8 


8 




n 


8. 


Enter period in N 


SOD 


6 2 7.7 8 


1st year depreciatit 
Rounded to two de 
places 


— 


2 1 9 7.2 2 


Depreciable value 


SOD 


5 4 9.3 1 


2nd year depreciati 




1 6 4 7.9 1 


Depreciable value 


SOD 


4 7 0.83 


3rd year depreciatic 


*-* 


1 1 7 7.0 8 


Depreciable value 


SOD 


3 9 2.3 6 


4th year depreciati 


~ 


7 8 4,7 2 


Depreciable value 


SOD 


3 1 3.8 9 


5th year depreciati 


~ 


4 7 8 3 


Depreciable value 


SOD 


2 3 5.4 2 


6th year depreciati 


~ 


2 3 5.4 1 


Depreciable value 


SOD 


1 5 6.9 4 


7th year depreciaT 


^ 


7 8.4 7 


Depreciable value 


SOD 


7 8.4 7 


8th year depreciat 




0. 


Depreciable value 



3-45 




Calculators 



MM5763 statistical calculator 
general description 

The single-chip MM57S3 Statistical Calculator was 
developed using a metal-gate, P-channel enhancement 
and depletion mode MOS/LSI technology with low 
end-product cost as a primary objective. A complete 
calculator as shown in Figure 1 requires only the 
MM5763, a keyboard, DS8864 digit driver, NSA1298 
LED display, 9V battery and appropriate hardware. 

Keyboard decoding and key debounce circuitry, all 
clock and timing generation and 7-segment output 
display encoding are included on-chip and require no 
external components. Segments can usually be driven 
directly from the MM5763, as it typically sources about 
8.5 mA of peak current. [Note: The typical duty cycle 
of each digit is 0.104; average LED segment current is 
therefore approximately 0.104 (8.5 mA), or 0.9 mA 
average. Correspondingly the worse-case average segment 
current is 0.104 (5.0 mA), or 0.52 mA.] The ninth digit 
(left-most) is used for the negative sign, or the decimal 
point of a number less than unity. 

An internal power-on clear circuit is included that clears 
all registers, including the memory, when V DD and V ss 
are initially applied to the chip. 

Trailing zero suppresion allows convenient reading of the 
left justified display, and conserves power. The DS8864 
digit driver is capable of sensing a low battery voltage 
and providing a signal during Digit 9 time that can be 
used to turn on one of the segments as an indicator. 
Typical current drain of a complete calculator displaying 
five "5's" is 30 mA. Automatic display cutoff is included. 
If no key closure occurs for approximately 25 seconds, 
all numbers are blanked and all decimal points displayed. 

The Ready output signal is used to indicate calculator 
status. It is useful in providing synchronization informa- 
tion for testing or applications where the MM5763 is 
used with other logic or integrated circuits; e.g., with the 
IVHV15765 Programmer (Figure 3). 

Thirty-two keys are arranged in a four-by-nine matrix 
as shown in Figure 1. There is an automatic constant 
feature. 



The user has access to eight registers designated X, T, 
A, C, Y, S, N and M. The X-register is used for 
keyboard entry and display. The T and A-registers 
are used in multiply/divide and add/subtract calculations, 
respectively. C, Y, S and N-registers are used specifically 
for calculating the statistical functions. M is an accumu- 
lating storage memory. Statistical key functions use 
essentially all registers, including M. 

Data is entered into the calculator in floating point 
business notation. All entries and results are displayed 
left justified with insignificant zeros to the right of the 
decimal point suppressed. All intermediate results of a 



chain calculation are floating point. Terminating keys: 
equal, percent and "= +" round the display result to two 
decimal places. 

features 

■ Complete business and statistical capability 

• Arithmetic functions +, — , x, ^ 

• Per cent: includes markup and discount 

• Statistical functions: 

* "Ex" key sums X, X 2 and N 

* "2y" key sums Y, Y 2 and X • Y 

* "REMOVE x" key corrects "Sx" mistake 

* "REMOVE y" key corrects "Ey" mistake 

A "FREQ x" key sums grouped data for standard 

deviation 
A "X, SD" key calculates standard deviation and 

mean 
A "COR-SLOPE" key performs linear regression 

giving coefficient of correlation, slope, and 

intercept 
A "INT" key calculates y-intercept on line for 

given x 

■ Square root 

■ Accumulating memory 

■ Auto constant 

■ Business notation 

• +, — "adding machine" notation 

• x, ^, = algebraic notation 

■ Eight full digits 

■ Power-on clear 

■ Display cutoff 

■ Low system cost 

connection diagram (DiPTopView) 



DIGIT 3 - 
DIGIT 2 — 
DIGIT 1 - 

f K 4 - 



SEGMENT G - 
SEGMENT 8- 



■0IGIT4 
-DIGIT 5 
-DIGIT G 
■DIGIT? 
■DIGIT a 
-DIGIT 9 
■READY 

■ SEGMENT D 

■ SEGMENT E 
■SEGMENT A 
■DECIMAL POINT 

■ SEGMENT C 



Order Number MM5763N 
See Package 22 



8-46 



absolute maximum ratings 

Voltage at Any Pin Relative to V ss . (All other 

pins connected to V ss ) 

Ambient Operating Temperature 

Ambient Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 



operating voltage range 

6.5V <V SS - V DD <9.5V 

V ss always defined as most positive supply voltage. 



dc electrical characteristics 



- 0.3V to V s 



■ 12.0 



Cto+70 C 

-55°C to +150°C 

300°C 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Operating Supply Current (l DD ) 


V DD =V SS -9.5V.T A -25°C 




8.0 


16.0 


mA 


Keyboard Scan Input Levels 












(Kl, K2, K3and K4) 












Logical High Level 


V SS -6.5V < V DD < V SS -9.5V 


V ss "2. 5 






V 


Logical Low Level 


Vdd = V SS -6.5V 






Vss 5 


V 




V DD =■ V SS -9.5V 






Vss 6.0 


V 


Digit Output Levels 












Logical High Level (V OH ) 


R 1GAD = 3.2ki2toV DD 












V SS -6.5V< V aD <V ss ~9.5V 


Vss 1.5 






V 


Logical Low Level (V 0L ) 


Vdd = V ss 6.5V 






V ss 6.0 


V 




V DD -V S5 -9.5V 






Vss" TO 


V 


Segment Output Current 


T A = 25' C 










(Sa through Sg and Decimal Point! 


Vout - V ss -3.6V, V DD = V SS -6.5V 


5.0 


-8.5 




mA 




Vout =V SS -5V,V DD =V SS -8V 




-100 




mA 




Vout ' V ss 6.5V, V dd = V ss 9.5V 






15.0 


mA 


Ready Output Levels 












Logical High Level (V OH ) 


Iout = -0 4 mA 


V ss -1 






V 


Logical Low Level (V OL ) 


lour " 10mA 






V DD *1.0 


V 



ac electrical characteristics 



2 
01 
w 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Word Time (Figure 2} 






0,32 


0.8 


2.0 


ms 


Digit Time {Figure 2) 






36 


89 


222 


MS 


Segment Blanking Time {Figure 2) 






2 


5.5 


14 


MS 


Digit Output Transition Times 


•-•load 


100 pF, R LO ad =9.6kS2 




2 




Ms 


(t RISE and t FALL ) 














Keyboard Inputs High to Low 


C-LOAD 


- 100 pF 




4 




MS 


Transition Time After 














Key Release 














Ready Output Propagation Time 














(Figure 3) 

Low to High Level (t PDH ) 


Cload 


= 100 pF 


10 




50 


MS 


High to Low Level (t PDL ) 


''LOAD 


= 100 pF 






1 


ms 


Key inpdt Time-out 
Key Entry 
Key Release 






2.8 
5.1 


7.2 
12.8 


18 
32 


ms 
ms 


Display Cutoff Time 






10 


25 


63 


sec 


(The time after the last valid key 














closure that all numbers will be 














blanked and all decimal points 














displayed.) 















8-47 



CO 

in 



-^*. 



-^» 



-^ 



:i S;i St, S<: Sri S- SI S:, (l|) 

:5 MM5/63 

' A PI 0? 03 04 OS OC 7 08 09 






ci o ci ci ci ci o n n 
/_/. /_/. /_/. /_/. /_/. /_/. /_/. a. a. 



A 



FIGURE 1. Complete Calculator Schematic 



o,J- 



»~L 



WOflO TIME - 



U 1 i — u — u — U 



-SEGMENT BLANKING TIME 



»J U U U — L 



;,J L 



u 



J LT 

IJ 1_ 

il L 



J U U 1 J L 

■ ~ i i ___ r 

J U U U U 1 I L 



«cto«l display O ~l C C U D Zl I 
U I U _/ I U.C I 



i 



i_ 

"IT 



J LT 



"LT 



SEGMENT '/ y /b 

DESIGNATION p / l c 



FIGURE 2. Display Timing Diagram. 



8-48 





















1 1 


























(71 


LEO 
DISPLAY 






CALCULATOR 












I 








(4) 


Vss 
INPUTS 


SEGMENT 
OUTPUTS 
MM5763 
DIGIT 
OUTPUTS 


DECIMAL 
POINT 

READY 


PROGRAM*' 


\RUN 


DECIMAL POINT SEGMENTS 

o n n o n n 
u.u.u.u.u.u. 

DIGIT 


NSA1298 

a n o 
/_/. /_/. /_/. 












MODE 
SWITCH 














01 








, 


191 1 
























+ 


r~ 


" 


1 


(9) 


(9) 


OUTPUT V cc 
INPUT DS8864 
GND 


9V 


— 


1 


~- 


J 


DATA 




(B) 


' ' 










- 






w 


K I/O s 

K5 


MM5765 


READY 
RUNLOAD 

ALARM 








I 








DATA 

KEYBOARD 

AND 

! X4 


CONTROL 






.«■ 


□ RIVER 




* 




I < 




PKUGHAMMtR 

CONTROL LEARN MQOE 
KEYBOARD PROGRAMMER 








— — H 


" ALARM 
- INDICATOR 


■■ ' 


SWITCH 

^o 





FIGURE 3. Low Cost Handheld Programmable Statistician Computer Using the MM5763 Calculator and MM5765 Programmer. 



KEYBOARD BOUNCE AND NOISE REJECTION 

The MMb763 is designed to interface with most low 
cost keyboards, which are often the least desirable 
from a false or multiple entry standpoint. 

A kev closure is sensed by the calculator chip when 
one of the key inputs, K1, K2, K3 or K4 are forced 
more Dositive than the Logical High Level specified in 
the e ectrical specifications. An internal counter is 
started as a result of the closure. The key operation 
begins after nine word times if the key input is still 
at a _ogical High Level. As long as the key is held 
down (and the key input remains high) no further 
entry is allowed. When the key input changes to a 
Logic; I Low Level, the internal counter starts a sixteen 
word time-out for key release. During both entry and 
releass time-outs the key inputs are sampled approxi- 
mately every other word time for valid levels. If they 
are fo jnd invalid, the counter is reset and the calculator 
assum;s the last valid key input state. 

One o the popular types of low-cost keyboards available, 
the e astomeric conductor type, has a key pressure 
versus contact resistance characteristic that can generate 
contir uous noise during "teasing" or low pressure key 
depreisions. The MM5763 defines a series contact 
resist; nee up to 50 kil as a valid key closure, assuring a 
reliab e interface for that type of keyboard. 

AUTOMATIC DISPLAY CUTOFF 

If no key is depressed for approximately twenty-five 
seconds, an internal automatic display cutoff circuit 
will b ank all segments and display nine decimal points. 
Any Ley depression will restore the display; to restore 
the display without modifying the status of the calculator, 
use two Change Sign key depressions. 

READY SIGNAL OPERATION 

Thf Ready signal indicates calculator status. When the 
calculator is in an "idle" state the output is at a Logical 
High Level (near V ss ). When a key is closed, the internal 
key entry timer is started. Ready remains high until the 
time-out is completed and the key entry is accepted as 
valid, then goes low as indicated in Figures 4 and 5. It 
remains at a Logical Low Level until the function initiated 
by the key is completed and the key is released. The low 



to high transition indicates the calculator has returned to 
an idle state and a new key can be entered. 

ERROR INDICATION 

In the event of an operating error, the MM5763 will 
display all zeros and all decimal points. The error 
indication occurs if division by zero is attempted or 
either a result or intermediate value exceeds 99999999. 

The indication is cleared by depressing any key. 

If an error results from a "+" or "— " key, the X-register 
is cleared and the last entry is saved in the A-register; all 
other registers are not effected. An error condition 
during "x" or "^" operations clears X without changing 
any of the other registers. 

Overflow as a result of the statistical keys can effect 
any register they use; "CA" should be depressed if an 
error occurs. 

Overflow as a result of "M+" saves the value stored in M, 
clears X and displays the error indication. Calculations 
are immediately stopped and other registers are not 
cleared. 

AUTOMATIC CONSTANT 

The MM5763 retains as a constant the first factor of a 
multiplication calculation or the second factor of a 
division calculation, when that calculation is terminated 
by "=" key, "%" key or "= +" key. Subsequent 
calculations using the stored constant are made by 
entering a number and operating upon it with the 
appropriate terminator ("=," "%" or "= +" key). The 
T-register is used to store the constant in the constant 
mode of operation. 

The calculator automatically changes to the chain mode 
when a "x" or 'S-" key occurs in the calculation. In 
the chain mode, the result of each "x" or "^" key is 
stored in both X and T-registers. A new entry replaces 
X without altering T. At the completion of a chain 
calculation, the T-register will contain the value used as 
first factor of the last multiply, or the latest entry if the 
last operation was a divide. 

Table I summarizes the four modes. 



8-49 



CO 

to 
in 



TABLE I. Mode Summary 



MODE 


KEYS THAT 
SET MODE 


DESCRIPTION 
(See Calculation Examples} 


CONSTANT 
MULTIPLY 


"CLEAR" 


Depression of an "=," "= +" or "%" key will multiply 
the X-register by the T-register and replace X with the 
product. T remains unchanged. 


CHAIN 
MULTIPLY 


"x," 
following a terminator, or 
or "x" operation 


Depression of an "=," "= +" or "%" key will multiply 
the X-register by The Y-register and place The product in 
X. T remains unchanged. 


CONSTANT 
DIVIDE 




With calculator 
previouslv in chain 
divide mode. 


Depression of an "-," "- + " or % key will divide the 
X-register by the T-register and replace X with the 
quotient. T is unchanged. 


CHAIN 
DIVIDE 


following a terminator or "-.-" 
or "x" operation 


Depression of an "=," "= +" or "%" key wili divide the 
T-register by the X-register, transfer X to T, and place 
the quotient in X. 



DIGIT / [^ 



X 



r~iL 



FIGURE 4. Ready Timing. 



NEW 

KEVIS 

DEPRESSED 



■-9W08DS— ■ *-! 



ANY 

SWITCH 

INPUT 



JJUULJULl 



NEW KEV HAS 
BEEN ACCEPTED 
BY CALCULATOR. 
THE KEY MAY 
BE RELEASED 



16WQRDS AFTER 

KEY RELEASE OR 

AFTER CALCULATION 

IS COMPLETE, 

WHICHEVER IS 

LONGER 



FIGURE 5. Functional Description of Ready Signal and Key Entry. 



r 



NEXT KEY 

CAN BE 
ENTERED. 



KEY OPERATIONS 

(Note: Register X is always displayed.) 
Clear Key, "C" 

Following a number entry key, it clears the X-register 
only (clear entry). Following any other key it clears 
registers X, K, C, S, N and T. 

Clear All Key, "CA" 

Clears all registers and sets the calculator to the constant 
multiply mode. 

Number Entries 

The first entry clears the X-register and enters the 
number into the LSD of X. Second through eighth 
entries (excluding a decimal point) are entered one 
digit to the right of the last number. The ninth, and 
subsequent entries are ignored. First entry after a "+," 
"— ," or "M+" following a "+" or "— " key causes the 
number in the X-register to be transferred to the A- 
register before clearing and placing the new entry in X. 



Decimal Point, "." 

As the first depression of a number entry, it clears the 
X-register and places a point in the left most digit. If the 
previous key was a number, it enters a decimal point 
to the right of the last number entered. Following a 
"+," " — ," or "M+" following a "+" or "— ," the 
X-register is transferred to A, cleared and a decimal 
point entered in the leftmost digit. The last decimal 
point depression of a number entry is accepted as the 
valid point. 

Change Sign Key, "CS" 

Changes sign of register X. 

Addition Key, "+" 

If the previous key was not a "+" or "-" key, the number 
in the A-register is added to the X-register, X is transferred 
to A, and the sum is stored in X. When the last key was 
a "+" or "— " key, the number in A is added to the 
number in X without destroying the value of A. The 
sum is stored in X. 



I-50 



Subtraction Key, 



Memory Recall/Memory Clear Key, "MR" 



If the previous key was not a "+" or "-" key, the number 
in the X-register is subtracted from the number in the 
A-register, X is transferred to A, and the difference is 
stored in X. When the last key was a "+" or "-" key, 
the number in A is subtracted from X without destroying 
the value of A. The result is stored in X, 

Multiplication Key, "x" 

If there has not been a "x" or "-f-" key since the last 
terminator key ("=," "= +" or "%"), the value of the 
X-register is copied into the T-register and the calculator 
is set to the chain multiply mode. In a chain calculation 
in which there has been a "x" key since the last terminator 
or "+" key, X is multiplied by T and the resulting 
product is stored in both X and T; if a "V key has 
occured since the last terminator or "x" key, depression 
of "x" will divide the T-register by the X-register, with 
the quotient stored in both X and T. 

Division Key, "+" 

If there has not been a "x" or "^" key since the last 
terminator key ("=," "= +" or "%"), the value of the 
X-register is copied into the T-register and the calculator 
is set to the chain divide mode. In a chain calculation if a 
"x" key has occured since the last terminator or "-:■■" 
key, X is multiplied by T and the product is stored in 
both X and T; if a "^" key has occured since the last 
terminator or "x" key, depression of "^" will divide 
the T-register by the X-register, with the quotient stored 
in both X and T. 

Equal Key, "=" 

In the chain multiply mode, the value in the X-register 
is multiplied by the T-register with the product stored 
in X. Register T remains unchanged. In the chain divide 
mode, depression of "=" will divide Y by X, transfer X 
to T, and place the quotient in X. If the calculator is in 
constant multiply, "=" will multiply X by T, place the 
product in X and retain T. For constant divide, the 
X-register is divided by T, the quotient is stored in X; 
T is unchanged. 

The "=" key always rounds the answer stored in X to 
two places to the right of the decimal point, and clears 
register A. 

Per Cent Key, "%" 

This key acts exactly like the "=" key except the value 
of X is divided by 100 and copied in register A before 
performing the required operation. Register A is not 
cleared. The result stored in the X-register is rounded to 
two decimal positions. 



Automatic Accumulation Key, 



"= +" 



It acts just like the "=" key in all modes. After the result 
is stored in X, the value of X is added to the number in 
the M-register. The result stored in X and accumulated 
into M is rounded to two decimal places. Register A is 
cleared. 



Following any key except "MR," the value of the 
M-register is copied in to the X-register. If the preceding 
key was "+," "— " or "M+" following "+" or "— ," the 
number in the X-register is transferred to the A-register 
before M is recalled. Following another "MR" key, the 
M-register is transferred to X, then cleared. 

Memory Plus Key, "M+" 

The number in the X-register is accumulated in the 
M-register. Registers X and A are not changed, so the 
repeat addition or subtraction conditions that existed 
before accumulation to memory are still valid. 

Square Root Key, "\fx " 

The absolute value of the number in the X-register is 
replaced with its square root. 

Sum of X Key, "Zx" 

Adds X to the C-register, adds the square of X to the 
T-register, saves the value of X (to four decimal places) 
in the Y-register and increments N by one. The operation 
is completed by copying N into X. The maximum value 
of N is 99. The register returns to zero on the 100th entry. 

Sum of Y Key, "Xy" 

Adds the value of X to the A-register, adds the square 
of X to the M-register, adds the product of X and Y to 
the S-register, and recalls N to X. 

Remove X Key, "REM X" 

This is used to delete a data point previously entered by 
"Zx" key. It subtracts X from C, subtracts the square of 
X from T, saves X to four decimal places in Y, decrements 
IN by one and copies the new value of N in to X. 

Remove Y Key, "REM Y" 

This is used to delete an incorrect data point previously 
entered by the "Sy" key. It subtracts X from A, 
subtracts the square of X from M, subtracts the product 
of X and Y from S and copies N to X. 

Frequency of X Key, "FREQ" 

This is used to sum grouped (identical) data entries for 
mean and standard deviation computations. If the sign 
of X is positive, "FREQ" performs the "2x" operation 
X - 1 times. When X is negative, "FREQ" performs the 
"REM X" function IXl - 1 times. 

Mean and Standard Deviation Key, "X, SD" 

Computes both the arithmetic mean and the standard 
deviation of data points (entered by the "Sx" and 
"FREQ" keys) with a single key depression. The mean 
is stored in register X (and therefore is the initial result 
displayed). Standard deviation is stored in registers A 
and M and is displayed by using the "MR" key. Registers 
T, C and N are saved so that additional data points may 
be entered or deleted, and new mean and standard 
deviation values calculated. 



1-51 



CO 
CO 

r» 



Correlation Coefficient and Slope Key, "COR SLOPE" 

The correlation coefficient and slope of a least squares 
line fit of accumulated paired data values (that have 
been entered with the "Sx" and "Zy" keys) are 
computed with a single key stroke. The correlation 
coefficient is stored in registers X and S (and therefore is 
the initial result displayed). Slope is in M and is obtained 
by using the "MR" key. Registers T and C are lost. 



Y-lntercept Key, "INT" 

After the "COR SLOPE" key has been used to compute 
a least squares line fit on a set of paired data values, 
any y-coordinate corresponding to a given x-coordinate 
lying on that line can be computed by entering the 
x-coordinate in X, and depressing "INT." 



TABLE It. Summary of Statistical Functions 



KEY 


REGISTERS 


STATISTICAL EQUATION 




X > Y 

X 2 ■ t - T, where r = original vaiue of T 
n + 1 -> N, where n = original value of N 


::,,«„« „ 


"IV 


Xi,i > A. where a = original value of A 

X 2 i m -*■ M, whore m -■ onqioal vahut: u' M 


i*\ 


"REM x" 


o ■■ X - C 
t X 2 - T 
n ■ 1 • N 


Deln-.e X n 
Delete x„ : ' 
Decement n 


"REM y" 


a ■■ X 'A 

s- IX ■ Yi - S 


Delete y r 
Delm: v,. ? 


"X, SD" 


* X 
N 

C 2 

y"' N - 1 


SD 


"COR-SLOPE" 


C • A 
N 


-* - v - -— 


> c :)(- a :i 

C ■ A 
S - ..... _. 


i----)^ n 


C 2 
T 

N 

A - M ■ C 

N 


i,.- y •".-.* 


"INT" 


M ■ X +■ A- X 


V „,.„,*.!. 



EXAMPLES 






1. Addition or subtraction 


2.0 






3.2 






-12.3 


KEYS 


DISPLAY 


COMMENTS 


2 


2 
2. 




3 


3 
3. 




2 


3.2 
5,2 




2 


1 2 
1 2. 




3 


1 2.3 




- 


-7.1 




C 


0. 




2. Repeat add 


or subtract 




KEYS 


DISPLAY 


COMMENTS 


3 
1 


3 
3 

3.1 
3.1 




< 


6.2 
9.3 
6.2 




C 


0. 





3. Chain multiplication or division 



COMMENTS 



2 


1 


X 


2. 


3 


3 




3. 


1 


3.1 


X 


6 2 


4 


4 


2 


4.2 




2 6.0 4 






1 




1 


2 


2 




5. 





1 




.5 


? 


2 


= 


.2 5 



1-52 



EXAMPLES (Continued) 
3. (Continued) 



7. Perform add-on and discount 



EYS 


DISPLAY 


COMMENTS 


2 


2 







20 




X 


2 0. 




4 


4 
8 0. 




8 


8 




^ 


1 0. 




7 


7 




X 


1.4 2 8 5 7 1 4 




4 


4 




= 


5.7 1 


Result rounded to 



4. Constant multiplication or division 



KEYS 


DISPLAY 


3 


3 


X 


3. 


2 


2 


= 


6 


4 


4 


- 


1 2. 


5 


5 




5. 


2 


5 2 


- 


1 5.6 


= 


4 6.8 


5 


5 


- 


5 


2 


2 


= 


2.5 


4 


4 


= 


2. 


5 


5 




5. 


2 


5.2 


= 


2.6 


- 


1.3 



COMMENTS 



"i constant multiply 



KEYS 




DISPLAY 


al Add-On. 


1 25 + 5% 


1 
2 




1 
1 2 


5 




1 2 5. 


X 




1 2 5. 


5 




5 

6.2 5 
1 3 1.2 6 


b) Discount 


532. 


-6% 


5 




5 


3 




53 


2 

1 




5 3 2 
5 3 2 
5 3 2.1 


X 




5 3 2.1 


6 




6 

3 1.9 3 


- 




500.1 7 



COMMENTS 



5% of 125 is displayed 
125 J 5% is displayed 



6% of 532.1 is displayed 
532.1 -6% is displayed 



8. Perform change sign 



5. To perform products of sum; e.c 
(5 + 4) x (3 + 2)/(6 + 7) = 

KEYS DISPLAY 







KEYS 


DISPLAY 


COMMENTS 






1 
2 


1 
1 2 




Second factor 


n constant divide 


CS 
3 

CS 
5 

CS 
6 
C 


1 2 

-1 2 3 

-1 2 3. 
1 2 3. 
1 2 3.5 
1 2 3.5 
1 2 3.5 6 
0. 


Change sign does not 
terminate entry. 



COMMENTS 





5 




5 
5. 




4 




4 
9. 




X 




9. 




3 




3 




+ 




3. 




2 




2 




+ 




5. 




- 




4 5. 




6 




6 
6. 




7 




7 
1 3 




= 




3.4 6 


6. 


Calculate 


percentage 




5% of 300.25 






KEYS 




DISPLAY 




3 




3 









3 









300 
3 0. 




2 




3 0.2 




5 




3 0.2 5 




x 




3 0.2 5 




5 




5 

1 5.0 1 



(5 - 4) x (3 * 2) 



45 : (6 ■+■ 7} is executed and 
rounded to two places 



COMMENTS 



9. Accumulate in memory, recall and clear memory 

COMMENTS 

Accumulate in memory 

Accumulate In memory 

Recall memory 

Recall and clear memory 

Recall and clear memory 



ilate in memory 



"Live %" key executes 
operation and rounds two 
places 



EYS 


DISPLAY 


3 


3 


M» 


3. 


4 


4 


M + 


4. 


5 


5 


MR 


7. 


MR 


7. 


MR 


0. 


5 


5 


t 


5. 


6 


6 


Mi 


1 1. 


7 


7 


^ 


1 8. 


Mt 


1 8. 


* 


2 5. 


3 


3 


2 


3 2 




3 2 


2 


3 2.2 


CS 


-3 2.2 


M + 


3 2 2 


9 


9 


+ 


3 4 


MR 


3.2 


* 


3 0.8 


MR 


-3.2 


MR 


3.2 


MR 


0. 



Accumulate in memory 
Repeat add 



Accumulated value of M is recalled 



Accumulated value of M is recalled 
M is cleared 



i-53 



EXAMPLES (Continued) 










10. Accumulate 


in memory with the "= +" key 








KEYS 


DISPLAY 


COMMENTS 


CS 


7 




5 


5 




FREQx 


3. 


Negative x sets 








"REMOVE x" function 


X 


5. 




5 


5 




3 


3 






4. 




= f 


1 5. 


5x3= 15 is added to M 


4 


4 




4 


4 
4, 




FREQx 


7. 


Corrected data has been 










entered 


2 


4.2 




X, SD 


4.57 1 4 28 5 




x 


4.2 




MR 


.534 523 15 




3 


3 










- + 


1 2.6 


4.2 x3 = 12.6 is added to M 








6 


6 




dl Compute r 


unning mean and standard deviations 




6. 
7 
.8 6 




Data: 7, 8, 


6,7,5 




='t 


f Rounded to 2 decimal places 


CA 


0. 




9 


9 


\ and added to M 


7 


7 




CS 


9 


Note method of multiplying 


2x 


1. 




X 


-9. 


negative number 


8 


8 




4 


4 




1'x 


2. 


n ■ 2 


= t 


-3 6. 


-9x4 = -36 is added to M 


X, SD 


7.5 


Mean of first two data 


MR 


-7.5 4 








entries 








MR 


.707 10678 


Standard deviation of 
first two data entries 


STATISTICAL 


FUNCTIONAL 


EXAMPLES 


6 

Sx 


6 
3. 


n = 3 


1. Perform mean and standard 


deviation 


X. SD 


7. 


Mean of first three entries 








MR 


1. 


Standard deviation of 


KEYS 


DISPLAY 


COMMENTS 


7 


7 


first three entires 


a) Data: 4.0, 5. 


, 4.5 




£x 


4. 


n = 4 


CA 
4 


0. 
4 
1 




X, SD 


7. 


Mean of first four entries 




MR 


.8 16496 5 7 


Standard deviation of 


( Display indicates first data 






first four entries 


5.1 
4.5 


5.1 
2. 
4.5 
3. 


V point has been entered 
2nd data point entered 


5 

Zx 
X, SD 


5 
5. 
6.6 


Mean of all five entires 




MR 


1.1 40 1 754 


Standard deviation of all 




3rd data point entered 








X, SD 


4.5333333 


Mean and standard 
deviation are com- 






five entires 






puted; mean is 


2. To perform 


least squares line 


fit on given data 






displayed 


(See piottec 


data on page 10) 


MR 


,5 5075765 


Standard deviation is 












recalled from M 


KEYS 


DISPLAY 


COMMENTS 


b) Data: 3, 3, 


3, 3, 4.1, 3.6 




a) Data: 1, 1 
3, 2 






CA 


0. 


Always use "CA" after mean 


4, 3 






3 


3 


and SD calculation 


6,4 






4 


4 




CA 









FREQx 


4 


Grouped data points may 




1 






4.1 


4.1 


be entered conveniently 


Ix 


1. 




n 1 


— x 


5. 


using the "FREQ" key 


1 


1 






3.9 


3.9 




~v 


1. 






ISx 


6. 


Wrong data entry 


3 


3 






3.9 


3.9 




-X 


2. 




n =■• 2 


REM x 


5. 


Wrong data is removed Five 


2 


2 




3.6 


3.6 


data points are entered. 


'iv 


2. 






lix 


6. 




4 


4 






X, SD 


3.28333 3 3 


Mean and standard 


iix 


3. 




n -■ 3 






deviation are computed: 


3 


3 








X is displayed 


-V 


3. 






MR 


.4 6654774 


Standard deviation is 


6 


6 








recalled from M 


4 


4. 
4 




c) Correction of 


group data entered 


with "FREQ" 


-y 


4 




Data. 4, 4, 4 


5, 5, 5, 5 




COR-SLOPE .9 9227788 


Correlation coefficient 












s displayed (perfect 


CA 


0. 








correlation = 1.0) 


4 


4 




rVR 


6 1538461 


Slope of least squares 


Lx 


1. 








line fit is recalled from 


3 


3 








M 


FREQx 


3 










x = 


5 


5 




INT 


.346154 


y-intercept of least 


iix 


4. 








squares line at x = 


7 


7 








is computed 


FREQx 


10. 


7 Is incorrectly entered 


8 


8 


x -- 8 


5 


5 




INT 


5. 2692308 


y-intercept of least 


REM x 


9. 








squares line at x = 


7 


7 








is computed 



1-54 



STATISTICAL FUNCTION EXAMPLES (Continued) 

2. (Continuedi 



7 
6 
5 

(Vl 4 



































I 








• 


LEAST SQUARES- 




<f 






i^dlLOPE 






W^ 








-i. 


* 


* 




Gl 
-P0 


k/EN DATA 


J 






L_ 







12 3 4 5 6 7 



b) Data: 2, 5 
1. 4 
0, 3 



KEYS DISPLAY 

CA 0. 

2 2 



KEYS DISPLAY 



Sx 


1 


5 


5 


i'v 


1 


8 


8 


v x 


2. 


9 


9 


-V 


2. 


8 


8. 


REM x 


1. 


9 


9 


REVI v 


1, 


Ix 


2 


4 


4 


-y 


2 








^x 


3. 


3 


3 


-V 


3 


COR-SLOPE 


1. 


MR 


1 


3 


3 


INT 


6. 



COMMENTS 



Wrong data point is 
entered 

n, = 2 

n y = 2 

Wrong data point is 

removed 

n„ - 1 



n v - 1 
n =2 



Correlation coefficie 
is displayed 
Slope is displayed 
For x = 3, 
the y-intercept is 6 



2 

w 

01 

w 



EO 



i-55 




Calculators 



MM5764 conversion calculator 



general description 



The single-chip MM5764 Conversion Calculator was 
developed using a metal-gate, P-channel enhancement 
and depletion mode MOS/LSI technology with low 
end-product cost as a primary objective. A complete 
calculator as shown in Figure 1 requires only the 
MM5764, a keyboard, DS8864 digit driver, NSA1298 
LED display, 9V battery and appropriate hardware. 



Data is entered into the calculator in floating point 
business notation. All entries and results are displayed 
left justified with insignificant zeros to the right of the 
decimal point suppressed. All intermediate results of a 
chain calculation are floating point. Terminating keys 
"=," "%," and "= +" round the displayed result to two 
decimal places. 



Keyboard decoding and key debounce circuitry, all 
clock and timing generation and 7-segment output 
display encoding are included on-chip and require no 
external components. Segments can usually be driven 
directly from the IV! M 5 7 64, as it typically sources about 
8.5 mA of peak current. [Note: The typical duty cycle 
of each digit is 0.104; average LED segment current is 
therefore approximately 0.104 (8.5 mA), or 0.9 mA 
average. Correspondingly the worse-case average segment 
current is 0.104 (5.0 mA}, or 0.52 mA.] The ninth digit 
(left-most) is used for the negative sign, or the decimal 
point of a number less than unity. 

An internal power-on clear circuit is included that clears 
all registers, including the memory, when V DD and V ss 
are initially applied to the chip. 

Trailing zero suppresion allows convenient reading of the 
left justified display, and conserves power. The DS8864 
digit driver is capable of sensing a low battery voltage 
and providing a signal during Digit 9 time that can be 
used to turn on one of the segments as an indicator. 
Typical current drain of a complete calculator displaying 
five "5's" is 30 mA. Automatic display cutoff is included. 
If no key closure occurs for approximately 25 seconds, 
all numbers are blanked and all decimal points displayed. 

The Ready output signal is used to indicate calculator 
status. It is useful in providing synchronization informa- 
tion for testing or applications where the MM5764 is 
used with other logic or integrated circuits; e.g., with the 
MM5765 Programmer (Figure 3). 

Thirty-two keys are arranged in a four-by-nine matrix 
as shown in Table I. There is an automatic constant 
feature. 

The user has access to five registers designated X, T, 
A, K and M. The X-register is used for keyboard entry 
and display. The T and A-registers are used in multiply/ 
divide and add/subtract calculations, respectively. M is 
an accumulating storage memory. The K-register is used 
to store a user defined conversion constant. 



features 

■ Full 8-digit entry and display calculator 

■ Arithmetic functions: +, — , x, -r, =, %, 1/x 

■ Percent mark-up and discount 

■ Twenty automatic conversions 

■ A user definable conversion key 

■ Change sign and "ft" keys 

■ Accumulating memory: MR, IV +, =+, MC 

■ Square root . 

■ Auto constant 

■ Business notation 

• +, - "adding machine" notation 

• x, -^, = algebraic notation 

■ Automatic power-on clear 

■ Automatic display cutoff 

■ Direct 9V battery compatibility; low power 

connection diagram 

Dual-ln-Line Package 



DIGIT 3- 

DIGIT2- 

DIGIT1 - 

K 4 - 

K3- 

K Z - 

l Ki - 

Vdd- 

SEGMENTG- 

SEGMENT B - 

SEGMENT F- 



- DIGIT 6 

- DIGIT 7 

1 
-DIGITS 

-DIGIT 9 
-READY 

- SEGMENT D 

- SEGMENT E 
-SEGMENT A 
-DECIMAL POINT 

- SEGMENT C 



TOP VIEW 

Order Number MM5764N 
See Package 22 



3-56 



absolute maximum ratings 

Voltage at Any Pin Relative to V ss . (All other 

pins connected to V ss ) 

Ambient Operating Temperature 

Ambient Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 

operating voltage range 

6.5V <V SS - V DD <9.5V 

V ss always defined as most positive supply voltage. 

dc electrical characteristics 



+ 0.3V to V ss - 12.0 

0°C to +70°C 

-55°C to+150X 

300° C 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Operating Supply Current II DD ) 


V DD - V SS -9.5V, T A - 25"C 






160 


mA 


Keyboard Scan Input Levels 












|K1, K2, K3 and K4) 












Logical High Level 


V SS -6.5V> V DD «. V ss 9.5V 


Vss- 2 - 5 






V 


Logical Low Level 


V OD - V sq 6.5V 






Vss 5 


V 




V DD - V SS -9.5V 






V S s 6 


V 


Digit Output Levels 












Logical High Level (V C() ) 


Rload -3.2k<» to V DD 












V ss 6.5V-;'. V nlJ <. V s3 -9.5V 


V ss 1.5 






V 


Logical Low Level (V ol I 


V D D = V ss -6.5V 






V'ss 6.0 


V 




V DD = V ss 9.5V 






V S s 7 


V 


Segment Output Current 


T A -25 C 










(Sa through Sg and Decimal Point) 


V ou , - V ss 3.6V, V DD - V ss 6.5V 


-5.0 


-8.5 




mA 




Vout ' v ss 5V. V DD - V ss 8V 




- 10.0 




mA 




V OUT 'V ss 6.5V, V DD -- V ss 9.5V 






-15 


mA 


Readv Output Levels 












Logical High Level (V OH ) 


l OUT = 0.4 mA 


Vss ■ 1 ° 






V 


Logical Low Level (V OL ) 


lout "- 10- A 






V DD -r1.0 


V 



ac electrical characteristics 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Word Time (Figure 2) 






0.32 


0.8 


2.0 


ms 


Digit Time [Figure 2) 






36 


89 


222 


Ms 


Segment Blanking Time {Figure 2) 






2 


5.5 


14 


Us 


Digit Output Transition Times 


Cj. OAD 


100 pF, Rload - 9.6 kS! 




2 




MS 


(tpist and t rAt L } 














Keyboard Inputs High to Low 


Cload 


- 100 pF 




4 




Ms 


Transition Time After 














Key Release 














Ready Output Propagation Timsi 














[Figure 3) 














Low to High Level (t PDH ) 


C l o a n 


' 100 pF 


10 




50 


MS 


High to Low Level <t PDL ) 


C, OAD 


100 pF 






1 


ms 


Key Input Time-out 














Key Entry 






2 8 


7.2 


18 


ms 


Key Release 






5.1 


12.8 


32 


ms 


Display Cutoff Time 






10 


25 


63 


sec 


(The time after the last valid key 














closure that all numbers will be 














blanked and all decimal points 














displayed.) 















2 
en 

-si 

en 



J 



857 



(0 
r- 
in 



^* 



-i* 



V_ 



-i»- 



Kl Sa Sb Sc Ed Se Sf Sg dp 

K2 

K3 MM5761 

K* 1 01 02 D3 Dfl 05 U6 1)7 D8 D9 



-^»- 



KEYBOARD 
Note; See Table II inr Key Matrix Designator 



dp Sij Sf Si; St! Sc Sb S;i NSA1I 

o a o o a a o r/ /~/ 
/_/. /_/. /_/. /_/. /_/. /_/. /_/. o. o. 

no ua 0/ uu D5 u<j uj nz ui 



FIGURE 1. Complete Calculator Schematic 



— — UK 

1" 

POWtR A 
SK „CK \ 



DIGIT 

OUTPUTS 

D, 





-— WORD TIME ■■■ 




~— 
















--DIGIT! 


IME 










02 




























03 


























D9 


1 












! 








J 




SEGMENTS 














Sa 


J 


J 


1 II 


LI 


il 




I 






— 


|— SEGMENT BLANK 


NG TIME 








Sb 




J J 


r i 


1 


1 1 


j J 


I 


Sc 








i i 












1 J u u 

! ! 


J 


1 1 


j 




1 












Sd 




J J 


i ii 


1 1 


1 


1 




















Se 


J 




1 


i i 


1 










1 ! 




i 






Sf 


J U u 


i i 












i 












Sg 


1 


I 


J u u 


i i 




1 


I 



ACTUAL DISPLAY /— / / /— . '—. '—! — 1 1 .—' j 



FIGURE 2. Display Timing Diagrarr 



SEGMENT *IJLl b 

DESIGNATION e / # c 



8-58 













1, 






-H 


>__ ■ 


























17} 

1 ' 


LED 




CALCULATOR 












I 










(4) 


Vss 

K 
INPUTS 


SEGMENT 
OUTPUTS 
MM5764 
DIGIT 
OUTPUTS 


DECIMAL 
POINT 

READY 


PROGRAM *■ 


ytuN 


DECIMAL POINT SEGMENTS 

/-/ n n o o a 
u.u.u.u.u.u. 

DIGITS 


NSA1298 

/"/ o o 
/_/. /_/. /_/. 












SWITCH 












(9) 








i 


,., , 








1 


i 
















1 


19) 


0) 


OUTPUT V cc 
INPUT DM8864 
GND 


9V _= 


1 

/ 


-- 


-1— 

J 


DATA 




(B) 


' ' 










/ 




W 


K t/O's 
K5 


MM5765 
Vqd 


READY 
RUN LOAD 

ALARM 








t 






DATA 

KEYBOARD 

AND 

1 X4 


CONTROL 








DRIVER 
POWER 






> ■■■< 


LED 


PROGRAMMER 
CONTROL 
KEYBOARD 


LE 
PRO 


RN M 
GRAN 


ODE 

1MER 




i 


V ALARM 
- INDICATOR 

> 


■< 


-^0— 








FIGURE 3. Low Cost Handheld Programmable Calculator Using the MM5764 Calculator and MM5765 Programmer. 



KEYBOARD BOUNCE AND NOISE REJECTION 

The MM5764 is designed to interface with most low 
cost keyboards, which are often the ieast desirable 
from a false or multiple entry standpoint. 

A key closure is sensed by the calculator chip when 
one of the key inputs, K1, K2, K3 or K4 are forced 
more positive than the Logical High Level specified in 
the electrical specifications. An internal counter is 
started as a result of the closure. The key operation 
begins after nine word times if the key input is still 
at a Logical High Level. As long as the key is held 
down (and the key input remains high) no further 
entry is allowed. When the key input changes to a 
Logical Low Level, the internal counter starts a sixteen 
word time-out for key release. During both entry and 
release time-outs the key inputs are sampled approxi- 
mately every other word time for valid levels. If they 
are found invalid, the counter is reset and the calculator 
assumes the last valid key input state. 

One of the popular types of low-cost keyboards available, 
the elastomeric conductor type, has a key pressure 
versus contact resistance characteristic that can generate 
continuous noise during "teasing" or low pressure key 
depressions. The MM5764 defines a series contact 
resistance up to 50 kf2 as a valid key closure, assuring a 
reliable interface for that type of keyboard. 

AUTOMATIC DISPLAY CUTOFF 

If no key is depressed for approximately twenty-five 
seconds, an internal automatic display cutoff circuit 
will blank all segments and display nine decimal points. 
Any key depression will restore the display; to restore 
the display without modifying the status of the calculator, 
use two Change Sign key depressions. 

READY SIGNAL OPERATION 

The Ready signal indicates calculator status. When the 
calculator is in an "idle" state the output is at a Logical 
High Level (near V ss ). When a key is closed, the internal 
key entry timer is started. Ready remains high until the 
time-out is completed and the key entry is accepted as 



valid, then goes low as indicated in Figures 4 and 5. It 
remains at a Logical Low Level until the function initiated 
by the key is completed and the key is released. The low 
to high transition indicates the calculator has returned to 
an idle state and a new key can be entered. 

ERROR INDICATION 

In the event of an operating error, the MM5764 will 
display all zeros and all decimal points. The error 
indication occurs if division by zero is attempted or 
either a result or intermediate value exceeds 99999999. 

The indication is cleared by depressing any key. 

If an error results from a "+" or "-" key, the X-register 
is cleared and the last entry is saved in the A-register; no 
other registers are affected. An error condition during 
"x" or "-r-" operations clears X without changing any of 
the other registers. 

Overflow as a result of "M+" saves the value stored in M, 
clears X and displays the error indication. Calculations 
are immediately stopped and other registers are not 
cleared. 

Overflow as a result of a conversion clears X and saves 
all other registers. 

AUTOMATIC CONSTANT 

The MM5764 retains as a constant the first factor of a 
multiplication calculation or the second factor of a 
division calculation, when that calculation is terminated 
by "=" key, "%" key or "= +" key. Subsequent 
calculations using the stored constant are made by 
entering a number and operating upon it with the 
appropriate terminator ("=," "%" or "= +" key). The 
T-register is used to store the constant in the constant 
mode of operation. 

The calculator automatically changes to the chain mode 
when a "x" or "-r" key occurs in the calculation. In 
the chain mode, the result of each "x" or "V key is 
stored in both X and T-registers. A new entry replaces 
X without altering T. At the completion of a chain 



i-59 



in 



TABLE I. Mode Summary 



MODE 


KEYS THAT 
SET MODE 


DESCRIPTION 
(See Calculation Examples) 


CONSTANT 
MULTIPLY 


"CLEAR" 

"%" 


Depression of an "=," "= +" or "%" key will multiply 
the X-register by the T-reglster and replace X with the 
product. T remains unchanged. 


CHAIN 
MULTIPLY 


following a terminator, or ■ 
or "x" operation 


Depression of an "=," "= +" or "%" key will multiply 
the X-register by the T-register and place the product in 
X. T remains unchanged. 


CONSTANT 
DIVIDE 


::;':' 


With calculator 
previously in chain 
divide mode. 


Depression of an "=," "= +" or "%" key will divide the 
X-register by the T-register and replace X with the 
quotient. T is unchanged. 


CHAIN 
DIVIDE 


following a terminator or - 
or "x" operation 


Depression of an " = ," "-■ +" or "%" key will divide the 
T-register by the X-register, transfer X to T, and place 
the quotient in X. 



X 



FIGURE 4. Ready Timing 



NEW 

KEY IS 

DEPRESSED 



ANY 

SWITCH 

INPUT 



JL^XjLI 



1G WORDS AFTER 
KEY RELEASE OR 

AFTER CALCULATION 

IS COMPLETE. 

WHICHEVER IS 

LONGER. 



r 



NEW KEY HAS 
BEEN ACCEPTED 
BY CALCULATOR. 
THE KEY MAY 
BE RELEASED. 



NEXT KEY 

CAN BE 
ENTERED. 



FIGURE 5. Functional Description of Ready Signal and Key Entry. 



calculation, the T-register will contain the value used as 
first factor of the last multiply, or the latest entry if the 
last operation was a divide. 

Table I summarizes the four modes. 



KEY OPERATIONS 

(Note: X-register is always displayed.) 
Clear Key, "C" 

Following a number key, it clears only the X-register 
(clear entry); after any other key, it clears registers X, 
A and T. 



Number Entries 

The first entry clears the X-register and enters the 
number as the LSD of X. Second through eighth 
entries (excluding a decimal point) are entered one 
digit to the right of the previous number. The ninth, and 
subsequent entries, are ignored. First entry after a "+," 



"-," or "M+" following a "+" or "-" key transfers the 
existing number in the X-register to the A-register before 
clearing and placing the new entry in X. 

Conversion Functions 

With the exception of the six single function conversion 
keys, all conversions are preceded by either the shift key, 
"-►/' or the reverse conversion key, "<-," Depression of 
the appropriate conversion key replaces the value in the 
X-register with a converted result, as summarized in 
Table II. The six single function keys (inches -*• mm," 
"inches -* cm," "ft -* inches," "ft -* m," "yds -*■ m" 
and "miles -> km") do not need to be preceded by the 
shift key, "->/' for forward conversions. Only the X- 
register is affected by a conversion operation. 

Constant Store Key, "KS" 

The value of X is copied into the K-register. Following 
a forward conversion key, "-> f " x is multiplied by K and 
the product stored in X; following a "<-" key, X is 
divided by K, and the quotient is stored in X. 



8-60 



Decimal Point, "." 

As the first depression of a number entry, it clears the 
X-register and places a point in the leftmost digit. If the 
previous key was a number, it enters a decimal point 
to the right of the last number entered. Following a 
"+," " — ," or those keys preceding a "M + " key, the 
X-register is transferred to A, cleared and a decimal 
point entered in the leftmost digit. The last decimal 
point depression in a single number entry is accepted as 
the valid point. 



in X. Register T remains unchanged. In the chain divide 
mode, depression of "=" will divide T by X, transfer X 
to T, and place the quotient in X. If the calculator is in 
constant multiply, "=" will multiply X by T, place the 
product in X and retain T. For constant divide, the 
X-register is divided by T, the quotient is stored in X; 
T is unchanged. 

The " = " key always rounds the answer stored in X to 
two places to the right of the decimal point, and clears 
register A. 



Change Sign Key, "CS" 

Changes sign of register X. 

Addition Key, "+" 

If the previous key was not a "+" or "— " key, the number 
in the A-register is added to the X-register, X is transferred 
to A, and the sum is stored in X. When the last key was 
a "+" or "— " key, the number in A is added to the 
number in X without destroying the value of A. The 
sum is stored in X. 

Subtraction Key, "— " 

If the previous key was nota "+" or "-" key, the number 
in the X-register is subtracted from the number in the 
A-register, X is transferred to A, and the difference is 
stored in X. When the last key was a "+" or " — " key, 
the number in A is subtracted from X without destroying 
the value of A. The result is stored in X. 

Multiplication Key, "x" 

If there has not been an "x" or "^" key since the last 
terminator key ("=," "= +" or "%"), the value of the 
X-register is copied into the T-register and the calculator 
is set to the chain multiply mode. In a chain calculation 
in which there has been a "x" key since the last terminator 
or ' ,J r" key, X is multiplied by T and the resulting 
product is stored in both X and T; if a "+" key has 
occured since the last terminator or "x" key, depression 
of "x" will divide the T-register by the X-register, with 
the quotient stored in both X and T. 

Division Key, "-r" 

If there has not been an "x" or "-:■" key since the last 
terminator key ("=," "= +" or "%"), the value of the 
X-register is copied into the T-register and the calculator 
is set to the chain divide mode. In a chain calculation if a 
"x" key has occured since the last terminator or " ^" 
key, X is multiplied by T and the product is stored in 
both X and T; if a "^" key has occured since the last 
terminator or "x" key, depression of "^" will divide 
the T-register by the X-register, with the quotient stored 
in both X and T. 



Per Cent Key, "%" 

This key acts exactly like the "=" key except the value 
of X is divided by 100 and copied in register A before 
performing the required operation. The result stored in 
X is rounded to two decimal positions. 

Memory Plus Key, "M+" 

The number in the X-register is accumulated in the 
M-register. Registers X and A are not changed, so the 
repeat addition or subtraction conditions that existed 
before accumulation to memory remain valid. 

Memory Recall Key, "MR" 

The value of register M is copied into the X-register. If 
the preceding key was a "+," "-" or "M+" followed by 
"+" or "-," the value of X is transferred to the A-register 
before M is copied into it. 

Memory Clear Key, "MC" 

The (Vi-register is cleared, without affecting any other 
registers. 

Reciprocal Function, "1/x" 

If the number entry key "1" is preceded by either the 
forward or reverse conversion shift keys, "-*■" or "<-" 
a non-zero value of X is replaced by its reciprocal. 
Registers A, T, K and M are not altered. 

Square Root Function, "\/x " 

If the number entry key "2" is preceded by either the 
forward or reverse conversion shift keys, "~^" or "<- t " the 
absolute value of X is replaced by its square root. 
Registers A, T, K and M are unaltered. 

Pi-function, "v." 

If the decimal point entry key is preceded by either the 
forward or reverse conversion shift keys, "->" or "*-/' 
the value of X is replaced by the constant 3.1415927. 

Equal Plus Key "=+" 



Equal Key, "=" 

In the chain multiply mode, the value in the X-register 
is multiplied by the T-register with the product stored 



This key acts exactly like the "=" key followed by a 
"M+" key. The multiply or divide is executed the result 
is rounded to two places then the rounded result is 
added to the Memory. 



8-61 





TABLE II. Summar 


y of Key Functions 




KEY MATRIX 


PRIMARY KEY 


IF PRECEDED 


IF PRECEDED 


DESIGNATION 


FUNCTION 


BY "->•' SHIFT KEY 


BY "»" SHIFT KEY 


K1-D1 


N/C 


- 


- 


K1-D2 


Minus, "-" 


.._.. 


"-'■ 


K1-D3 


Plus, "4" 


" + " 


"4" 


K1-D4 


Divide, ■'-'■ 




"■f" 


K1-D5 


Mulriplv, "x" 


"x" 


"x" 


K1-D6 


Constant Store, "KS" 
Constant Conversion 


X ■ K -» X 


X 4K-»X 


K1-D7 


Ft -> in 


X„ • (12) -X 


X,-: (121 ^X 


K1-D8 


In -* mm 


X • (25.4) ■■> X 


X„ 4 (25.4) - X 


K1-D9 


In -* cm 


X D ■ (2.54) -» X 


X„ 4- (2.54) ^X 


K2-D1 


Mile -> km 


X ■ (1.609344) ->X 


X„ 4- (1.6093441 -> X 


K2-D2 


Ft^ m 


X ■ (0.3048) - X 


X 4- (0.3048) -» X 


K2-D3 


Forward Shift, "->" 


"-" 




K2-D4 


Memory Clear, "MC" 


"MC" 


"MC" 


K2-D5 


Yard -> m 


X„ ■ (0.9144) -> X 


X : (0.9144) -> X 


K2-D6 


Memory Plus, "M4" 
MPH -> knots 


X • (0.86836) -' X 


X D 4- (0.86836) -> X 


K2-D7 


Memory Recall, "MR" 
Imp. Gal.-> U.S. Gal. 


X • (1.20094) -> X 


X D 4- (1.20094) -> X 


K2-D8 


Clear, "C" 


"C" 


"C" 


K2--D9 


N/C 




- 


K3-D1 


N/C 






K3-D2 


Equal, "=" 
Acres -* Hectares 


X„ • (0.404687) -> X 


X :- (0.404687)^ X 


K3-D3 


Equal Plus, "'+" 
Cubic Ft --> gal 


X () • (7.4805) * X 


X„ : (7.4805) -X 


K3-D4 


Change Sign, "CS" 
Atmospheres ^ PSI 


X„ ■ (14.696) > X 


X 4 (14.696) -• X 


K3 D5 


Decimal Point, "." 


3.1415927 -> X 


3.1415927 -» X 


K3-D6 


"9" 
Oz -> cc 


X„ • (29.5737) -> X 


X - (29.5737) -> X 


K3-D7 


"8" 

Quarts -> liters 


X„ ■ (0.946333) -> X 


X :■ (0.946333) - X 


K3-D8 


"7" 

Gal -^ liters 


X„ ■ (3.785332)^ X 


X„ : (3.785332) ^X 


K3-D9 


"6" 

Lb -► oz 


X ■ (16) -> X 


X i (16) ->- X 


K4-D1 


"5" 

Oz -^ grams 


X • (28.3495)^ X 


X„ 4- (28.3495) -» X 


K4--D2 


„ 4 „ 

Lb -* kilogram 


X D ■ (0.453592)^ X 


X : (0.453592) -> X 


K4-D3 


"3" 
Stone -* lb 


X„ ■ (14) -> X 


X„ : (14) - X 


K4-D4 


"2" 

Square Root, "VX" 


\%, > X 


v'Xo * X 


K4-D5 


"1" 

Reciprocal, "1 /X" 


l/X„-» X 


1/X -* X 


K4-D6 


„ „ 
°F-*°C 


X • (9/5) t 32 -> X 


(X 32) • 5/9^ X 


K4-D7 


Reverse Shift, "< " 


„^„ 


"-" 


K4-D8 


Percent, "%" 
Acre -* Sq. ft 


X ■ (43560) -* X 


X : (43560) -4 X 



8-62 



EXAMPLES 



1. Addition and subtraction of a column of numbers: 

2.0 

3.2 

-12.3 



KEYS 


DISPLAY 


2 


2 


f 


2 


3 


3 




3 


2 


32 


■•■ 


5.2 


2 


1 2 




1 2 


3 


1 2.3 




7.1 


C 


0. 



2 + 3.2 is displayed 



12.3 is subtracted *rorr 
(2 - 3.2) 



4. Constant multiplication or division 



V 


3. 


2 


2 




6. 


4 


4 




1 2 


5 


5 




5 


2 


5.2 




1 5.6 




4 G.8 



2. Repeat add or subtract 



2 


2 




2.5 


4 


4 


= 


2. 


5 


5 




5 


2 


5.2 




2.6 


^ 


13 



2 



KEYS 


DISPLAY 


3 


3 




3 


1 


3.1 




3.1 


^ 


6.2 




9.3 


- 


6.2 


C 


0. 



3.1 is entered 

3.1 + 3.1 computed 

3.1 i 3.1 * 3.1 computed 

9.3 ■ 3.1 computed 



3. Chain multiplication or division 



KEYS 


DIS 


1 Multiplication 






1. 


2 


2 


x 


2. 


3.1 


3.1 


X 


6.2 


4.2 


4.2 


= 


26.0 4 



Division 




10 


10 


^r 


10. 


2 


2 


T 


5. 


10 


10 




.5 


2 


2 


= 


.2 5 



c} Mixed multiplication and division 

20 20 

x 20. 



10. 

7 

1.4 28 5 7 1 4 



1 x 2 is computed 
2x3! ^s computed 
6.2 *4.2 s computed 



10 ■;■ 2 is computed 
5 : 10 ;s computed 
0.5 '■ 2 s computed 



Result rounded to two 
places 



5. To perform products of sums 
(5 - 4) x (3 + 2}/{6 + 7) = 



YS 

4 

3 
2 


DISPLAY 

5 
5 
4 
9. 
9 
3 
3 
2 
5. 


COMMENTS 




4 5. 


(5 • 41 x 13 • ?l is 


6 


6 






6. 




- 


1 3. 






3 4 6 


45- 16 t 71 isexe 



6. Calculate percentage 



rounded to two places 



EYS 


DISPLAY 


COMMENTS 


3 


3 







3 







300 
3 00 




2 


3 0.2 




5 


3 0025 




X 


3 0.2 5 




5 


5 






1 5.0 1 


"Live °f." key; rot 
two places 



m 



1 . Perform add-on and discount 



KEYS 


DISPLAY 


COMMENTS 


1 Add-On 






1 


1 
1 2 




v 


1 2 5 
1 2 5. 




5 


5 






6.2 5 


5% ot 125 is displayed 




13 12 5 


125 + 5% is displayed 



863 



EXAMPLES (Continued) 
7. (Continued) 



10. (Continued) 



KEYS 


DISPLAY 


COMMEMTS 


b) Discount 






5 
3 


5 3 




2 
1 


b 3 2 
E. 3 2. 

6 3 2 1 




X 


5 3 2.1 




6 


6 




'':. 


3 1.9 3 


6% of 532.1 is displ 


- 


5 00.1 7 


532.1 6°; is displa 



Perform change sign 



EYS 


DISPLAY 


COMMENTS 


1 
2 


1 
1 2 




CS 


1 2 


Change sign does not 


3 


-12 3 
12 3. 


terminate entry. 


CS 


1 2 3. 




5 


1 2 3.5 




CS 


1 2 3.5 




6 


12 3 56 





9. Accumulate in memory, recall and clear memory 



KEYS 


DISPLAY 


COMMEMTS 


3 


3 




Mt 


3. 


Accumulate in memory 


4 


4 




Ml 


4 


Accumulate in memory 


5 


5 




MR 


7. 


Recall memory 


MC 


7. 


Clear memory 


MR 


0. 




5 


5 
5. 




G 


6 




M + 


1 1. 


Accumulate in memory 


7 


7 
1 8. 




Ml 


1 8. 


Accumulate 1 1 + 18 in rr 


+ 


2 5. 


Repeat add 


3 


3 




2 


3 2 
3 2. 




2 


3 2.2 




CS 


3 2.2 




Mr 


3 2 2 


(11 i 18) - 32.2 is accu 


9 


9 
3 4. 


n memory 


MR 


3.2 


Accumulated value of M 




3 0.8 


is recalled 


MR 


3.2 


Accumulated value of M 


MC 


-3.2 


is recalled 



10. Accumulate in memory with the "= +" key 



MC 

C 

5 



0. 
0. 
5 
5 
3 
1 5. 



4.2 
4 2 
3. 
1 2.6 



COMMENTS 



; 3 ' 15 is added to M 



4.2 x 3 = 12.6 is added t 



KEYS 


DISPLAY 


6 


6 




6. 


7 


7 


- + 


.8 6 


9 


9 


CS 


-9 


X 


-9. 


4 


4 


= a 


3 6. 


MR 


-7.5 4 



Rounded to 2 decimal places 

Note method of multiplying 
negative number 

-9x4 =-"-36 is added to M 



1 1 . Square root and reciprocal calculations. 
Find square root of 70064: 



70064 

70064. 



2(\'X) 



Either shift key could be 
used to set up \/x function 
Square root is computed 
Either shift key could be 
used to set up 1 /X function 



.00377791 Reciproc, 



12. Use of constant tt: 2m = 2(ir) (6.8) 



nputed 



KEYS 


DISPLAY 


COMMENTS 


2 


2 




X 


2 








Either shift key could be 
used to set up r. 


• M 


3.1 4 1 592 7 




X 


6.2 8 3 1 8 5 4 


2~ is computer! 


6.8 


6.8 
42.7 3 





13. Use of conversion keys: 



KEYS 


DISPLAY 


2 

n * cm 


2 
5.08 


n -• cm 


12.90 3 2 


n * cm 


32.7 7 4 12 




32.7 74 12 


n -* cm 
C 
5 


12.90 3 2 

0. 

5 

5. 



7 (gal » liters) 18.9 2 6 66 



8 (qts — liters) 20. 
125 12.5 



KS 
2 



12.5 

2 

2 

25. 



KS 


2 


C 


0. 


77 


77 




77 


= ■- CI 


25 



Two inches is converted 
to cm 

Two square inches is con- 
verted to square cm 
Two cubic inches is con- 
verted to cubic cm 
Reverse conversion mode 
is set 



Data entry is terminated 

and forward conversion 

mode is set 

Five gal. is converted to 

liters 

Last shift key is valid 

direction 

Liters ' qts computed 

Entry is stored in K 

Forward shift sets up K 

conversion 

Multiply by K 

Divide by K 

77 ( 'F is entered 

77 *F is converted to °C 



8-64 



keyboard outline 



2 
01 



in/mm intern in'ft 



t 


ft^m 


ya^m 


mi^km 


CHS 


mph'Kts 


MC 


stoK 


= + 

ft :, 'gal 


MR 

gali I ga 


ac * ft : 


ac 'nect 



gai' : i: qt' 



b'kg oz'gr cz'ID 

1 2 3 





F< C 



8-65 




Calculators 



MM5765 calculator programmer 
general description 

The MM5765 provides a convenient and inexpensive 
means of adding "learn mode" programmability to many 
National Semiconductor calculator chips. It interfaces 
directly by simply adding a single static switch, four 
dynamic keys and a mean of displaying an alarm condi- 
tion. The monolithic MOS integrated circuit combines 
P-channel enhancement and depletion mode technologies 
to obtain low voltage and low power characteristics 
necessary for economical battery-powered products. 

The MM5765 is a dynamic key sequence programmer 
that memorizes any combination of key entries while in 
the Load Mode, then automatically plays back the pro- 
grammed sequence as often as desired in the Run Mode. 
Up to 102 characters can be stored in multiprogram 
sequence blocks. Each block, or program, can be exe- 
cuted individually or the operator can make the decision 
to branch to specific programs, run each in series or 
perform intermediate calculations from the keyboard. 
When programming in the Load Mode, the Delete key 
provides a convenient editing feature and the Halt key 
programs variable data entry points where control is 
temporarily returned to the operator in the Run Mode. 
Start and Skip keys control operation in both modes. 

Synchronization with the calculator chip is accomplished 
by monitoring its Digit Output and Ready signals. The 
digit signals give timing information while the Ready 
indicates status of the calculator and synchronizes the 
key entry interface between it and the MM5765. 



Up to four switch inputs (K1, K2, K3 and K4) and up 
to twelve digit lines are connected in parallel with the 
calculator switch and digit terminals that scan the key- 
board. Keys stored in the MM5765 that are entered by 
selecting K1 through K4 are encoded simply as matrix 
positions, i.e., a particular switch input at a specific 
digit time. Therefore it is the key matrix address that is 
stored and not the key function. (Con't on page 4) 

features 

■ Many NSC calculator chips can be provided with 
programming capability with the addition of only 
one static switch and four dynamic keys. 

■ Any key sequence, including constants and date entry 
points, may be stored automatically in the Load Mode 
and executed in the Run Mode. 

■ 102 step storage capacity of up to 47 different keys 
arranged in a 12 x 4 matrix. 

■ Multiprogram capability 

■ Provision for editing in Load Mode using the Delete 
key 

■ Convenient verification of programs using a Step 
Mode feature 

■ Alarm for full storage condition— or if a deletion of 
the first step in a program is attempted 

■ Power-on clear 

■ Direct 9V battery compatibility 



block and connection diagrams 




Dual-ln-Line Package 



- LOAD/RUN MODE 

-READY 

► ALARM 



- Kb, CONTROL INPUT 




TOP VIEW 

Order Number MM5765N 

See Package 21 



8-66 



absolute maximum ratings operating voltage range 

Voltage at Any Pin Relative to V ss V ss + 0.3V to V ss - 12V V SS -6.5V < V DD < V SS -9.5V 

(All other pins connected to V ss ) 
Ambient Operating Temperature 0°C to +70°C (V ss is always the most positive supply) 
Ambient Storage Temperature -55°C to+150°C 
Lead Temperature (Soldering, 10 seconds) 300°C 


dc electrical characteristics 






PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Operating Supply Current (l DO ) 


V DD = V SS -9.5V 
T a = 25 : C 




8.0 




mA 


Keyboard Scan Input Levels 
(K1, K2, K3, K4, K5) 

Logical High Level (V lH ) 
Logical Low Level (V, L ) 


V DD = V SS -6.5V 
Vdd = V ss -9 5V 


Vss-2-5 




V ss -5.0 
Vss -6-0 


V 
V 
V 


Digit Input Levels (D2 through 012) 
Logical High Level (V IH ) 
Logical Low Level (V, L ) 


Vdd "V ss -6.5V 
Vqd " V ss 9 5V 


V 5S -2.5 




Vss-5.0 
Vss-6.0 


V 
V 
V 


Other Inputs (Ready, Run and Test) 
Logical High Level (V, H ) 
Logical Low Level IV, L ) 


V DD = V SS -6.5V 
Vdd = V SS -9.5V 


Vss-2 5 




V ss -5.0 
V ss -6.0 


V 
V 
V 


Switch Buffer Output Levels 

(K1, K2, K3, K4) 

Logical High Level (V OH | 
Logical Low Level (V Q l) 


Vdd = V ss 6.5V 
Vdd = V ss - 9.5V 


V s s-1.5 




v ss 
Vss "6.0 
V s s-7.0 


V 
V 
V 


Alarm Output Current 
Source Current 


Vout = V SS -4.5V, V DD = V ss -6.5V 
Vout = V ss 5.2V, V DD =V SS -7.25V 
Vout = V SS -7.8V, V DD = V SS -9.5V 


-5.0 


-8.0 


-20.0 


mA 
mA 
mA 


ac electrical characteristics 


PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Digit Input Time {Figure 3) 




70 






t-ts 


Word Time {Figure 3) 




0.64 






ms 


Switch Input Time {Figure 3) 




0.70 






MS 


Switch Output Time {Figure 4) 




70 






Ms 


Switch Propagation Delay Output 
{Figure 4) 






15 


26 


Ms 


Switch Output Transition Time 
{Figure 4) 


Cload = 100 pF 




2 




Ms 


Switch Input K5 Key Bounce-out 
Stability Time 

(The time a keyboard input must be 
continuously higher than the mini- 
mum Logical High Level to be ac- 
cepted as a key closure, or lower than 
the maximum Logical Low Level to 
be accepted as a key release, i.e., 6 
or 7 cycles of D2.) 




4.5 




17.0 


ms 


Key Closure Rate 

(Time between consecutive key 

outputs in Run Mode.) 






40 




ms 


Key Acceptance Rate 

(Time between consecutive key 

inputs in Load Mode.) 








47 


ms 



8-67 











— "i 


■ — — 
















In) 




(8) 






(8) 








V 

SWITCH 
INPUTS 


ss SEGMENTS 
OUT 

CALCULATOR 

DIGIT 
OUTPUTS 


V(JD 

READY 










noo....i 

U.U.U. L 

DISPLAY 


in 

J.U. 














(m) 














M 








r (mxn) 

' KEYBOARD 
I MATRIX 




lml| 




Vcc 
DIGIT DRIVER 

GND 






' 1 
1 


1 F 






' 




t 


1 








(n) 


V 

SWITCH 

1/0's 

Kb 


s DIGIT 
INPUTS 

MM5765 


READY 

ALAHM 
RUN/LOAD 
Vdd 






























* 




H 












r 


SWITC 
RUM O 


^0 

































ALARM 

INDICATOR 

LED 



POWER SWITCH 



FIGURE 2. MM5765 Programmer Connected in Low-Cost Battery Operated Calculator System 



;-«---»-; DIGIT TIME 



m. 



__T1 



r\ 



r 



DIGIT <J 
INPUT 



r\ 



K1 SWITCH I/O 

WITH 

KEY DEPRESSED 

AT K1 - D3 



-*--»—— SWITCH TIME 



-J-\ 



r 



FIGURE 3. Input Timing 



7f V 



r— h 



Kl SWtTEH 

I/O 

OUTPUT 



SWITCH PROPAGATION DELAY (OUTPUT! 



° H / SWITCH \ 

/ — — TIME — *-.\ 



S 



i i iri i i rM \y\ 1 1 i i 



Y 



~L 



;i switch . i 

OUTPUT I I LJ_I I K 



Kl 03 KEY IS 
K2SWITCH ENTERED INTO 
I/O CALCULATOR 
OUTPUT 



<1 - D3 KEY RELEASE 

TIMED OUT 

BY CALCULATOR 



I I I I I 



K2 - D3 KEY IS ENTERED K2 - 03 KEY 

INTO CALCULATOR RELEASE 



FIGURE 4. Programmer Output Timing 



TABLE I. Action of Dynamic Control Keys as a Function of The LOAD/RUN Mode 



KEY 


LOAD 


RUN 


START 


Clears and initializes program storage 


Starts program when stopped in HALT 




area. 


mode. Starts first program. 


SKIP 


Terminates current program and 


Skip remainder of current program and 




initializes a new one. 


begins execution of next one. 


HALT 


Programs an operator data entry or 
check point in RUN MODE. 




DELETE 


Erases the last key entered. (Acts as a 
backspace key.) 





general description (con't) 

Forty-seven different addresses can be stored using a 
12x4 keyboard matrix. (The illegal address is Digit 1 and 
K4.) Switch Input K5 is used to enter programming con- 
trol signals only and is not connected to the calculator in 
any way. The K5 input has key debounce protection 
identical to the calculator chip, which debounces K1 
through K4. The MM5765 does not accept a K1 , K2, K3 
or K4 input until the Ready signal from the calculator 
goes from an idle, or high state, to a low state — indicating 
the key has been debounced by the calculator. 

The program chip is dynamic, which means power must 
not be interrupted if a program is to remain stored. 
When power is applied an internal circuit automatically 
clears the MM5765, inhibiting false entries to the cal- 
culator and conditioning the system for entry of a 
new program. 



switching back to the Load Mode and entering the new 
steps. The storage register pointer always returns to 
the end of the previously entered key sequence when 
the mode is changed from Run to Load, and to the 
beginning of the first program when changed from 
Load to Run. 

"Start" Key (Refer to Table II for keyboard connections) 

The function of this dynamic key depends upon the 
position of the Load/Run Mode Control Switch: 

1. With the Mode Switch in the Load position, Start 
clears the entire program storage register of all pro- 
grams and initializes the device for accepting a new 
set of programs by setting the pointer at the first 
storage location. 



Actual storage of the sequential key information is in a 
612-bit shift register (see Figure 1). Each input char- 
acter is encoded into a six-bit word and placed in the 
I/O register. If a Ready input confirms the character has 
been accepted by the calculator as a valid key entry, or 
the internal key debounce circuit in the case of Switch 
Input K5, the new key information is transferred by 
the commutator to the storage register. It is always 
placed in sequence at the end of the existing program, 
and an internal pointer is advanced six bits. The control 
word detector keeps track of the pointer and special 
codes required for control and alarm situations. In the 
Run Mode, characters are sequentially transferred into 
the I/O register, decoded on command of the Ready 
signal and entered into the calculator via the appropriate 
Switch Input Line. 

When the MM5765 is used with calculators with long 
execution times, it may be useful to use a buffered 
Ready signal to drive a "Busy" indicator. This would 
give the user a visual feedback of status during Run 
operations. 



With the Mode Switch in the Run position, Start 
begins execution of the first program, or if pausing 
in the Halt Mode, continues the program. This key 
is not seen by the calculator and therefore has no 
affect on the calculations in progress. 



The Start key is timed out by the key bounce-out 
stability timer of the MM5765 on both key entry and 

release 



TABLE II. Control Signal Input. K5, Keyboard Matrix 



CONTROL KEY 
FUNCTION 


DIGIT TO 
K5 CONNECTION 


START 
SKIP 
DELETE 
HALT 


D5 to K5 
D6 to K5 
D7 to K5 
D8 to K5 



PROGRAMMER CONTROL FUNCTIONS 

"Load/Run" Mode Control 

This control requires a single-pole, single throw static 
switch. It prepares the MM5765 for either accepting a 
key sequence or playing it back. Its position controls 
the function of the dynamic keys as shown in Table I. 

Additional steps or programs can be appended to a 
stored key sequence even after execution simply by 



"Skip" Key 

This is the other dynamic key whose function depends 
on the position of the Load/Run Switch: 

1. In the Load Mode, this key terminates the current 
program and marks the beginning of a new program. 
Repetitious depressions will be ignored. The Delete 
key will erase this key from the storage register, but 
the Alarm will be set indicating to the user that a 



869 



complete program has been deleted. A new Skip 
will reinitiate the deleted program; otherwise, sub- 
sequent deletions or additions will be to the pre- 
vious program. 

2. In the Run Mode, if the MM5765 is at a Halt, the 
Skip key will cause the remaining steps of the 
current program to be skipped. Execution auto- 
matically begins again at the start of the next program 
and continues to the first programmed Halt; in the 
absence of a Halt, execution will continue to the 
end of the program. 

Depression of this key is not seen by the calculator and 
does not affect its status. The Skip key is timed out by 
the key bounce-out stability timer of the MM5765 on 
both key entry and key release. 

"Halt" Key 

The Halt key is a dynamic key that has a function only 
in the Load Mode. It is ignored in the Run Mode. 

The Halt key is used to program a data entry pause in 
the playback of a key sequence. When a Halt occurs in 
the program sequence during operation in the Run Mode, 
the MM5765 ignores all key entries except Start or Skip. 
The calculator chip accepts all nonprogrammer keys in 
the normal manner so that constants or variables can be 
entered, or intermediate calculations can be performed. 
The operator may use the Halt as a decision making 
point where he has the option to continue the program 
in a number of ways based on an intermediate result; 
e.g., skip to another program, restart the present pro- 
gram, or even go to a co-routine in a second MM5765 
program chip. 

If the user switches to the Load Mode during a Halt, 
execution of the current program will be terminated 
and the MM5765 will be ready to store additional keys 
at the end of the last program. If the mode is then 
returned to Run, Start will begin execution at the be- 
ginning of the first program. 

The Halt key is debounced by the MM5765. 

"Delete" Key 

The Delete is another dynamic control key that functions 
only in the Load Mode and is ignored in the Run Mode. 

It provides a method of editing by erasing the end step 
of the program. It is essentially a "backspace" key. 
Multiple Deletes can be used to remove several steps 
or even complete programs, but the Alarm will be set 



if a Skip code is deleted or an attempt is made to delete 
the Start code (beginning of first program). 

The Delete key is debounced by the MM5765. 

Switch Input K5 Keyboard Bounce Protection 

The MM5765 programmer chip is designed to interface 
with most low-cost keyboards and has characteristics 
identical to the standard NSC calculator keyboard bounce 
protection circuits. 

A control key closure is sensed when Switch Input K5 is 
forced more positive than the Logical High Level speci- 
fied in the Electrical Specifications. At the instant of 
closure, an internal "Key Bounce-out and Stability 
Time" counter is started. Any significant voltage per- 
turbation occurring on the K5 input during timeout will 
reset the timer. Hence, a key is not accepted as valid 
until noise or ringing has died out and the stability time 
counter has timed-out. Noise that persists will inhibit 
key entry indefinitely. Release is timed in the same 
manner. The actual control operation is performed by 
the MM5765 after the release is validated, to differen- 
tiate the action from a calculator key. 



ALARM CONDITIONS 

An alarm condition will be indicated by the MM5765 
program chip as a Logical High Level output on pin 7. 
An alarm condition can exist due to three circumstances: 

1. All 102 storage locations in the storage register 
are full. The Alarm is reset by entering a Delete 
key or if the mode is changed to Run and any key is 
pressed. When the storage register is full, subsequent 
data keys are ignored; the existing program is not 
disturbed. 

2. An attempt is made to delete a Start key code in 
the storage register during editing of a program. 
The alarm is set and the Delete key is ignored. Any 
of the calculator keys, the Skip or Halt keys or 
moving the Mode Switch to Run and pressing any 
key will reset the Alarm. 

3. A Skip key code is deleted from the storage register 
while editing. The alarm is set and the Skip is 
deleted. Any calculator or programmer key, or 
switching to the Run Mode and pressing a key 
will reset the alarm condition. If a Skip key is not 
re-entered, new key entries will be appended to the 
previous program, and the original program being 
edited will no longer exist. 



TABLE ML Ready Signal Description 



CALCULATOR FUNCTION 


READY SIGNAL 


Idle 

Key entry and functional operation 

Key release and return to idle 


Ready is quiescently at a Logical High Level (^V ss ). 

When a key is depressed, the calculator bounce-out stability timer 
is initiated. Ready remains high until the bounce-out time is 
completed and the key is entered, at which time it changes to a 
Logical Low Level CW DD |. 

Ready remains low until key release is debounced and the 
calculator returns to the idle state. The low to high transition 
signals the return to idle. 



;-70 



TABLE IV. Mode and Alarm Truth Table 



PIN 


MODE 


LEVEL 


Load/Run Input 


RUN 
LOAD 


LOW 
HIGH 


Alarm Output 


ACTIVE 
INACTIVE 


HIGH 
LOW 



TYPICAL OPERATION 



Loading a New Program 



At power-on, the MM5765 automatically clears and 
initializes the storage register. All that is necessary to 
start programming is to switch to the Load Mode. If 
unwanted programs already exist in the storage register 
from previous operations, switching to the Load Mode 
and depressing Start will clear the memory and initialize 
a new program. 

Programming is accomplished by simply keying the 
calculator in the normal manner. The MM5765 mem- 
orizes each key in the sequence entered. It is usually 
convenient to have the calculator displaying as the pro- 
gram is entered to catch entry errors and keep track of 
progress. However, it is necessary to consciously con- 
sider the anticipated results when programming to ensure 
a meaningful display at each step. For example, wherever 
variables are to be entered in the program, the Halt 
key is used rather than any numeric value. Because the 
calculator chip does not see a Halt, the display will no 
longer be correct as the remainder of the sequence is 
loaded. One convenient way around the problem is to 
depress and hold the Halt key down while a dummy 
variable is entered into the calculator. The depressed 
Halt key will lock-out the MM5765 without affecting 
the calculator. An alternate approach would be to enter 
the Halt and the dummy variable, followed by the proper 
number of Delete keys required to erase the dummy 
variable from the storage register. Either approach re- 
sults in a valid calculator display and stored program 
during programming. 

Because the primary reason for using a key sequence 
programmer is to allow convenient recall of often used 
routines or in optimizing a particular solution by iter- 
ating a function many times with a variety of input 
variables-in other words, many iterations of a common 
sequence— it is always worth the time to spend a few 
minutes planning the best way of entering the program. 
Learning what the calculator should be displaying at 
each step of the programming can be done conveniently 
by keying the program while in the Run Mode, using 
the proper dummy variables, and jotting down inter- 
mediate results. In this manner potential calculator 
overflow conditions are caught, and subsequent Load 
Mode entry errors can be easily detected. When an 
entry error is made while programming in the Load 
Mode, use the Delete key to erase as many steps as nec- 
essary, switch back to the Run Mode and depress Start 
to correct the calculator display and return to the Load 



Mode to finish. If the program does not approach the 
102 key capacity of the MM5765, you may wish to 
simply use the calculator functions (such as Clear Entry) 
to correct the error situation even though they will be 
included in the stored program. 

When the program is correctly loaded move the Mode 
Switch to Run. The program is now ready to be 
executed. Additions can be made to the program (even 
after execution in the Run Mode) by returning to Load. 
New key entries will be automatically appended to the 
end of the existing stored sequence. By executing the 
program before returning to Load, the calculator display 
will have a valid display and be in the correct state for 
properly displaying the new key additions. In this 
manner long programs may be constructed by connecting 
together a series of short sequences which are debugged 
as you go (reducing the possibility of error and min- 
imizing confusion). 



Running a Program 

Use of a stored program requires only that the calculator 
be preconditioned, if necessary, and the Start key 
depressed while in the Run Mode. The program will 
continue to the end, or until a Halt is encountered in 
the key sequence. 

Halts act as a pause during execution to permit entry of 
variable data, manual calculation of data, or checking of 
intermediate values. They are also available as user de- 
cision points for jumping to subsequent programs and 
can provide the capability for multiprogram labeling. 
When a Halt is encountered during execution, the 
MM5765 stops making key closures and returns control 
to the keyboard. 

Upon reaching the end of a program, the internal 
pointer will return to the beginning and wait for another 
Start key. 

As discussed above, programming certain sequences can 
result in errors in the calculator chip either during load- 
ing or during execution. If an error occurs as the 
program is loaded, the MM5765 will continue to store 
key depressions as they are made-independent of the 
calculator. Such a situation exists if a calculation results 
in overflow during execution of a stored program. The 
MM5765 continues to step through the sequence com- 
pletely independent of calculator status as long as the 
Ready signal responds properly. 



Multiple Programs 

Use of the Skip key in the Load Mode codes that 
location as the beginning of a new program, just as the 
Start key is used to initialize the first program. All other 
aspects of loading the program are the same. 

When a program stops at a Halt during execution, the 
user has the option of pressing the Skip key to jump to 
the next program or the Start key if he wishes to con- 
tinue the original sequence. When control passes to the 
next program, execution begins and proceeds to the end 
of that program or until a Halt is encountered. 



8-71 



This property of automatically executing a program 
down to the first Halt provides a convenient method of 
labeling multiprograms. For example, entering a program 
with the sequence: 



Start 

1 
Halt 



Halt 
Skip 

2 
Halt 

C 



Halt 



(Load/Run = Load Mode) 

(Calculator Clear Entry) 

Desired key sequence for Program No. 1 



Desired key sequence for Program No. 2 



has stored two program sequences. In the Run Mode, 
pressing Start will display a "1", a second Start will 
execute Program 1 (or to the first internal Halt) even- 
tually stopping at the last Halt and displaying a program 
result. The operator now has the opportunity to make a 
decision. He may rerun Program 1 by using the Start 
key, or continue to Program 2 by depressing the Skip 
key. 

If he chooses Skip, a "2" will be displayed indicating 
that Program 2 has been addressed (as programmed by 
the Skip-2-Halt sequence at the beginning of Program 2 
in the Load Mode). Start will then execute Program 2 
down to its first Halt. The Program 2 result can be dis- 
played by inserting another Halt at the end of that 
sequence. If a third program has been stored in the 
MM5765, depressing Skip will move the internal pointer 
to the beginning of that program and execute it to the 
first Halt. Assuming a Skip-3-Halt sequence was used at 
the front of the program, a "3" would be displayed by 
the calculator. If the operator had wished to rerun Pro- 
gram 1, instead of advancing to Program 3, he would 
have used Start (internal pointer is initialized). Start 
(displays shows "1") and Start (program is executed). 
For a rerun of Program 2 from the last Halt of Program 
2, he would push Start (internal pointer is initialized) 
and Skip (pointer locates the top of Program 2, executes 
to first Halt and calculator displays "2"). 

Adding a Step Mode Feature 

By returning the Ready input of the MM5765 to V ss 
when the Mode Switch is in the Run Mode position, 
and depressing any of the control keys (Start, Skip, 
Halt or Delete) the program stored in the MM5765 may 
be executed and advanced one step at a time. This 
provides a convenient method of debugging programs. 

Figure 5 shows the wiring of a 2-pole, 3-position switch 
used as the Mode Switch of a Programmer/Calculator 
system with the Step Mode as an added feature. Switch- 
ing from the Load Mode to the Step Mode conditions 



PROGRAMMER . 
MODE | 
SWITCH I 



OSTEP 
O RUN 



READY SIGNAL 
_FROM 

"calculator 



FIGURE 5. Switch Wiring for Adding Step Mode 

the programmer to step through the stored program 
starting from the first entry of the first program. Start 
must be used to initiate the sequence, then any of the 
control keys can be used. Each depression of Start, Skip, 
Halt or Delete will advance the program being executed 
by the calculator one step. When a Halt is encountered 
in the program while in the Step Mode, the MM5765 
ignores all key entries except Start or Skip just as 
described in Table I. If the Mode Switch is moved to 
Step from a Halt point in the Run Mode, the program 
may be stepped from that point on by using Start or 
Skip followed by depressions of any of the control keys. 
Switching to Run from any intermediate point of a 
Run operation from that point. From a Halt, a Start or 
Skip Key must be pressed after switching to the Run 
Mode. 

PROGRAMMING EXAMPLES 

These examples assume use of the MM5738 calculator, 
which is an 8-digit, floating point, algebraic notation, 
single memory chip with constant operation. Please re- 
view the MM5738 data sheet for explanation of key- 
board notation and function capability. 

Example 1 

A problem often encountered in communications design 
is the solution of 



SinO 



With a programmer and even a simple calculator like the 
MM5738, this problem can be repetitively solved easily 
without tables. First, program the sequence for approx- 
imating sin using 



SinO: 



3 
3! 



, where 8 is expressed in radians. 



1200 -20e J + a 
120 



-, where 5! = 120 



He 2 -20) e 2 + 1201 o 

120 



I-72 



— ■ 

Example 1 


(Con't) 








KEY 




DISPLAY 


RUN/LOAD 


COMMENTS 


C 






Load 




C 







Load 


Clear calculator 


2 




2 


Load 


Dummy variable "2" for 8 is entered. 


Start 




2 


Load 


MM5765 is initialized. 


MS 




2 


Load 




X 




2 


Load 




= 




4 


Load 


is formed 


- 




4 


Load 




20 




20 


Load 




X 




- 1 6 


Load 




MR 




2 


Load 




X 




-32 


Load 




MR 




2 


Load 




+ 




-64 


Load 


(B 2 - 20) 2 is formed. 


122 




1 22 


Load 


122 is an entry error 


C 




-64 


Load 


After entering "C", operator can simply 


Delete 




-64 


Load 


continue by entering 120, or can correct 


Delete 




-64 


Load 


program sequence by deleting last four 


Delete 




-64 


Load 


keys. Result is the same, except the second 


Delete 




-64 


Load 


alternative would use less program storage. 


120 




1 2 


Load 




X 




56 


Load 




MR 




2 


Load 




+ 




1 1 2 


Load 




120 




1 20 


Load 








0.9 3 3 3 3 3 3 

7T TT 


Load 


Sin 8 for 6 = 2 radians is displayed 


Check progrc 


m by executing 


with 8 = — , — 
4 3 






3.14 




3.1 4 


Run 


Enter approximation of tt 


^ 




3.1 4 


Run 




4 




4 


Run 


tt 


= 




0.7 8 5 


Run 


6 = — , in radians 
4 


Start 




0.7 686 1 3 


Run 


TT 

V5in — displayed 


3.14 




3.1 4 


Run 


4 


+ 




3.1 4 


Run 




3 




3 


Run 


TT 


= 




1.04 66 666 


Run 


8 = — , in radians 
3 


Start 




0.8 6 6 2 8 7 


Run 


TT 

'vSin — displayed 
3 


Now we wou 


Id like to add to the same program 


the rest of the express 


on: 


S 


nfi 








Y — 


8 








KEY 




DISPLAY 


RUN/LOAD 


COMMENTS 


1 




1 


Run 


"1" is dummy variable for sin 


Halt 




1 


Load 


"Halt" is tagged onto end of existing 
program to allow readout of sin 8 
during execution 


+ 




1 


Load 




MR 




1.04 66666 


Load 




X 




0.9 554 1 4 


Load 




Halt 
1 




0.9 5 5 4 1 4 
1 


Load 
Load 


Allows for Y entry 
Dummy variable for Y 


Delete 




1 


Load 


Dummy variable is removed from program 






0.9 554 1 4 


Load 


by Delete, or Halt could have been held down 
while 1 is entered, in which case Delete would 
not be required. 



2 

(Jl 

05 



8-73 



in 
in 

5 



Example 1 


Con't) 








Problems can 


now be solved using the program 






S 

Evaluate: 0. 54- 


n(0.72) 
0.72 






KEY 




DISPLAY 


RUN/LOAD 


COMMENTS 


0.72 




0.7 2 


Run 


Enter 6 = 0.72 radians 


Start 




0.65 9 4 044 


Run 


Sin (0.72) displayed 


Start 




0.9 1 5 8 3 9 4 


Run 




.54 




0.5 4 


Run 


Enter variable Y 


Start 




0.4 9 4 5 5 3 2 


Run 
Run 


Sin(0.72) 

0.54 displayed 

0.72 


A sequence could easily h 


ave been included to convert degrees to red 


ans. 


PROGRAMMING 








As an examp 


e of a multi 


program application. 


consider an automobile salesman who needs to calculate price plus sales 


tax, down pa 


yment and monthly payment on 


new cars many times 


a day. Again assume use of the MM5738 (although 


more powerf 


ul NSC calcu 


ators could obvious 


y make the problem 


even easier). To simplify the example, assume the 


finance time 


s fixed at 36 


months and the interest rate at 12% of the 


unpaid balance. 


KEY 




DISPLAY 


RUN/LOAD 


COMMENTS 


C 






Load 




Start 
1 




1 


Load 
Load 


Clear calculator and programmer. Label 
Program No. 1 


Halt 




■j 


Load 




C 







Load 


Clear program label. 


5 




5 


Load 


Sales tax = 5%. 


% 




0.0 5 


Load 




X 




0.0 5 


Load 




Halt 




0.0 5 


Load 




100 




1 00 


Run 


Load dummy variable for car price. Switching 


MS 




1 00 


Load 


to Run is another method of entering a dummy 


+ 




5. 


Load 


variable without having to Delete. 


K= 




1 5. 


Load 




Halt 




1 05 


Load 


Program No. 1 displays price + tax amount. 


Skip 




1 05 


Load 


Initialize Program No. 1 


2 




2 


Load 




Halt 




2 


Load 


Label Program No. 2 


C 




1 05 


Load 


Clear program label. 


Halt 




1 5 


Load 


"Halt" for down payment %. 


20 




20 


Run 


Dummy down payment %. 


% 




0.2 


Load 




X 




0.2 


Load 




MR 




1 00 


Load 




= 




20 


Load 




Halt 




20 


Load 


Program No. 2 displays required down payment. 


Skip 




20 


Load 


Initialize Program No. 3. 


3 




3 


Load 




Halt 




3 


Load 


Label Program No. 3. 


C 




20 


Load 


Clear program label. 


- 




20 


Load 




MR 




1 00 


Load 




= 




-8 


Load 


Program No. 3 computes monthly 


MS 




-80 


Load 


payment from equation 


1.01 




1.0 1 


Load 




X 




1.0 1 


Load 


Monthly payment = [Total loan (1 + i/q) nq /nq] 


1.01 




1.0 1 


Load 


i = interest per year, 12% is assumed. 






1.020 1 


Load 


nq = total number of months = 36 
q ~ 12 months per year 
(1 +i/q) = 1.01 



8-74 



PROGRAMMING (CON'T) 



KEY 



X 
1.01 



K= 



X 

MR 



36 

Halt 



DISPLAY 


RUN/LOAD 


COMMENTS 


1.040604 


Load 


(1.01) 4 


1.0828566 


Load 


(1.01 ) s 


1.1 7 25784 


Load 


(1.01) 16 


1.1 725 784 


Load 




1.0 1 


Load 




1.1 84304 1 


Load 


o.oD 17 


1.1 96 1 47 1 


Load 


(1.01) 18 


1.4307678 


Load 


(1.01) 36 


1.4 307678 


Load 




80 


Load 




1 1 4.46 1 42 


Load 




36 


Load 




3.1 7 948 3 


Load 




3.1 7 9483 


Load 


Program No. 3 displays re 



2 



EXECUTION OF PROGRAM 

Salesman has potential customer for $4995.95 automobile. Bank requires 20% down. The customer wants to know 
amount of down payment and monthly payments over 3 years at 12%. 



KEY 

Start 
Start 
4995.95 
Start 
Skip 
Start 

20 
Start 
Skip 
Start 



DISPLAY 


RUN/LOAD 


COMMENTS 


1 


Run 


Program No. 1 label. 


0.0 5 


Run 


Sales tax displayed. 


499 5.9 5 


Run 


Price entered. 


524 5.74 75 


Run 


Price + tax displayed. 


2 


Run 


Program No. 2 label. 


52 4 5.7 47 5 


Run 




20 


Run 


Enter % down. 


999.1 9 


Run 


Down payment displayed. 


3 


Run 


Program No. 3 label. 


1 58.8 4 54 3 


Run 


Monthly payment displayed 



8-75 




Calculators 



MM5766 calculator programmer 
general description 



The MM5766 provides a convenient and inexpensive 
means of adding "learn mode" programmability to the 
National Semiconductor MM5758 scientific calculator 
chip. The monolithic MOS integrated circuit combines 
P-channel enhancement and depletion mode technolo- 
gies to obtain low voltage and low power characteristics 
necessary for economical battery-powered products. 

The MM5766 is a dynamic key sequence programmer 
that memorizes any combination of key entries while in 
the Load Mode, then automatically plays back the pro- 
grammed sequence as often as desired in the Run Mode. 
Up to 102 characters can be stored in multiprogram 
sequence blocks. Each block, or program, can be exe- 
cuted individually or the operator can make the decision 
to branch to specific programs, run each in series or 
perform intermediate calculations from the keyboard. 
When programming in the Load Mode, the Delete key 
provides a convenient editing feature and the Halt key 
programs variable data entry points where control is 
temporarily returned to the operator in the Run Mode. 
Start and Skip keys control operation in both modes. 

Synchronization with the calculator chip is accomplished 
by monitoring its Digit Output and Ready signals. The 
digit signals give timing information while the Ready 
indicates status of the calculator and synchronizes the 
key entry interface between it and the MM5766. 



Up to four switch inputs {K1, K2, K3 and K4) and up 
to twelve digit lines are connected in parallel with the 
calculator switch and digit terminals that scan the key- 
board. Keys stored in the MM5766 that are entered by 
selecting K1 through K4 are encoded simply as matrix 
positions, i.e., a particular switch input at a specific 
digit time. Therefore it is the key matrix address that is 
stored and not the key function. Please refer to the 
MM5765 data sheet for a detailed functional description. 

features 

■ Any key sequence, including constants and data entry 
points, may be stored automatically in the Load Mode 
and executed in the Run Mode. 

■ 102 step storage capacity of up to 47 different keys 
arranged in a 12 x 4 matrix. 

■ Multiprogram capability 

■ Provision for editing in Load Mode using the Delete 
key 

■ Convenient verification of programs using a Step 
Mode feature 

■ Alarm for full storage condition— or if a deletion of 
the first step in a program is attempted 

■ Power-on clear 



slock and 




connection 


diagr 

1 


ams 






IJI2 BIT STORAGE: REGISTER 


"«- 
















1 


' 
















CONTROL WORD 
DETECTOR 




COMMUTATOR 




10 
REGISTER 


















t 




. 


L 








I 






MAIM 
CONTROL 




ENCODER.' 
DECODER 
















I 








I/O 
TIMING 

AND 
CONTROL 


4— ►K1 
4 *K2 








INPUTS 






, 


i 










POWER 

ON 
CLEAR 




SWITCH 
I/O 








4— LOAD/RUN MODE 

■4 READY 

> ALARM 






t 






KEY 
DESOUMCE 


4 Kb, CONTROL INPUT 


FIGURE 


1 







Dual-ln-Line Package 



Order Number MM5766N 
See Package 21 



8-76 



absolute maximum ratings 

Voltage at Any Pin Relative to V ss V BS ->■ 0.3V to V ss - 12V 

(All other pins connected to V ss ) 
Ambient Operating Temperature O'C to +70"C 

Ambient Storage Temperature -55 C to M50X 

Lead Temperature (Soldering, 10 seconds) 300 C 

dc electrical characteristics 



operating voltage range 

V ss -6.5V '___ V DD 1 V ss --9.5V 

(V <.-■<.-; is always the most positive supply) 



2 

0) 
0> 



PARAMETER 



CONDITIONS 



Operating Supplv Current 
Keyboard Scan Input Levels 
IK1, K2, K3, K4I 
Logical High Level 

Logical Low Level 

K5and Digit Input Levels 
ID2 through DI2! 
Logical High Leve 

Logical Low Level 

Other Inputs (Ready, Bun and Test) 
Logical High Level 
Logical Low Level 

Switch Butter Output Levels 
SKI, K2, K3, K4) 

Logical High Level 

Logical Low Leve 

Alarm Output Current 
Source Current 



V DD = V ss -9.5V, T A = 25"C 



r V ss 7.2V 

' Vss 8.8V 

= V ss 6.5V 

V ss 9-5V 



' 2V; l lh 
8.8V: l lh 
6.5V 
9.5V 



200uA 
200uA 



V S s 2.5 
V S s 1-0 



-2.5 
4 



+ 1.0 
H.5 



v DD n.o 



V DD = V^r - 7.2V 

v dd ■■ V..,s 8.8V 

V-ju V ss 6.5V 

V DD V. :: , 9.5V. l ol - 1.5 in A 

Vn._ T V,:,s 4.5V, V Dr , -V ss 6 5V 
V oi , Vss 5.2V, V DD -- V ss '.25V 
V, n , - - Vss 7-8V, V 1)L) V bS 9 5V 



1.5 
3.0 



-5 
6.0 



Vss 6.0 
Vss -7.0 



ac electrical characteristics 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 




Digit Input Time 


1 Figure 31 




70 






f'S 




Word Time 


(Figure 3j 




0.64 






ins 




Switch Input Time 


(Figure 3( 




70 






,us 




Switch Output Time 


(Figure 4i 




70 






;js 




Switch Propagation Delay Output 


(Figure 4i 






15 


26 


fJS 


t R an 

t r 


d Switch Output Transition Time 

Switch Input K5 Key Bounce out 
Stability Tune 

(The tune a keyboard input must be 
continuously signer than the minimum 
Logical High Level to be accepter! as a 
key closure, or lower than the maximum 
Logical Low Level to be accepted as a 
key release, i.e., 6 or / cycles sf D2 1 
Ready Timing 


C LCAD 100 
(Figure 3i 


pp. (Figure 4} 


4.5 


2 


1/.0 


us 


Ir"1 










3 


5 


/•s 


«o 








0.1 






^s 


1SET 


je 






20 






(US 


<PW 


Key Closure Rate 

(Time between consecutive key outputs 

in Run Mode.) 

Key Acceptance Rate 

(Time between consecutive key inputs 

in Load Mode.) 






400 


40 


47 


(US 

ms 
ms 



8-77 



D fl D B D c D D 



Da D h D c d 
PSB86B 





!00t<> i MVW -I 



D12 D11 010 D9 DB D7 QG 05 fl4 D3 



n 



>SEGMEN 
OUTPUT: 
DSB367 £ 
DRIVER 



SEGMENT 
UTPUTSTO 

SEGMENT 



FHOM 

DS88B7 

' SEGMENT 

DRIVER 



i 

LOAD j 

-O • O V^s 



PROGRAM 
MODE 
SWITCH 



FIGURE 2. Interface of MM5766 Programmer with MM5758 Scientific Calculator 





i — DIGIT TIME 




-| D!G!T TIME 


DIGIT 2 
INPUT 


■U 


~~^S~ 


DIGIT 3 
INPUT 


"M 


\_ 


D!G!T4 

INPUT 


~ 


SWITCH TIME 


V^-iTH 
V DEPRESSED 
AT K 1 - D 3 


;M 


\_ 


READY 


1 o , ^\+ 

L 




-(/- 90'a 



FIGURE 3. Input Timing 



I SWITCH! OUTPUT 



^ r 

SWITCH L — 

— TIME Jp 

rv , ° u,p " Ti / ■■■ 



,/ Y 



-J SWITCH PROPAGATION DELAY (OUTPUT; 



I lj I I I I M \ I I I II I I I I I I I I I II I I 

J \ U I I 

I IS. I I I I y 



K1 D3KEYIS K1 D3KEY REILASE 

ENTERED IMTO TIMED OUT 

CALCULATOR BY CALCULATOR 



TT 



FIGURE 4. Programmer Output Timing 



8-79 



(0 

in 



23 



Calculators 



MM5767 slide rule calculator* 



general description features 

The single-chip MM5767 Slide Rule Calculator was ■ 

developed with the primary objective of low end- ■ 

product cost. A complete calculator as shown in Figure m 

1 requires only the MM5767, a 20 or 22 key keyboard, 
DM8864 digit driver, NSA298 LED display and a 9V 
battery with appropriate hardware. 

Keyboard decoding and key debounce circuitry, all 
clock and timing generation and 7-segment output dis- 
play encoding are included on-chip and require no 
external components. Segments can usually be driven 
directly from the MM5767, as it typically sources about " 

8.5 mA of peak current. (Note: the typical duty cycle ■ 

of each digit is 0.104; average LED segment current is 
therefore approximately 0.89 mA.) The left-most digit ■ 

is used for the negative sign or the decimal point of a m 

number less than unity. m 

An internal power-on clear circuit clears all registers, ■ 

including the memory, when V DD and V ss are initially 
applied to the chip. 

■ 
Trailing zero suppression allows convenient reading of 
the left justified display, and conserves power. The 
DM8864 digit driver is capable of sensing a low battery 
voltage and providing a signal during Digit 9 time that 
can be used to turn on one of the segments as an " 

indicator. ■ 

*Note: For detailed information on electrical specifications and key operati 



20 or 22 key keyboard 

Full 8-digit entry and display capacity 

Complete electronic slide rule capability 

• Arithmetic functions: +, — x, ^, \fx, 1/x 

• Logarithmic functions: In x, log x, e x 

• Trigonometric functions: sin x, cos x, tan x, arc 
sin x, arc cos x, arc tan x 

• Other functions: Y x , tt, change sign, exchange, 
radians to degrees, degrees to radians 

Three-register operational stack 

Independent accumulating storage register with store, 

recall, memory plus and memory minus functions 

Floating point input and output 

Direct 9V battery compatibility; low power dissipation 

Power-on clear 

No external components required other than display 

digit driver, keyboard and LED display for complete 

calculator 

Error indication for over range, overflow and invalid 

operations 

Left justified entry and results with trailing zero 

suppression 

Automatic display cutoff 

Reverse polish notation 

ons please refer to the MM5760 data sheet. 



connection diagram 



keyboard outline 



Dual-ln-Line Package 



DIGIT 3 




24 
— DIGIT4 


DIGIT 2 — 




23 
DIGIT 5 


DIGIT 1-2- 




22 
DIGIT 6 




4 
K 4 




21 
DIGIT 7 


NITCH 


K3 




DIGITS 


UP UTS 


6 
NC 




— DIGITS 




7 
L K1 




18 
READY 


»„-i 




17 
-—SEGMENT 


9 
SEGMENT G 




16 
— SEGMENT E 


SEGMENT B 




15 
SEGMENT A 


SEGMENT F — 




14 
— DECIMAL POINT 




v^ 




13 
SEGMENT C 



r 




00 


[ t, | ( MS ] f 1/x | f x - • V | 
I F II MR II CHS II ENT 


COS" 1 
I 7 


SIN" 1 


TAN" 1 --> R 
9 


[ COS 

I 4 

[ LOG 

LlJ 

LN 



[ SIN 






f TAN |[r • d] 
I ' ll X I 

00 
00 



TOP VIEW 

Order Number MM5767N 

See Package 22 



•Optional 



8-80 



Typical current drain of a complete calculator displaying 
five "5's" is 30 mA. Automatic display cutoff is 
included. If no key closure occurs for approximately 
35 seconds, all numbers are blanked and all decimal 
points displayed. 

The keys are arranged in a three-by-nine matrix (Figure 
2). In addition to seven arithmetic functions plus loga- 
rithmic, trigonometric and accumulating memory 
functions, the calculator Js capable of calculating Y x , 
automatically entering -n and providing degrees/radian 
converions. 



The user has access to four registers designated X, Y, Z 
and M. X is the display and entry register, and is the 
bottom of a "push-up" stack that also includes registers 
Y and Z: 



Z 
Y 
X 



2 



Note: Lower case letters designate the data in the register 
identified by a capital letter. 



Sj Sh Sc Sri Sh !if Sg QP 
I MM57G7 

I Dl 02 03 04 Ob D6 [ 1 D8 D9 



/_/. /_/. /_/. o. /_/. /_/. /-/. /_/. /-/. 



09 08 07 D6 



D4 D3 D2 D1 



FIGURE 1. Complete Calculator Schematic 





K1 


K3 


K4 


D9 




TAN/6 




D8 




COS 1 /7 


ff/F 


D7 


R - * D/x 


SII\T 1 /8 


D* 


D6 


D -> R/^ 


TAN V9 


LN/0 


D5 


Mt/+ 


V '""/• 


Log/1 


D4 


m-; 


EXC/EN 


Y x /2 


D3 


CLF/CL 


MS/MR 


e"/3 


D2 


CA* 


1/x /CS 


COS/4 


D1 






SIN/5 



OR 

T_ EOUIV. 



m 



"Keys not included in 20 key \. 



FIGURE 2. Keyboard Matrix 



KEYBOARD BOUNCE AND NOISE REJECTION 

The MM5767 is designed to interface with most low cost 
keyboards, which are often the least desirable from a 
false or multiple entry standpoint. 



segments and display nine decimal points. Any key de- 
pression will restore the display; to restore the display 
without modifying the status of the calculator, use two 
change sign, "CS," depressions. 

READY SIGNAL OPERATION 



A key closure is sensed by the calculator chip when 
one of the key inputs, K1, K3 or K4 is forced more 
positive than the Logical High Level specified in the Elec- 
trical Specifications. An internal counter is started as a 
result of the closure. The key operation begins after nine 
word times if the key input is still at a Logical High Level. 
As long as the key is held down (and the key input re- 
mains high) no further entry is allowed. When the key 
input changes to a Logical Low Level, the internal counter 
starts a sixteen word time-out for key release. During 
both entry and release time-outs the key inputs are 
sampled approximately every other word time for valid 
levels. If they are found invalid, the counter is reset and 
the calculator assumes the last valid key input state. 

One of the popular types of low-cost keyboards avail- 
able, the eiastomeric conductor type, has a key pressure 
versus contact resistance characteristic that can generate 
continuous noise during "teasing" or low pressure key 
depressions. The MM5767 recognizes a series contact re- 
sistance up to 50 kfl as a valid key closure, assuring a 
reliable interface for that type of keyboard. 

AUTOMATIC DISPLAY CUTOFF 

If no key is depressed for approximately 35 seconds, an 
internal automatic display cutoff circuit will blank all 



The Ready signal indicates calculator status. When the 
calculator is in an "idle" state the output is at a Logical 
High Level (near V ss ). When a key is closed, the internal 
key entry timer is started. Ready remains high until the 
time-out is completed and the key entry is accepted as 
valid, then goes low as indicated in Figures 3 and 4. It 
remains at a Logical Low Level until the function initiated 
by the key is completed and the key is released. The low 
to high transition indicates the calculator has returned to 
an idle state and a new key can be entered. 

ERROR INDICATION 

In the event of an operating error, the MM5767 will 
display all zeros and all decimal points. In addition to 
normal calculator overflow situations which occur as a 
result of adding, subtracting, multiplying or dividing and 
including division by zero, the error indication is dis- 
played for any other calculation where the result is 
IR I > 99999999 or |R I < 0.00000001 . 

For error conditions the Z-register is automatically 
cleared and the Y- and M-registers are saved. An error 
condition is cleared by depressing any key except 
"1/X," "H-," "LOG X" or "LN X." Operation on the 
X register with an error displayed will be performed as 
if X contained a zero. 



■v 



^n 



NEW 

KEY IS 

DEPRESSED 



FIGURE 3. Ready Timing 



ANY 

SWITCH 

INPUT 



JUULJLi 



Ib'WOROS AFTER 

KEY RELEASE OR 

AFTER CALCULATION 

IS COMPLETE, 

WHICHEVER IS 

LONGER. 



r 



NEW KEY HAS 
BEEN ACCEPTED 
BY CALCULATOR 
THE KEY MAY 
BE RELEASED 



NEXT KEY 

CAN BE 
ENTERED. 



FIGURE 4. Functional Description of Ready Signal and Key Entry 



8-82 



RANGE AND ACCURACY OF FUNCTIONS 

The smallest magnitude that can be displayed is 
±0.00000001 and the total range is from -99999999 to 
+99999999. The arithmetic functions ( + , -, x, +, 1/X, 



\/X) have eight digit accuracy. All results are truncated. 
Table I summarizes range and accuracy of the other 
functions. Arithmetic calculations will be completed in 
less than 0.5 second; all others except Y x in less than 
2.5 seconds and Y* in less than 5 seconds. 



TABLE I. Digit Accuracy for Various Functions 



FUNCTION 


RANGE 


APPROXIMATE 
ACCURACY (Note 1) 


SIN, COS, TAN 


■v -90° to "V 90° 


7 Digits 




"v -360" to -v 360 J 


6 Digits 


ARC SIN and ARC COS 


■^ -1 to "v +1 


6 Digits 


ARC TAN 


-99999999 to 99999999 


6 Digits 


LOG 


X>0 


6 Digits 


e* 


28 < X< {n 99999999 


6 Digits 


LN 


X>0 


6 Digits 


v^ 


X>0 


8 Digits 


Y x 


Y>0 

X tin Y < tn 99999999 


5 Digits 



Note 1: Six digit accuracy, as an example, would be: 
1 2 3 4 5 6 X X 



■ ±1 



th 



n digit accuracy has the n digit from the MSD being displayed accurate within ± 1 . 



883 



in 



a 



Calculators 



MM5777 calculator 6 -dig it, 4-function, floating decimal point 



general description 

The MM5777 single-chip calculator was developed using 
a metal gate, P-channel, enhancement and depletion 
mode MOS process with low end-product cost as the 
primary objective. A complete calculator, as shown in 
Figure 1, requires only a keyboard, DS8977 digit driver, 
6 1/4 digit LED display, an NSA1161 and a 9V battery 
with appropriate hardware. 

Keyboard decoding and key debounce circuitry, all 
clock and timing generation and output 7-segment dis 
play decoding are all included on-chip and require no 
external discrete components. LED segments can be 
driven directly from the MM5777 as it typically sources 
8.0 mA of peak current. [Note: The typical duty cycle 
of each digit is 0.143; average LED segment current is 
therefore approximately 0.143 (8.0 mA), or 1.14 mA. 
Correspondingly, the worst-case average segment current 
is 0.143 (4.5 mA), or 0.64 mA.] The seventh digit is 
used for the negative sign of a six digit number and as an 
error indicator. Negative results less than six digits will 
have the negative sign displayed one digit to the left of 
the most-significant-digit (MSD). The DS8977 digit 
driver is capable of indicating a low battery voltage con- 
dition by turning on a seventh digit segment— which does 
not hinder the actual calculator operation. 

Leading and trailing zero suppression allows convenient 
reading of the right justified display and conserves 
power. Battery life is estimated to be 10 to 20 hours, 
depending on battery quality, operating schedule and 
the average number of digits displayed. 



connection diagram 

Dual-ln-Line Package 




N/C 

KEY INPUT 3 (K3) 

KEY INPUT 2 1KZ) 

KEY INPUT 1 (Kl) 

SEGMENT e 

SEGMENTa 



The Ready output signal is used to indicate when the 
calculator is performing an operation (Table I). It is 
useful in testing of the device or when the MM5777 is 
used as part of a larger system and is required to inter- 
face with other logic. (Another feature that is important 
in such applications is the ability to reduce the key 
debounce time from seven word times to four word times 
by forcing the Digit 6 output high during Digit 7 time.) 

features 

■ 6-digit entry and display capacity for positive and 
negative numbers 

■ Four functions (+, -, x, -4-) 

■ Floating negative sign indicator is always displayed 
one digit to left of MSD 

■ Convenient algebraic key entry notation 

■ Floating point input and output 

■ Chain operations 

■ Direct 9V battery compatibility; low power 

■ Direct interface to LED segments 

■ No external components are required other than 
display digit driver, keyboard and LED display for 
complete calculator 

■ Overflow and divide-by-zero error indication 

■ Right justified entry and results, with leading and 
trailing zero suppression 



keyboard outline 



TOP VIEW 

Order Number MM5777N 
See Package 22 







0N> 






□ 


7 8 

CZ3 CD 


9 

CD \ZJ 


4 5 

CD CD 


6 

CD CD 


1 2 

CD CZ3 


3 + 

CD CD 


CE/C 


CD CD 



absolute maximum ratings 

Voltage at Any Pin Relative to V ss . (All 

other pins connected to V ss ). \ 

Ambient Operating Temperature 

Ambient Storage Temperature 

Lead Temperature (Soldering, 10 seconds) 

operating voltage range 

6.5V < V ss - V DD <9.5V 

(V ss always defined as most positive supply voltage.) 

dc electrical characteristics 



+ 0.3V to V ss - 12.0 

0°C to +70°C 

-55°C to+150°C 

300° C 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Operating Supply Current ( I DD ) 


V DD - V ss 9.5V 
T A = 25'C 




8.0 


14.0 


mA 


Keyboard Scan Input Levels 












(K1, K2 and K3I 












Logical High Level (V, H ) 


V SS -6.5V< V DD <V SS -9.5V 


V ss -2.5 






V 


Logical Low Level (V ]L ) 


Vod =V SS -6.5V 






Vss -5.0 


V 




Vdd = V SS -9.5V 






V S s "6.0 


V 


Digit Output Levels {Note 1} 












Logical High Level (V 0H ) 


V ss -6.5V<V DD <V SS 9.5V 


V S s-1.5 






V 


Logical Low Level (V OL | 


Vod = V ss -6.5V 






V ss -6.0 


V 




Vod = V ss H3.5V 






V ss -7.0 


V 


Segment Output Current 












(Sa through Sg and Decimal Point) 


T fl = 25'C 












Vout = V ss -3.8V, V DD = V ss -6.5V 


-5.0 


-8.0 




mA 




Vout = V ss -5.0V, V DO = V ss -8.0V 




10.0 




mA 




Vout = V S s -6.5V, V DD = V ss -9.5V 






-15.0 


mA 


Ready Output Levels 












Logical High Level (V OH ) 


Iout = ~0-4 mA 


V ss -1.0 






V 


Logical Low Level (V OL ) 


I out = 10mA 






V DD + 1.0 


V 



Note 1: With digit connected through key to K-line and to DS8977. 

ac electrical characteristics 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Word Time (Figure 21 




0.50 


1.20 


4.1 


ms 


Digit Time (Figure 21 




70 


170 


580 


MS 


Interdigit Blanking Time (Figure 2} 






4 




MS 


Digit Output Transition Times 
(tmsE and t FALL ) 


Cload = 100 pF 




2 




Ms 


Keyboard Inputs High to Low 
Transition Time After 
Key Release 


Cload = 100 pF 




4 




MS 


Ready Output Propagation Time 

(Figure 31 

Low to High Level (t PDH ) 
High to Low Level (t PDL ) 


Cload = 100 pF 
Cload = 100 pF 


60 
0.06 


140 
0.5 


480 
1.5 


Ms 
ms 


Key Bounce-out Stability Time 
(The time a keyboard input must be 
continuously higher than the 
minimum logical high level to be 
accepted as a key closure, or con- 
tinuously lower than the maximum 
logical low level to be accepted as a 
key release.) 




3.40 


8.20 


29.0 


ms 


Calculation Time for 
999999 v 1 = 999999 




53.9 


128.7 


451 


ms 



2 

Ul 



8-85 



1^ 
in 




Sa Sb Sc Sd Se Sf Sg tip 

MM5777 
02 D3 04 05 D6 D7 



/_ o a o o a o 
.u.u.u.u.u.u. 



1 



I" 

POWER \ 
SWITCH \ 



CALCULATOR CHIP 



DISPLAY DRIVER 



FIGURE 1. Complete Calculator Schematic 



TABLE I. Ready Signal Description 



CALCULATOR FUNCTION 


READY SIGNAL 


Idle 

Key Entry and Functional Operation 

Key Release and Return to Idle 


READY is quiescently at a Logical High Level (^V ss ). 

When a key is depressed, the bounce-out stability timer is initiated. 
READY remains high until the bounce-out time is completed and the 
key is entered, at which time it changes to a Logical Low Level (^V DD ). 

READY remains low until key release is debounced and the calculator 
returns to the idle state. The low to high transition signals the return to 
idle. (The display may lag the READY by up to eight word times.) 



KEY INPUT BOUNCE AND NOISE REJECTION 



The MM5777 calculator chip is designed to interface 
with low cost keyboards, which are often the least 
desirable from a noise and false entry standpoint. 

A key closure is sensed by the calculator chip when one 
of the Key Input Lines, K1, K2 or K3 is forced more 
positive than the Logical High Level specified in the Elec- 
trical Specifications. At the instant of closure, an internal 
"Key Bounce-out Stability Time" counter is started. 
Any significant voltage perturbation occurring on the 
switched key input during timeout will reset the timer. 
Hence, a key is not accepted as a valid entry until noise 



or ringing has stopped and the stability time counter has 
timed out. Noise that persists will inhibit key entry 
indefinitely. Key release is timed in the same manner. 

One of the popular types of low cost keyboards 
available, the elastomeric conductor type, has a key 
pressure versus contact resistance characteristic that can 
generate continuous noise during "teasing" or low pres- 
sure key depressions. The MM 5777 defines a series 
contact resistance up to 50 kfi as a valid key closure, 
providing an optimum interface to that type of keyboard 
as well as more conventional types. 



i-86 



ERROR CONDITIONS 

!n the event of an overflow, the MM5777 will indicate 
error in the leftmost digit and at least five of the signifi- 
cant digits of the answer. Division by zero results in an 
error indication with six trailing zeros. Once in an error 
condition, all keys except the clear key are ignored. 
When used with the NSA1 161 display, segments f and g 
will be displayed in the seventh digit tn an error 
condition. 

KEY OPERATIONS 
Clear Key 

Operation after a number entry clears the entry and 
d'splays a previous result. Second depression clears all 
registers and displays a zero without decimal point in 
the LSD. Operation after a function key ( + , ~, x, : or ^) 
clears all registers and displays a zero without decimal 
point. Two depressions are always required after power 
is applied. 

Number Entries 

First, entry clears the display register and enters the 
number into the least significant digit (LSD) of the 
display register. Second through sixth entry shifts the 
display register left one digit and enters the number into 
the LSD. The seventh, and subsequent entries, are 
ignored and no error condition is generated. Because 
only five positions are allowed to follow the decimal 
point, the sixth and subsequent entries after a decimal 
point entry are ignored. 



Decimal Point 

First depression of this key in a number entry will enter 
a decimal point in the LSD position of the display 
register. Subsequent depressions of the decimal point 
key before any function key will be ignored. 

Add, Subtract, Multiply or Divide Keys 

First depression after a number entry will terminate the 
entry, perform the previously recorded operation, if 
any, and record the function key depressed as the next 
operation to be performed after another number entry. 
Subsequent depressions of any function key, without an 
interceding number or decimal point entry will supersede 
the previous function as the next to be performed. After 
an equal key, the displayed result of the equai operation 
will be re-entered and the function key depressed will 
become the next operation to be performed after a 
number entry is followed by another function key 
(including equai). 

Equal 



First depression after a number entry will terminate the 
entry, perform the previously recorded operation and 
record the fact that an equal key has been depressed. 
Depression after the add, subtract or divide keys, with- 
out an interceding number or decimal point entry, will 
be ignored. After a multiply key, the number being 
displayed will be squared. 



DIGIT 

OUTPUTS 

0, 




_J 


.... WQRD T | ME 

— INTERDIGIT BLANKING TIME 


















i 








-— Dl 


IT TIM 


















02 




I; 






I 




















03 


i 


I 




| 




• j 


i 






















07 | 




I 




L 






























DECIMAL POINT \ 


I 








SEGMENTS 






















..- 
















I 










! 










Sb 




































Sc 






I 










I 
























Sd 
















I 


J 
















| 




Se ; 




I 




i 


























_ 

Sg 

AC 
DIS 












i 
























02 

r 
u 


iz /. 

_/ 


D3 

_/ 
/ 


04 

Zl Zl 1 
_/./_ 1 


D5 
D1 


D6 


i 




Dl 
TUAL 
LAY: 


07 




D7 
DE 


S 
SIG 


Dl 

GMEMT 
NATIOrii 


i/7"/b 



FIGURE 2. Display Timing Diagram 



3-87 




















DIGIT 7 


_J 


L 


~1_ 


.. 1 


L \ 










DIGIT 1 








r 


\ 






Vs. 
READY 








/ 


> j. 








— 


'pdl 


<VoL 


— »-l 
\ 


i— t™ 






10%^ 


»i 9K 










FIGURE 3. Ready Output Timing 




sample problems 














1. Single Calculations 














5 x 3.14 = 15.7 














Key 








Display 


Comments 




C 










Two clears are required after power-up. 




C 















5 








5 






X 








5 






3 

1 








3 

3. 

3 1 






4 








3 1 4 






J 








1 5 7 






II. Chain Calculations 














A. 23.37 + 243.00 489.16 


-222.79 








Key 








Display 


Comments 




C 














c 















23.37 








2 3.3 7 






+ 








2 3.3 7 






243 








2 4 3 






X 








2 6 6 3 7 


Function key completes previously recorded " 4 


" operation. 


(Wrong Function Key) 














- 








2 6 6 3 7 


Wrong "X" function key is updated to "- ." 




489.17 








4 8 9.1 7 






C 








2 6 6.3 7 






489.16 








4 8 9.1 6 
2 2 2 7 9 


Number entry error is cleared and corrected. N( 
floating negative sign. 


te the 


B. Find square root of 169 usinc 


a n 


lodified Newton app 


oximation method. Let N represent the squared ru 


mher and X 


the initial estimate The f 


rst 


aPF 


roximation, X , , is 






X, - |N/X * X > 


2 












If X is 15, 














X, = (169/15 f 15) 


2 












X 2 - (169/X, * X, 


)/2 












X 3 - (169/X 2 * X 2 


1/2 


etc 










Key 








Display 


Comments 




C 














C 















169 








1 69 
1 69 






15 








1 5 






+ 








1 12 666 






15 








1 5 






+ 








26.2 66 6 






2 








2 






--- 








13 13 3 3 


Result is X, 




169 








1 69 
1 69 






13 13 








1 3.1 3 


Four digits are conveniently remembered 





sample problems (con't) 

II. Chain Calculations (continued) 
Key 

13.13 
2 



III. Auto Squaring 

A 5.25^=27 5625 

Key 

C 

C 

5.25 

B. 5.25 5 -= 3988 37 

Key 

C 

C 

5.25 



Display 

12 8 7 12 

1 3.1 3 

2 600 12 

2 

13000 6 



Display 




5.2 5 
5.2 5 

2 7.5 62 5 



Display 





5.2 5 

5.2 5 

2 7.5 62 5 

2 7.5 62 5 

7 5 9.6 9 1 

7 5 9.6 9 1 

5.2 5 

39 88.3 7 



2 



Result is X 2 , which is usually adequate If more 
accuracy is required, continue the iteration. 



Number in display register is squared 



Auto square = 5.25" 
Auto square = 5.25 4 

Result is 5.25 b 



01 



8-89 




Calculators 



MM5780 educational toy calculator 
general description 

The MM5780 single-chip, educational calculator was 
developed using a metal gate, P-channel, enhancement 
and depletion mode MOS process. It was designed with 
low end-product cost as the primary objective and is 
directed toward the educational toy market. Besides the 
MM5780, a complete calculator, as shown in Figure 1 , 
requires only a keyboard, "Right" and "Wrong" LED 
display, a 9V battery and an on/off switch. Keyboard 
encoding and key debounce circuitry, all clock and 
timing generation and the capability to drive the two 
LEDs are all included on-chip and require no external 
discrete components. 

The MM5780 educational calculator was designed to be 
a mathematical aid to school age children. Problems are 
entered into the machine in algebraic form exactly as 
they are written across a printed page. The student 
provides the answer or missing factor and when finished, 
depresses the Test key. "Right" and "Wrong" outputs 
provide an indication of the results of the test. If wrong, 
the student trys the problem again. If correct, he can 
move on to the next problem. Most problems using +, 
-, x and -4- can be learned using this machine. The 
calculator does not have provisions for remainders in 
division or negative number entries. A negative result 
can be entered before the Test key is depressed. 

The MM5780 is a low power device which operates 
directly from a 9V battery. Battery life is estimated to 
be 10 to 30 hours depending on battery quality and 
operating schedule. 



When the battery voltage falls below an operational 
level, an internal circuit will disable both indicator 
outputs; i.e., neither indicator will be on after depression 
of Test. 

The Ready output signal is used to indicate when the 
calculator is performing an operation. It is useful in 
testing of the device or if interfacing with other logic. 
Another feature that is important in testing is the 
capability of reducing the key debounce time from seven 
word times to four word times by forcing the Digit 7 
output high during Digit 9 time. 



features 

■ Full 8-digit entry capacity 
* Four functions {+, ~, x, -r) 

■ Convenient algebraic key entry notation 

■ Floating point input and output 

■ Chain operations 

■ Direct 9V battery compatibility; low power 

■ Direct interface to LED indicators 

■ No external components required other than keyboard 
and LED display for complete educational calculator 

■ Overflow and divide-by-zero error indication 

■ Low battery voltage sensing 



connection diagram 



Dual-ln-Line Package 



- DIGITS 

- DIGIT 5 



-KEY INPUT 3 (K3) 



-KEY INPUT 2 (K2j 



^6_ WRONG ' 
INDICATOR 

^_ RIGHT' 
INDICATOR 



Order Number MM5780IM 
See Package 22 



8-90 



absolute maximum ratings 

Voltage at Any Pin Relative to V ss . (All 
other pins connected to V ss .} 
Ambient Operating Temperature 
Ambient Storage Temperature 
Lead Temperature (Soldering, 10 seconds) 



V ss + 0.3V to V ss - 12.0 

0°C to +70° C 

-55° C to+150°C 

300°C 



2 
2 

00 

o 



operating voltage range (Notei) 

6.5V <V SS -V DD <9.5V 

(V ss is always defined as the most positive supply voltage.) 



dc electrical characteristics 



PARAMETER 



CONDITIONS 



MIN 



TYP 



MAX 



UNITS 



Operating Supply Current (Idd ) 

Keyboard Scan Input Levels 

(K1, K2 and K3) 

Logical High Level (V, H ) 
Logical Low Level (V jL ) 



Digit Output Levels (Note 1 ) 
Logical High Level (V OH ) 
Logical Low Level (V i_) 

Indicator Output Current 
Source Current 



Ready Output Levels 

Logical High Level (V OH ) 
Logical Low Level (V OL ) 



= V, S -9.5V, T fl = 25 C 



V SS -6.5V < V DD < V SS -9.5V 
V~dd = V SS -6.5V 
Vod = V SS -9.5V 

V SS -6.5V<V DD <V SS -9.5V 
V DD = V SE -6.5V 
Vdd = V ss -9.5V 

T A = 25°C 

Vout = V ss -4.5, V DD = V SS -6.5V 

Vn, it = V^-4.8, V nn = V«-9.5V 



l OUT = -0.4 mA 
l OUT = 10uA 



-2.5 



-1.5 



-10.0 



-1.0 



-15.0 
-25.0 



14.0 



V ss -5.0 
Vo S -6.0 



Vss "SO 
V ss -7.0 



-32.0 



Vno + 10 



mA 



V 
V 
V 

V 
V 
V 



mA 
mA 



ac electrical characteristics [Figure 2) 



PARAMETER 



CONDITIONS 



TYP 



MAX 



Digit Time 

Keyboard Input (K1, K2, K3) 
High to Low Transition 
Time After Key Release 

Ready Propagation Time 
Low to High Level (t PDH ) 
High to Low Level ft PDL } 

Key Bounce-out Stability Time 
(The time a keyboard input must 
be continuously higher than the 
minimum logical high level to be 
accepted as a key closure, or 
continuously lower than the max- 
imum logical low level to be 
accepted as a key release.) 

Calculation Time for 
99999999 > 1 = 99999999 



Cload = 100 pF 



Cload = 100 pF 



0.6 
70 



60 



4.2 



1.5 
170 
4 



140 
0.5 

10.5 



5.2 
580 



480 
1.5 

35.0 



765 



/"s 

MS 



MS 
ms 



Notel: The internal low battery voltage sensing circuit will disable both indicator outputs when Vss-Vqq falls below a safe operating 
voltage. That voltage may be less than or greater than 6,5V depending on process variables; the MM5780 will have been tested to operate correctly 
for any voltage less than 9.5V at which an indicator output is enabled. 



8-91 



o 

00 

in 

2 



<^_ 



<v 



<V. 



<v 



<v_ 



<Vs. 



<V. 




^ 



S.^ 



^ **- 



(1 V ss RIGHT WRONG 

^ MM578Q v d 

D1 D2 03 04 D5 06 07 08 D 



^- 



S- 



**- 



^>*- 



-2^. 



^- 



6 24 23 22 21 20 2 



FIGURE 1. Complete Calculator 



\ 



— -INTERNAL DELAY 



T^A. 



v 



_/TA. 



—■—-DIGIT TIME- 



^TA. 



FIGURE 2. Output Timing 



KEY INPUT BOUNCE AND NOISE REJECTION 



The MM5780 calculator chip is designed to interface 
with low cost keyboards, which are often the least 
desirable from a noise and false entry standpoint. 

A key closure is sensed by the calculator chip when one 
of the Key Input Lines, K1, K2 or K3 are forced more 
positive than the Logical High Level specified in the Elec- 
trical Specifications. At the instant of closure, an internal 
"Key Bounce-out Stability Time" counter is started. 
Any significant voltage perturbation occurring on the 
switched key input during timeout will reset the timer. 
Hence, a key is not accepted as a valid entry until noise 



or ringing has stopped and the stability time counter has 
timed out. Noise that persists will inhibit key entry 
indefinitely. Key release is timed in the same manner. 

One of the popular types of low cost keyboards 
available, the elastomeric conductor type, has a key 
pressure versus contact resistance characteristic that can 
generate continuous noise during "teasing" or low pres- 
sure key depressions. The MM5780 defines a series 
contact resistance up to 50 k£2 as a valid key closure, 
providing an optimum interface to that type of keyboard 
as well as more conventional types. 



892 



Error Conditions 

In the event of an overflow or divide-by-zero the 
"Wrong" light will come on and remain on until a 
Clear key is depressed. Normally the indicator lights are 
activated only after depression of the TEST key. 

KEY OPERATIONS 
Clear Key 

The Clear key clears all registers to zero and places the 
machine in an idle state. 

Number Entries 

First entry clears the entry register and enters the 
number into the least significant digit (LSD) of the 
entry register and extinguishes the indicator lights. 
Second through eighth entry shifts the entry register 
left one digit and enters the number into the LSD. The 
ninth and subsequent entries, are ignored and no error 
condition is generated. Because only seven positions 
are allowed to follow the decimal point, the eighth and 
subsequent entries after a decimal point entry are ignored. 

Decimal Point 

Depression results in a decimal point entry into the 
entry register. 



Subsequent depressions of any function key, without an 
interceding number or decimal point entry will supersede 
the previous function as the next to be performed. If a 
function key is depressed after an equal key, the result 
of the operation will be re-entered and the function key 
depressed will become the next operation to be per- 
formed after a number entry is followed by another 
function key (including equal). 

Equal 

First depression after a number entry will terminate the 
entry, perform the previously recorded operation and 
record the fact that an equal key has been depressed. 
Depression after the add, subtract or divide keys, with- 
out an interceding number or decimal point entry, will 
be ignored. After a multiply key, the number in the 
entry register will be squared. 

Resultant Entries 

Results are entered as number entries after an equal key 
and before the Test key. Results are assumed positive 
and a plus key should not be entered prior to the 
resultant. Negative results must be preceded by a minus 
key. 

Test 



Add, Subtract, Multiply or Divide Keys 

First depression after a number entry will terminate the 
entry, perform the previously recorded operation, if 
any, and record the function key depressed as the next 
operation to be performed after another number entry. 



The Test key is used to terminate computations and 
to initiate a test of the student's answer versus the 
calculator's answer. If the answers match, the "Right" 
indicator is enabled, otherwise the "Wrong" indicator is 
enabled. If the results are incorrect the problem must be 
worked again from the beginning. 



TABLE I. Ready Signal Description 



CALCULATOR FUMCTION 


READY SIGNAL 


Idle 


READY is quiescently at a Logical High Level ('W ss ). 


Key Entry and Functional Operation 


When a key is depressed, the bounce-out stability timer is initiated. 
READY remains high until the bounce-out time is completed and the 
key is entered, at which time it changes to a Logical Low Level {'\'V DD ). 


Key Release and Return to Idle 


READY remains low until key release is debounced and the calculator 
returns to the idle state. The low to high transition signals the return 
to idle. 



TABLE II. Indicator Truth Table 



CALCULATOR CONDITION 


INDICATOR OUTPUT 


PIN IS 


PIN 16 


Test was last key depressed with correct answer entered. 


HIGH 


LOW 


Test was last key depressed with incorrect answer 
entered or the problem has resulted in an error or 
overflow condition. 


LOW 


HIGH 


Any key other than Test was last depressed and 
calculator is not in an error or overflow condition. 


LOW 


LOW 


Clear was last key depressed. 


LOW 


LOW 


The battery supply voltage has fallen below a valid 
operating voltage for the MM5780. Independent of 
keys depressed. 


LOW 


LOW 



8-93 



o 

00 

in 

1 



sample problems 










1. Simple Addition: 


4 + 5 = ? 








Key 






Display 


Comments 


C 










C 






NONE 


Clear necessary on power-up 


4 






NONE 




+ 






NONE 




5 






NONE 




= 






NONE 




8 






NONE 


Answer supplied 


TEST 






WRONG 


Wrong answer 


4 






NONE 


Indicator goes out 


+ 






NONE 




5 






NONE 




= 






NONE 




9 






NONE 




TEST 






RIGHT 




II. Missing Factor Addition: 6+? = 


= 11 






Key 






Display 


Comments 


6 






NONE 


Indicator goes out 


+ 






NONE 




5 






NONE 


Missing factor supplied 


= 






NONE 




11 






NONE 




TEST 






RIGHT 




III. Subtraction: 4- 


7 = ? 








Key 






Display 


Comments 


4 






NONE 


Indicator goes out 


- 






NONE 




7 






NONE 




= 






NONE 




- 






NONE 




3 






NONE 


Negative answer supplied 


TEST 






RIGHT 




IV. Multiplication: ; 


x 3 = ? 








Key 






Display 


Comments 


7 






NONE 


Indicator goes out 


X 






NONE 




3 






NONE 




= 






NONE 




21 






NONE 


Answer supplied 


TEST 






RIGHT 





8-94 



sample problems (con't) 






V. Missing Factor Multiplication: 6 x ? = 


= 12 




Key 


Display 


Comments 


6 


NONE 


Indicator goes out 


X 


NONE 




3 


NONE 


Missing factor supplied 


= 


NONE 




12 


NONE 




TEST 


WRONG 


Incorrect 


6 


NONE 


Indicator goes out 


X 


NONE 




2 


NONE 


Missing factor supplied 


= 


NONE 




12 


NONE 




TEST 


RIGHT 




VI. Division: 15^3=? 






Key 


Display 


Comments 


15 


NONE 


Indicator goes out 


H- 


NONE 




3 


NONE 




= 


NONE 




5 


NONE 


Answer supplied 


TEST 


RIGHT 




VII. Complex Chain: (6 + 2- 10) x 3 = ? 






Key 


Display 


Comments 


6 


NONE 


Indicator goes out 


+ 


NONE 




2 


NONE 




- 


NONE 




10 


NONE 




x 


NONE 




3 


NONE 




= 


NONE 




- 


NONE 




6 


NONE 


Negative answer supplied 


TEST 


RIGHT 





8-95 



05 
115 



a 



Calculators 



MM5791 seven-function, accumulating memory calculator 



general description 

The single-chip MM5791 calculator was developed using 
a metal-gate, P-channel enhancement and depletion mode 
MOS/LSI technology with a primary objective of low 
end-product cost. A complete calculator as shown in 
Figure 1 requires only the MM5791, a keyboard, 
DS8874 digit driver, NSA1198 or NSA1298 LED 
display and a 9V battery. 

Keyboard decoding and key debounce circuitry, all 
clocks and timing generation, power-on clear, display 
turnoff and 7-segment output display decoding are in- 
cluded on-chip and require no external components. 
Segments can usually be driven directly from the 
MIVI5791, as it typically sources 8.5 mA of peak current. 
The left-most, or 9th digit is used to indicate memory 
in use or the negative sign of an eight digit number. 

Leading zero supression and a floating negative sign 
allows convenient reading of the display and conserves 
power. The DS8874 digit driver is capable of sensing a 
low battery voltage and providing a signal during the 
left-most digit time that can be used to turn on one of 
the segments as an indicator. Typical current drain of a 
complete calculator displaying five "5's" is 30 mA. 
Automatic display cutoff after approximately 25 seconds 
is included. 

The Ready output signal is used to indicate calculator 
status. It is useful in providing synchronization informa- 



tion during testing and when the MM5791 is used with 
other logic devices. 

Data (D) and Shift (CP) outputs are the only two 
connections required between the MM5791 and the digit 
driver. This reduces the number of pins on both packages 
and the amount of interconnect on the printed circuit 
board. Figure 3 shows the timing relationships between 
the MM5791 and DS8874. 



features 

■ Full 8-digit capacity 

■ 7-functions (+, -, x, +, x 2 , y/x, %) 

■ Convenient algebraic notation 

■ Fully protected accumulating memory (M+, M— ) 

■ Automatic constant independent of memory 

■ Floating input/floating output 

■ Power-on clear* 

■ On-chip oscillator* 

■ Display turnoff after 25 seconds (typical)* 

■ Direct 9.0V battery compatibility* 

■ Low system cost 

■ Direct segment drive of LED display* 

'Requires no external components. 



connection diagram 

Dual-ln-Ltne Package 



NC 


• 


NC-2- 




NC_i 




HC-L 




- 5 
D 




6 
CP 




VoD — 




■! 8 




niRPI AY _i 




RESET 




s c — 




s -LI 




12 

vss — 





■ K2 
-K3 



— Sf 



TOP VIEW 

Order Number MM5791N 

See Package 22 



keyboard outline 



Sample Keyboard 



GD 



GDQQEH 
QHHQQ 

□QQHB 

□0EEB 
EEEBQ 



absolute maximum ratings operating voltage 


range 




Voltage at Any Pin Relative to V S s Vss + °- 3V to V SS ~ 12V 6 - 5V < V SS ~ V DD < 9 - 5V 






(All Other Pins Connected to Vss) 






Ambient Operating Temperature 0°C to + 70° C 






Ambient Storage Temperature — 55°C to +150°C 






Lead Temperature (Soldering, 10 seconds) 300 C 






dc electrical characteristics 






PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Operating Supply Current (l DD ) 


Vnn " V ss 9-5V, T A - 25 C 




8 


15 


mA 


Keyboard Scan Input Levels 












(K1-K4) 












Logical High Level (V, H ) 


V|j D = v ss 6.5V, l IH < 300 AJA 


v ss "2.5 




v ss 


V 




v dd = v ss 9 -5V,l| H < 300 jjA 


Vss 4.7 




Vss 


V 


Logical Low Level (V, L ) 


V DD = V ss -6.5V 


Vdd 




V ss 5.5 


V 




V DD = V s5 -9.5V 


Vdd 




V ss -B.O 


V 


Display Reset Input Levels 












Logical High Level 


V Dn = V ss - 6.5V 


Vss-1 5 






V 


Logical Low Level 


V DD - V SS -9.5V 






V DD + 1.5 


V 


Segment Output Current 


T A - 25 C, 












Voui = Vss 3.6V, V DD = Vss 6.5V 


5 






mA 




V„ut " V ss -5.0V, V DD - Vss -8.0V 




10 




mA 




V oul -- Vss -6 5V, V DD = Vss "9.5V 






15 


mA 


Ready Output 


Vdd- V ss 6.5V 










Logical High Level 


Iout ' "250mA 


V ss -1.0 






V 


Logical Low Level 


l OUT -25mA 






Vss 5 


V 


D and CP Outputs 












Logical High Level 


V DD - Vss -6-5V, V OUT - V ss --2.0V 


220 






pA 




Vdd" V ss -9.5V, V ou - - V ss --5.0V 






-1100 


pA 


Logical Low Level 


V DD = V ss -9.5V, V OUT = V DD tO.SV 


100 






AlA 


ac electrical characteristics 


PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Word Time 


(Figure 2) 


0.53 




3.3 


ms 


Digit Time 


'Figure 2} 


58 




367 


PS 


Interdigit Blanking Time 


(Figure 2} 




4.0 




PS 


(Segment Outputs) 












CP and Transition Times 












High to Low 


V DD = V ss 6.5V 




5 


12 


PS 


Low to High 


C l oad " 50 pF 




075 


1.5 


PS 


Ready Transition Times 












High to Low 


Vdd "- V ss -6.5 




5 


20 


Ps 


Low to High 


C LO , VJ = 50 pF 




2 


4 


PS 


Keyboard Scan Inputs 












High to Low 












Low-to-High Transition Time 


C, i,AD = 100 pF 




4.0 




PS 


After Key Release 












Key Bounce-Out Stability Time 




6.36 




39.6 


ms 


(The time a keyboard scan input must be con- 












tinuously lower than the maximum logical low 












level to be accepted as a key closure, or higher than 












the minimum logical high level to be accepted as a 












key release.) 












Display Cutoff Time 






25 




seconds 


(The time after the last valid key closure at which 












the 7 most-significant has will be blanked.) 












Worst Case Calculation Time 








200 


word times 



2 



8-97 



FUNCTIONAL DESCRIPTION 


The MM5791 is a calculator chip which contains four The MM5791 performs the "+," "-," "x" and "^" 


data registers: (1 ) entry, (2) accumulator, (3) working and functions using algebraic notation. This requires the use 


(4) memory, each consisting of 8 digits, sign, and decimal of a mode register and a terminate flag. The mode 


point. The entry register is always displayed. It contains register directs the machine to the proper function (add. 


digit entries from the keyboard, and results of all func- subtract, multiply or divide) with each new key entry. 


tions except M+ and M-. The accumulator is used in all After the function has been performed, the key entered 


arithmetic functions and stores a copy of the entry is used to modify the mode register 


register on all results. This allows another number to be 


entered without losing an intermediate result. Multiply The terminate flag is set on "=" and sometimes on "%" 


and divide requires three registers to perform the function and "C." This signifies the end of the problem. The 


and save the divisor, or multiplier. The working register MM5791 allows for full floating entries and intermediate 


is provided to perform these functions in conjunction results. 


with the entry and accumulator registers. 


If the terminate flag is set, a "+," "-," "x" or "-■" key 


The memory register is used only to store a number to be signals the beginning of a new problem. The number 


used later. It is fully protected during all operations, and being displayed is copied into the accumulator register 


is only modified by depressing a "MS," "M+," or "M-" and the mode register assumes the mode of the key 


key. Power on clears all of the registers including the entered. The terminate flag is always reset by the "+," 


memory register. 






"—, " "x" and "t" keys. 










s ao 


Sq 


SI 


Se 


Ssi 


Sc 


Sb 


S.I 


1 


I 


!ia| Sb 


Sc 


Stl 


Se: 


St 


Sb 










K! 


MM!i791 






MSA129B 
















Vss 








K3 




K4 




























1 


CP 








□ 1 


D2 


D3 


D4 


05 


DB 


ui 


D8 


D9 














READY 






' 






















v DO 






















_*■ 1 












D 


CP 


Vss 


v ou 


LV 
























9V 

-o o-* 


















DS8874 




















-ON-OFf" 




09 


D3 


D7 


06 


D5 


D4 


D3 


D2 


01 






■ 


SS- 


s^ 


«- 


^ 








































s^ 


N, 


^, 


>, 






































i 


M>- 


SS- ' 


^m_ ■ 


So- 




































v s 


^, 


n. 


































• 


S^ 


^_ , 


S^ 
































\ 


>, 


N, 






























< 


s&- 


VU ' 


l *- 




























-^ 


N, 


N, 


























' 


SJ- 


^_ 


^_ 
























\ 


% 


s. 






















i 


sS- 


^ , 


">«-' 




















-^ 


N, 




















i 


S^ 


^ , 


^-" 
















\ 


^ 


s. 
















l >i- 


^ 


k ^-" 










N i* >. 





h ■ 








FIGURE 1. Complete Calculator Schematic 





OUTPUT FROM . 

QIG1T DBfVER (—- 


WORD TIME ■ 










OV i i 

01 DU H 1 










i i 


_r 


"' — H —DIGIT TIME 




"' » 1 1 










i 








'.' ,» L._. 


J 










~!_ 


09 










i i 




1\ 








r~ 


~~l 


SEGMENTS' 












1 




Ss 


i n 


n r~ 


~y 


LT 


u 


- 1 | r~ 


~i_ 


-*- s— SEGMENT BL 


MKWU TIMt 


i 


»J u u 


II I 


r 


u 


1 ! II 


"IT 

-j" 










st J 


i ;> 


u u 


i 


LT 


u 


1 1 1 








Sd | 


i 11 


~> l^ 


U 

1 


|_ 


1 


~~] , r" 


"IT 


! 












Se ; 


.i i 


L_ 


1 


"~ i i ,r~ 


~!_ 


S( 












_J u 


u 


1_ 


1 


"~i 
















Sq 


1 u 

o ~i r r 
U 1 /_/ _/ 


U U 

1 1 ~l Zl 1 
1 _/./_ / 


u 

1 
Disp 


1 


1 


— l r— 


IT 


ACTUAl OlSPLfi 


lay Timing 


SEGMENT '/ S fa 

DESIGNATION e f t, 






FIGURE 2. 


MM5791 - 


°^U~ 




U 






u 




CP J ij 2 \j_ 


J 4 LiJ B LlI 8 L 


if 


2 jjj 4 1 


J 6 LlI 


[9 l] 2 [3] 4 I5J 6 1? 




DS8874 


'■» u~ 




i_r 






U 


u 




u 




u 


u 




1-T 




u 


04 


U 




~ LT 




u 


D5 


u 




U 


u 


DB 


u 






i_r^ 


u 


D7 


u 






"TJ 


l_ 


08 J 


u 






u 


U u 


u 






u 




FIGURE 3. Dtgrt Timing 






OPERATION IN THE ADD AND SUBTRACT MODE 












If the terminate flag is set, an "=" key w 


II result in a 




If the 


terminate flag is not set, and a number has not 


constant add/subtract. The number in the 


accumulator 




been t 


ntered 


from the keyboard 


or memory, a "+," 


will be added to (or subtracted from) the number being 




"- " ' 


X" ' ,J r 


key will only chan 


ge the mode register 


displayed. The result is right-justified and 


displayed in 




to the 


new key entry. 




the entry register. Accumulator and mode 


registers are 












not altered, allowing for constant operations 






If the 


terminate flag is not set, an "=" key will add/ 


If the terminate flag is not set and a num 


3er has been 




subtract the number being displayed to/from the number 


entered from the keyboard, or memory register, a "+," 




in the 


accumulator register. The number being displayed 


"-," "x" or "+" key will result in an 


addition or 




is transferred 


to the accumulator. 


and the result of the 


subtraction. The entry register will be adde 


d to or sub- 




operat 


on i s d 


splayed in the entry register. The terminate 


tracted from the accumulator and the new 


unning total 




flag is 


set, conditioning the calculator for constant. 


will be displayed in the entry register anc 


copied into 




add/subtract 


operation. The number being displayed 


the accumulator register. The mode wil 


be altered 




previous to the "=" key is stored 


n the accumulator as 


according to which key is entered. 






the constant. 







01 

CO 



899 



Operation of the "%" key in add/subtract mode, with 
the terminate flag reset, will multiply the accumulator 
by the last entry, divide the result by 100, and display it 
in the entry register. The mode register remains as it was 
in the add or subtract mode. All of the above is required 
to perform the percent add on or discount problems. 
Depression of an "=" key after the "%" key will either 
tax or discount the original number as a function of the 
mode register and the last entry. 

Operation of the "%" key in add/subtract mode, with 
the terminate flag set, will shift the decimal point of the 
number being displayed two places to the left and copy 
it into the accumulator register. The mode is set to 
multiply and the terminate flag remains set. 

OPERATION IN THE MULTIPLY MODE 

If the terminate flag is set, an "=" key will result in a 
constant multiply operation. The number being displayed 
is multiplied by the constant stored in the accumulator 
register. The result is displayed in the entry register and 
the accumulator and mode registers are not altered, 
allowing for constant operation. Repeated depressions 
of the "=" key can be used to raise a number to an 
integer power, i.e., "C," "C," "5.2," "x," "-," " = ," 
"=," computes 5.2 4 . 

The constant in multiplication, as well as in addition, 
subtraction and division is the last number entered. For 
the sequence: "C," "C," "3," "^," "4," "x," "2," "-" 
the constant multiplier for future problems is 2. 

If the terminate flag is not set, an "=" key will signal 
the end of a problem. The number in the display will be 
multiplied by the contents of the accumulator, and the 
results will be displayed in the entry register. The number 
previously in the entry register is stored in the accumu- 
lator register and the terminate flag is set. 

If the terminate flag is not set, and a number has been 
entered from the keyboard or memory register, a "+," 
"— ," "x" or "V key will result in a multiplication. The 
number being displayed will be multiplied by the num- 
ber residing in the accumulator register. The result will 
be copied into the accumulator and displayed in the 
entry register. The mode register is up-dated as a func- 
tion of the key depressed. 

Operation of the "%" key while in multiply mode looks 
exactly the same as an "=" key except the decimal 
point of the display is shifted two positions to the left 
before the multiplication takes place. 

OPERATION IN THE DIVIDE MODE 

If the terminate flag is set, an "=" key will result in 
constant divide operation. The number being displayed 
is divided by the constant stored in the accumulator 
register. The accumulator and mode registers are not 
altered allowing for constant operations. Repeated de- 
pressions of the "=" key will result in repeated divisions 
by the constant. Thus, it is possible to raise a number to 
a negative integer power using the sequence: "C," "C," 
"1," "V "No.," "=," "=," etc. 

If the terminate flag is not set, an "=" key will signal 
the end of a problem. The number in the accumulator 
register will be divided by the number being displayed. 
The result is transferred to the entry register and dis- 



played. The terminate flag is set and the divisor is stored 
in the accumulator register. 

If the terminate flag is not set, a "+," "-," "x" or "±" 
key will result in a division. The number in the accumu- 
lator register will be divided by the number being 
displayed. The results are displayed in the entry register, 
and a copy of the result is stored in the accumulator. 
The mode register is modified to reflect the latest key 
entry. 

Operation of the "%" key while in divide mode looks 
exactly the same as the "=" key except the decimal 
point of the display is shifted two positions to the left 
before division takes place. 

ERROR CONDITIONS 

If any of the operations mentioned above generates a 
number larger than 9999 9999, an error will occur. An 
error is indicated by displaying the eight most significant 
digits and sign with all nine decimal points. The first 
depression of the "C" key will clear the error condition, 
and all registers except the memory register. 

It is not possible to generate an error during number entry. 
The ninth and subsequent digits entered are ignored. 

DISPLAY TURNOFF AND LEADING ZERO 
SUPPRESSION 

In order to conserve battery power, the MM5791 blanks 
leading zeros and turns off all but the least significant 
digit, decimal point and sign after 25 seconds (typical) 
of no activity. Once the display turns off, any key 
depression will turn it back on and perform the function 
indicated. Two depressions of the "CS" key will turn 
on the display with no change to the machine. If Reset 
Display is hard-wired to V DD , the display will never 
turn off. 

POWER-ON CONDITION 

The MM5791 has an internal power-on clear circuit 
which clears all registers to zero, places the mode to add 
and sets the terminate flag. A zero and decimal point 
are displayed. 

KEYBOARD BOUNCE AND NOISE REJECTION 

The MM5791 is designed to interface with most low cost 
keyboards, which are often the least desirable from a 
false or multiple entry standpoint. 

A key closure is sensed by the calculator chip when one 
of the key inputs, K1, K2, K3 or K4 is forced more 
negative than the Logical Low Level specified in the 
electrical specifications. An internal counter is started 
as a result of the closure. The key operation begins after 
eleven word times if the Key Input is still at a Logical Low 
Level. As long as the key is held down (and the Key 
Input remains low) no further entry is allowed. When 
the Key Input changes to a Logical High Level, the 
internal counter starts an eleven word timeout for key 
release. During both, entry and release timeouts, the 
Key Inputs are sampled every word time for valid levels. 
If they are found invalid, the counter is reset and the 
calculator resumes scanning the keyboard. 



-100 



READY SIGNAL OPERATIONS 



The Ready signal indicates calculator status. When the 
calculator is in an "idle" state, the output is at a Logical 
High Level (near V ss ). When a key is closed, the internal 
key entry timer is started. Ready remains high until the 
timeout is completed and the key entry is accepted as 
valid, then goes low as indicated in Figures 5 and 6. 
It remains at a Logical Low Level until the function 
initiated by the key is completed and the key is released. 
The low to high transition indicates the calculator has 
returned to an idle state and a new key can be entered. 

TEST FEATURES 

Several features have been designed into the MM5791 
to facilitate testing. One is to allow the key debounce 
timing to be modified, and the second performs a 
"segment test" function which turns on all segments for 
all digit times, with no interdigit blanking. The key 
bounce time can be reduced from eleven word times to 
one if a key closure is made between D9 and K2. 
Similarly the "Segment Test" occurs when a key closure 
is made between D9 and K3. Closures for test operations 
are not debounced, and also may occur simultaneously 
with normal key closures if diodes are used to isolate 
the D-Lines from each other. The test features are active 
for every word time the Test switch closure is main- 
tained. These test matrix entries are isolated internally 
from the normal calculator keys, allowing simultaneous 
entry of "test" keys and "calculator" keys. 

FUNCTION OF KEYS 

Some of the keys operate differently when in the data 
or number entry condition. The MM5791 switches to 
entry condition when entering numbers and leaves this 
condition after most function keys. The following para- 
graphs discuss each of the keys on a full keyboard and 
the action taken when they are depressed. The earlier 
paragraphs which discussed the action of "+," "—, " "x," 



' 1J r" and "%" keys and the examples given in later 
sections will aid in further explaining these actions. 

Clear Key, "CE/C" 

While in the number entry condition, one depression 
will clear the entry register to zero and recall the 
accumulator for display. The machine then leaves the 
number entry state. 

If the error condition is displayed, one depression will 
clear the error, and all registers except the memory 
register. The machine could not be in the number entry 
condition with the error flag set. 

If the error flag is not set and the machine is not in the 
number entry condition, one depression of "CE/C" key 
will clear the entry and accumulator registers. It also 
places the machine in the add mode and sets the termi- 
nate flag. The memory register remains unchanged. 

Number Keys 0-9 

If not in the number entry condition, a number key will 
clear the display and then enter the value of the key 
into the LSD. The digits are displayed as they are entered 
and the machine assumes the number entry condition. 

If in the number entry condition, the entry register is 
shifted left one position and the key depressed is entered 
into the LSD. If there is a number in the most significant 
digit position (9th) the entry register is then shifted 
right one position and the entry is lost. 



Square Root Key, 



The square root key extracts the square root of the 
absolute value of the number being displayed in the 
entry register. 



°~LT 



5....S (TYPICAL) 



ELEVENTHSLJCCESSIVE'' ' 1 l"~ 
OIGIT INPUT ■— ' 



TJ — "" 



FIGURES. Ready Timing 



r 

11 WORDS 
AFTER KEY 
RELEASE OR 
CALCULATION 

-| IS COMPLETED. 

WHICHEVER IS 
LONGER 



WKEV HAS BEEN ACCEPTED 
BY CALCULATOR. THE KEY- 1 
MAY BE RELEASED. 



NEXT KEY CAN 
BE ENTERED 



FIGURE 6. Functional Description of Ready Signal and Key Entry 



8-101 



The mode of the calculator remains unchanged. This 
enables square root operations in the middle of chain 
calculations. For example: 

KEY DISPLAY KEY DISPLAY KEY DISPLAY 



A A 


A 


A 


yT VA 


X 


A 


+ \/A 


B 


B 


B B 


>T 


V§ 


v v§ 


= 


A\/B 


= Va + n/b 







11 


11 


+ 


11. 


5 


5 


= 


16. 


^r 


4. 


6 


6. 


= 


11 


9 


9 


V^ 


3. 



While in multiply or divide mode, this key shifts the 
displayed decimal point two places to the left, completes 
the multiplication or division and sets the terminate flag. 

In add or subtract mode, this key shifts the displayed 
decimal point two places to the left, multiplies the 
display times the accumulating register, places the pro- 
duct in the entry register and leaves the accumulator 
register and mode register undisturbed. This permits 
automatic calculation of net by depression of the "=" 
key. The terminate flag is not altered. 



SAMPLE PROBLEMS 



1 . Simple addition or subtraction 
KEYS DISPLAY 



COMMENTS 



Square 

Depression of the "Square" key copies the number being 
displayed into the accumulator register, and performs a 
multiplication. On completion of the square operation, 
the results are displayed in the entry register, the original 
number is stored in the accumulator and the mode of the 
calculator is unchanged. Entering a number to start a 
new entry will first clear the entry register. 

Memory Plus Key, "M+" 

When the "M+" key is depressed, the number being 
displayed is added to the contents of the memory and 
the results, providing there is no overflow, are placed in 
the memory. The calculator will be out of the data 
entry mode. 

if an overflow occurs, the contents of the memory are 
not altered. The display shows the eight most significant 
digits and sign of the results with all nine decimal points. 

Memory Minus Key, "M— " 

This key operates like the "M+" key only the displayed 
number is subtracted from memory. 



4.355 



3.25 
CS 

4 




3 

3. 
2 
5. 



4.3 5 5 
0.6 4 5 



0.6 4 5 

3.2 5 

-3.2 5 

-3.2 5 4 

-2.6 9 



-1.6 9 



Start addition pro- 
blem 
Sets add mode 

Completes addition, 
sets add mode 
Sets subtraction 
mode 

Completes subtrac- 
tion. Sets mode ter- 
minal 

Sets mode terminal. 
Sets add mode, resets 
Starts Digit Entry 
Changes Sign 
Continues Digit Entry 
Completes signed 
addition, sets add 
mode 

Completes signed 
addition, sets termin- 
ate mode 



Plus, Minus, Multiply and Divide Keys, 



x. 



2. Constant addition or subtraction (second factor 
constant) 



These keys terminate a number entry, complete the 
operation designated by the mode register and update 
the mode register for the next operation. A more detailed 
explanation of these keys is found in the description 
of modes. 

Equal Key, "=" 

This key terminates a number entry, complete the 
operation designated by the mode register and sets the 
terminate flag. 

Percent Key, "%" 

Following a clear-all operation or a number entry 
proceeded by a clear all operation, this key shifts the 
decimal point of the number being displayed two places 
to the left, copies it into the accumulating register and 
establishes the multiply mode. 



KEYS 

3 


DISPLAY 

3 


COMMENTS 


- 


3. 


Sets subtract mode 


2 

+ 

6 


2 

1. 

6 


Completes subtrac- 
tion, sets Add mode 




7. 


Completes addition, 
saves (6) as constant 
sets terminate mode 


.5 


.5 




= 


6.5 


Completes constant 
addition constam = 6 


7 


7 






7. 


Sets subtraction 
mode, resets termin- 
ate mode 



-102 



2. Constant addition or subtract 


on (second factor 


5. Constant 


multiplication (cont 


nued) 


constant) (continued) 














KEYS 


DISPLAY 


COMMENTS 


KEYS DISPLAY 


COMMENTS 


6 


6 




3 3 




= 


2 4. 


Completes constant 


4. 


Completes subtrac- 
tion, sets terminate 






multiplication, 
constant = 4 




mode, saves 3 as a 


3 


3 






constant 


- 


3. 


Sets subtract mode. 


8 8 








resets termination 


EX 3. 


Exchanges entry, and 


4.5 


4.5 






constant 


X 


-1.5 


Completes subtrac- 


-5. 


Completes subtrac- 
tion constant = .8 






tion, sets multiply 
mode 


9 9 




8 


8 




1. 


Completes subtrac- 


CS 


-8 


Changes sign 




tion constant = 8 




1 2. 


Completes multipli- 
cation '—8' as con- 
stant, sets termina- 
tion mode 


3. Simple multiplication 




EX 


-8. 


Exchanges entry 
register, and constant 


KEYS DISPLAY 


COMMENTS 


CS 
3 


8. 
3 




3.1 3.1 


Start multiplication 
problem 


= 


3 6. 


Completes constant 
multiplication 


X 3.1 


Sets multiply mode 






constant = 12 


6 6 




= 


4 3 2. 


Completes constant 


1 8.6 


Completes multipli- 






multiplication 




cation, sets terminate 


3 


3 


constant = 1 2 




mode 


X 


3. 


Sets multiply mode, 
resets termination 
mode 






+ 


3. 


Sets add mode. 


4. Chain multiplication 








Second function key 
only modifies mode 


KEYS DISPLAY 


COMMENTS 


- 


3. 


Sets subtract mode 






X 


3. 


Sets multiply mode 


3 3 




= 


9. 


Completes multipli- 


+ 3 


Sets add mode 






cation. Sets termina- 


4 4 








tion mode 


X 7. 


Completes addition, 
sets multiply mode 








6 6 










42. 


Completes multipli- 
cation, sets subtract 


6. Simple d 


vision 






mode 


KEYS 


DISPLAY 


COMMENTS 


2 2 










4 0. 


Completes subtrac- 


4 


4 






tion, sets terminate 




4. 






mode, saves 2 as 


3 


3 






constant 


CS 


-3 
-1.3333333 




5. Constant multiplication 




7. Chain div 


sion 




KEYS DISPLAY 


COMMENTS 


KEYS 


DISPLAY 


COMMENTS 


3 3 




3 


3 




X 3. 


Sets multiply mode 


^ 


3. 




4 4 




8 


8 




1 2. 


Completes multipli- 


+ 


0.3 7 5 






cation, saves '4' as 


2 


2 






constant, sets termin- 


X 


2.3 7 5 






ation mode 


3.1 


3.1 





8-103 



7. Chain division (continued) 



10. Percent in multiplication and division (continued) 



KEYS 



DISPLAY 



COMMENTS 



+ 7.3 6 2 5 

6 6 

1.22 70833 



8. Constant division 
KEYS 
6 
2 



15 

2 
X 
8.3 

3 

CS 

EX 

EX 
CS 
EX 
608.7 



Add on and discount problems 
KEYS DISPLAY 



DISPLAY 


500 

5 0. 

4 

12 500. 



DISPLAY 


6 


6. 


2 


3. 


1.5 


1 5 


1 5. 


2 


1 3. 


8.3 


1 7.9 


3 


-3 


1 7.9 


02780352 


1 7.9 


-1 7.9 


027 80352 


6 8.7 


-5.6 4 13 3 4 5 



COMMENTS 



KEYS 

500 



4 

% 



11. Memory operations 
KEYS DISPLAY 

6 

MI- 



COMMENTS 



COMMENTS 



695.99 



6 9 5.9 9 
6 9 5.9 9 



2 

M- 

MR 

3.678 

CS 

M+ 

X 

5 

M- 

MR 

5 

MS 

3 

X 

4 

X 

MR 


MS 



COMMENTS 



Memory indicator 
is activated 



3 

3. 

2 

2. 

5. 

4. 

3.6 7 8 

-3.6 7 8 

-3.6 7 8 

-3.6 7 8 

5 

5. 

-1 8.3 9 

-4.6 7 8 

5 

5. 

3 

3. 

4 

1 2. 

5. 

6 0. 



0. 



Memory indicator 



20 

% 


20 
1 3 9.1 9 8 






turned off when 
contents equal zero 


= 


5 5 6.7 9 2 








+ 


5 5 6.792 


12. Square 


root problems 




6 


6 








% 


3 3.4 7 5 2 


KEYS 


DISPLAY 


COMMENTS 


= 


5 9 0.1 9952 








17.95 


1 7.9 5 


3 


3 




- 


1 7.9 5 


^r 


1.7 3 20 508 




15 


1 5 


+ 


1.7320 50 8 




% 


2.6 9 2 5 


4 


4 




+ 


1 5.257 5 


V^ 


2. 




6 


6 


= 


3.7 3 20 508 




% 


0.9 1 54 5 


7 


7 






1 6.1 7 29 5 


+ 
8 


7. 

8 

1 5. 




10. Percent in 


multiplication and division 


v^ 


3.87 2 983 3 




KEYS 


DISPLAY COMMENTS 


13. Square 


problems 




308 


308 


KEYS 


DISPLAY 


COMMENTS 


X 


3 8. 








5 


5 


72 


7 2 




% 


1 5.4 


X 2 


5 184. 





8-104 



a 



Calculators 



2 
01 



MM5794 seven -function, accumulating memory, 
vacuum fluorescent display calculator 



general description 

The single-chip MM5794 offers a seven-function, 
accumulating memory MOS/LSI calculator device 
capable of directly driving 8-digit vacuum-fluorescent 
displays. A complete calculator as shown in Figure 1 
requires only the MM5794, a keyboard, vacuum 
fluorescent display and an appropriate power supply. 

Keyboard decoding and key debounce circuitry, all 
clocks and timing generation, power-on clear and 7- 
segment output display decoding are included on-chip 
and require no external components. Segments and 
digits can be driven directly from the MM5794. The 
left-most, or 9th digit is used to indicate memory in use 
or the negative sign of an eight digit number. 

Leading zero suppression and a floating negative sign 
allow convenient reading of the display and conserves 
power. Typical current drain of a complete calculator 
displaying five "5's" is 30 mA. 



features 

■ Full 8 digit capacity 

■ 7-functions (+, - x, 4-, x 2 , \/x , %) 

■ Convenient algebraic notation 

■ Fully protected accumulating memory (M+, M-) 

■ Automatic constant independent of memory 

■ Floating decimal input and output format 

■ Power-on clear* 

■ On-chip oscillator* 

■ Low system cost 

■ Direct segment and digit drive of fluorescent displays 

■ Memory in-use indicator 

+ Requires no external components. 



connection diagram 



keyboard outline 



Dual-ln-Line Package 



DIGIT 4— 




24 

— DIGIT 3 


DIGIT 5 — 2 - 




21 

DIGIT 2 


DIGIT6— 




22 

— v GG 


digit;— 




ii.K, 


DIGITS- 




20 
K2 


DIGIT 9— 




19 
— K3 


DIGIT 1 — 




18 
K4 


8 




17 

SEGMENT F 


SEGMENT D. P. 




SEGMENT B 


SEGMENT C — 




— SEGMENT G 


SEGMENT A — 




SEGMENT D 


Vss^ 




SEGMENT E 



Typical Keyboard 



HHLZBEB 
CDHQHQ 

CEBEB 
□EHEE 
HQQQG 



ED 



Order Number MM5794N 
See Package 22 



8-105 



absolute maximum ratings 

Voltage at Any Pin Relative to 

V ss Except V GG (All Other 

Pins Connected to V ss ) V ss + 0.3V to V ss - 12V 
Voltage at V GG Relative 

toV ss V ss + 0.3V to V ss -35V 

Ambient Operating Temperature 0°C to +70 J C 

Ambient Storage Temperature — 55°C to +150' C 

Lead Temperature (Soldering, 10 seconds) 300" C 



dc electrical characteristics 



operating conditions 



6.5 <V q 



V DD <9.8V 



Vss-V GG <32V 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Operating Supply Current 












'dd 


V DD " V ss 9.5V, T A ^ 25 C 




8 


15 


mA 


Igg 


Vgg - V ss - 32V 




500 




IsA 


Keyboard Scan Input Levels 












(K1-K4) 












Logical High Level (V, H ) 




Vss-70 




Vss 


V 


Logical Low Level (V, L ) 




Vgg 




V S s-22 


V 


Source Current, (Segments) 


T A = 25"C 










'oh 


Vout' V SS -4V, V DD - V ss -6.5V 






-0.6 


mA 


l0L 


Vqut =V SS -35V 






10 


/J A 


Digit Outputs 












Logical High Level 


Vgg = v ss " 32V, V olJT = V ss - 5.0V 






-3.5 


mA 




V GG ' V ss - 25V, V OUT - V ss 5.0V 






-2.2 


mA 


Logical Low Level 


Vdd = V ss - 9.5V, V OUT = V GG - V ss - 35V 






10 


MA 



ac electrical characteristics 



PARAMETER 


CONDITIONS 


MIN 


TYP 


MAX 


UNITS 


Word Time 


{Figure 2) 


0.53 




3.3 


ins 


Digit Time 


(Figure 21 


58 




367 


fs 


Interdigit Blanking Time 


(Figure 2) 


14.5 


20 




/Js 


(Segment and Digit Outputs) 












Digit Transition Times 


I 100k Resistor to V GG 










High to Low 


| V DD - V ss -6.5V 




20 




W 


Low to High 


(Cload = 100 pF 






4 


/Js 


Ready Transition Times 












High to Low 


Vdd V ss - 6.5 




5 


20 


/Js 


Low to High 


c i oad '" 50 PF 




2.0 


4.0 


f« 


Keyboard Scan Inputs Transition Times 


1 V GG = V S3 - 35 










High to Low (After Key Release) 


| c load = 50 pF 






100 


/US 


Low to High (After Key Release) 


| C LO ad = 100 pF 






4 


KS 


Key Bounce-Out Stability Time 




6.36 




39.6 


ms 


(The time a keyboard scan input must be con- 












tinuously lower than the maximum logical low 












level to be accepted as a key closure, or higher than 












the minimum logical high level to be accepted as a 












key release.) 












Worst Case Calculation Time 








200 


word times 



8-106 



FUNCTIONAL DESCRIPTION 

The MM5794 is a calculator chip which contains four 
data registers: (1 ) entry, (2) accumulator, (3) working and 
(4) memory, each consisting of 8 digits, sign, and decimal 
point. The entry register is always displayed. It contains 
digit entries from the keyboard, and results of all func- 
tions except M+ and M— . The accumulator is used in all 
arithmetic functions and stores a copy of the entry 
register on all results. This allows another number to be 
entered without losing an intermediate result. Multiply 
and divide require three registers to perform the function 



and save the divisor, or multiplier. The working register 
is provided to perform these functions in conjunction 
with the entry and accumulator registers. 



The memory register is used only to store a number to be 
used later. It is fully protected during all operations, and 
is only modified by depressing a "MS," "M+," or "M-" 
key. Power on clears all of the registers including the 
memory register. 



2 
CD 



100k 

1 1 — ^/^A/- 



100k 

ii ^AiV- 




ii Wv- 



100k 

ii — vw 



ii — vw- 



C/CE 



■^ 



V GG S G S F S E s S C S 8 S A S DP 
MM5794 

vss 

09 08 D7 06 05 D4 D3 02 01 



-i*- 



100 k 

u *AAr- 



V GG - V SS " 3 * v * 

V DD " V ss -fi.5VT0 V SS -9.5V 



o- 
o- 




-AW 



S DP S A S B S C S D S E S F S G 

FLUORESCENT DISPLAY 
D1 1 " DZ 03 04 05 D6 07 D8 09 




OC TO DC 

CONVERTER 'A.V7-6V 



m 



* V SS " V DD must be as specified in this data sheet (6.5-9.5) but V S s - V GG' E f and V Z are determined by the fluorescent display specifications. 
* D1 is the right-most display digit, also see Figure 2. 

FIGURE 1. Complete Calculator Schematic 



8-107 



The MM5794 performs the "+," "-," "x" and "±" 
functions using algebraic notation. This requires the use 
of a mode register and a terminate flag. The mode 
register directs the machine to the proper function (add, 
subtract, multiply or divide) with each new key entry. 
After the function has been performed, the key entered 
is used to modify the mode register. 



If the terminate flag is set, a "+," "-," "x" or "H-" key 
signals the beginning of a new problem. The number 
being displayed is copied into the accumulator register 
and the mode register assumes the mode of the key 
entered. The terminate flag is always reset by the "+," 

,,_., ,,^,, an( _j ,,J_,, kgyg 



The terminate flag is set on "=" and sometimes on "%" 
and "C/CE." This signifies the end of the problem. 
The MM5794 allows for full floating entries and results. 













- word™ 










DIGIT 
TIME 


















1 




L 


DIGIT 1 






— DIGI 


T BLANKING TIME 






DIGIT 2 




L 


DIGIT 2 














DIGIT 3 




L 


DIGIT 3 
















0IGIT4 


L 


0IGIT4 


















0IGIT5 








DIGIT 5 




















DIGIT 6 








DIGIT 6 






















DIGIT 7 








DIGIT 7 
























DIGITS 




L 


DIGITS 
























DIGIT 9 








DIGIT 9 


























SEGMENT D.P. 


L 








































SEGMENT A 


1 


L 


L 


L 


L 


L 










1 










SEGMENT B 


1 


L 


L 


U L 






i 




i i 






SEGMENT C 


| 




L 


L 


1 


I 


LI L 










i i 










SEGMENT D 


1 


1 




LI L 


1 






















SEGMENT E 








1 














' i 










SEGMENT F 


U LI _ 




1 












U L 












SEGMENT G 




1 


L 






1 







ACTDAL DISPLAY: /— j J !—. '—. '—! —J .—' J 



SEGMENT f /_S_/ b 

DESIGNATION ,/ l r SE( - 

T ' D.P. 



FIGURE 2. Display Timing 



108 



OPERATION IN THE ADD AND SUBTRACT MODE 



If the terminate flag is set, an "=" key will result in a 
constant add/subtract. The number in the accumulator 
will be added to (or subtracted from) the number being 
displayed. The result is right-justified and displayed in 
the entry register. Accumulator and mode registers are 
not altered, allowing for constant operations. 

If the terminate flag is not set and a number has been 
entered from the keyboard, or memory register, a "+," 
"— ," "x" or ' ,J r" key will result in an addition or 
subtraction. The entry register will be added to or sub- 
tracted from the accumulator and the new running total 
will be displayed in the entry register and copied into 
the accumulator register. The mode will be altered 
according to which key is entered. 

If the terminate flag is not set, and a number has not 
been entered from the keyboard, or memory, a "+," 
"~," "x" ,J -r" key will only change the mode register 
to the new key entry. 

If the terminate flag is not set, an "=" key will add/ 
subtract the number being displayed to/from the number 
in the accumulator register. The number being displayed 
is transferred to the accumulator, and the result of the 
operation is displayed in the entry register. The terminate 
flag is set, conditioning the calculator for constant, 
add/subtract operation. The number being displayed 
previous to the "=" key is stored in the accumulator as 
the constant. 

Operation of the "%" key in add/subtract mode, with 
the terminate flag reset, will multiply the accumulator 
by the last entry, divide the result by 100, and display it 
in the entry register. The mode register remains as it was 
in the add or subtract mode. All of the above is required 
to perform the percent add on or discount problems. 
Depression of an "=" key after the "%" key will either 
tax or discount the original number as a function of the 
mode register and the last entry. 

Operation of the "%" key in add/subtract mode, with 
the terminate flag set, will shift the decimal point of the 
number being displayed two places to the left and copy 
it into the accumulator register. The mode is set to 
multiply and the terminate flag remains set. 

OPERATION IN THE MULTIPLY MODE 



If the terminate flag is not set, an "=" key will signal 
the end of a problem. The number in the display will be 
multiplied by the contents of the accumulator, and the 
results will be displayed in the entry register. The number 
previously in the entry register is stored in the accumu- 
lator register and the terminate flag is set. 

If the terminate flag is not set, and a number has been 
entered from the keyboard or memory register, a "+," 
"-," "x" or "+" key will result in a multiplication. The 
number being displayed wilt be multiplied by the num- 
ber residing in the accumulator register. The result will 
be copied into the accumulator and displayed in the 
entry register. The mode register is up-dated as a func- 
tion of the key depressed. 

Operation of the "%" key while in multiply mode looks 
exactly the same as an "=" key except the decimal 
point of the display is shifted two positions to the left 
before the multiplication takes place. 



OPERATION IN THE DIVIDE MODE 

If the terminate flag is set, an "=" key will result in 
constant divide operation. The number being displayed 
is divided by the constant stored in the accumulator 
register. The accumulator and mode registers are not 
altered allowing for constant operations. Repeated de- 
pressions of the "=" key will result in repeated divisions 
by the constant. Thus, it is possible to raise a number to 
a negative integer power using the sequence: "C/CE," 
"C/CE," "1," "V "No.," "=," "=,"etc. 

If the terminate flag is not set, an "=" key will signal 
the end of a problem. The number in the accumulator 
register will be divided by the number being displayed. 
The result is transferred to the entry register and dis- 
played. The terminate flag is set and the divisor is stored 
in the accumulator register. 

If the terminate flag is not set, a "+," "— ," "x" or "-f" 
key will result in a division. The number in the accumu- 
lator register will be divided by the number being 
displayed. The results are displayed in the entry register, 
and a copy of the result is stored in the accumulator. 
The mode register is modified to reflect the latest key 
entry. 



If the terminate flag is set, an "=" key will result in a 
constant multiply operation. The number being displayed 
is multiplied by the constant stored in the accumulator 
register. The result is displayed in the entry register and 
the accumulator and mode registers are not altered, 
allowing for constant operation. Repeated depressions 
of the "=" key can be used to raise a number to an 
integer power, i.e., "C/CE," "C/CE," "5,2," "x," "=," 
"-," "=," computes 5.2 4 . 

The constant in multiplication, as well as in addition, 
subtraction and division is the last number entered. For 
the sequence: "C/CE," "C/CE," "3," "~," "4," "x," "2," 
"="the constant multiplier for future problems is 2. 



Operation of the "%" key while in divide mode looks 
exactly the same as the "=" key except the decimal 
point of the display is shifted two positions to the left 
before division takes place. 

ERROR CONDITIONS 

If any of the operations mentioned above generates a 
number larger than 9999 9999, an error will occur. An 
error is indicated by displaying the eight most significant 
digits and sign with all nine decimal points. The first 
depression of the "C/CE" key will clear the error condi- 
tion, and all registers except the memory register. 



8-109 



It is not possible to generate an error during number entry. 
The ninth and subsequent digits entered are ignored. 

POWER-ON CONDITION 



If the error condition is displayed, one depression will 
clear the error, and all registers except the memory 
register. The machine could not be in the number entry 
condition with the error flag set. 



The MM5794 has an internal power-on clear circuit 
which clears all registers to zero, places the mode to add 
and sets the terminate flag. A zero and decimal point 
are displayed. 

KEYBOARD BOUNCE AND NOISE REJECTION 

The MM5794 is designed to interface with most low cost 
keyboards, which are often the least desirable from a 
false or multiple entry standpoint. 

A key closure is sensed by the calculator chip when one 
of the key inputs, K1, K2, K3 or K4 is forced more 
positive than the Logical High Level specified in the 
electrical specifications. An internal counter is started 
as a result of the closure. The key operation begins after 
eleven word times if the Key Input is still at a Logical 
High Level. As long as the key is held down (and the 
Key Input remains high) no further entry is allowed. 
When the Key Input changes to a Logical Low Level, the 
internal counter starts an eleven word timeout for key 
release. During both, entry and release timeouts, the 
Key Inputs are sampled every word time for valid levels. 
If they are found invalid, the counter is reset and the 
calculator resumes scanning the keyboard. 

TEST FEATURES 

Several features have been designed into the MM5794 
to facilitate testing. One is to allow the key debounce 
timing to be modified, and the second performs a 
"segment test" function which turns on all segments for 
all digit times, with no interdigit blanking. The key 
bounce time can be reduced from eleven word times to 
one if a key closure is made between D9 and K2. 
"Segment Test" occurs when K3 is connected to D9. 
Closures for test operations are not debounced, and also 
may occur simultaneously with normal key closures if 
diodes are used to isolate the D-Lines from each other. 
The test features are active for every word time the 
Test switch closure is maintained. These test matrix 
entries are isolated internally from the normal calculator 
keys, allowing simultaneous entry of "test" keys and 
"calculator" keys, except for K3 keys during "Segment 
Test." 

FUNCTION OF KEYS 

Some of the keys operate differently when in the data 
or number entry condition. The MM5794 switches to 
entry condition when entering numbers and leaves this 
condition after most function keys. The following para- 
graphs discuss each of the keys on a full keyboard and 
the action taken when they are depressed. The earlier 
paragraphs which discussed the action of "+," "-," "x," 
"H-" and "%" keys and the examples given in later 
sections will aid in further explaining these actions. 

Clear Key, "CE/C" 

While in the number entry condition, one depression 
will clear the entry register to zero and recall the 
accumulator for display. The machine then leaves the 
number entry state. 



If the error flag is not set and the machine is not in the 
number entry condition, one depression of "CE/C" key 
will clear the entry and accumulator registers. It also 
places the machine in the add mode and sets the termi- 
nate flag. The memory register remains unchanged. 

Number Keys 0-9 

If not in the number entry condition, a number key will 
clear the display and then enter the value of the key 
into the LSD. The digits are displayed as they are entered 
and the machine assumes the number entry condition. 

If in the number entry condition, the entry register is 
shifted left one position and the key depressed is entered 
into the LSD. If there is a number in the most significant 
digit position (9th) the entry register is then shifted 
right one position and the entry is lost. 

Square Root Key, "V 

The square root key extracts the square root of the 
absolute value of the number being displayed in the 
entry register. 

The mode of the calculator remains unchanged. This 
enables square root operations in the middle of chain 
calculations. For example: 

KEY DISPLAY KEY DISPLAY KEY DISPLAY 



A A 


A 


A 


11 


11 


V~ Va 


X 


A 


+ 


11. 


+ Va 


B 


B 


5 


5 


B B 


V" 


VB 


= 


16. 


V" Vb 


= 


aVb 


V^ 


4. 


= Va+Vb 






6 
9 


6. 

11 

9 

3. 



Square Key, "X 2 " 

Depression of the "Square" key copies the number being 
displayed into the accumulator register, and performs a 
multiplication. On completion of the square operation, 
the results are displayed in the entry register, the original 
number is stored in the accumulator and the mode of the 
calculator is unchanged. Entering a number to start a 
new entry will first clear the entry register. 

Memory Save Key, "MS" 

The "MS" key transfers the number being displayed to 
the memory register. The display remains unaltered. 

Memory Recall Key, "MR" 

The "MR" key recalls the number being stored in the 
memory register and displays it in the entry register. 
This number can then be used as a new number entry. 



8-110 



Memory Store Key, "MS" 


1. Simple addit 


on or subtraction (continued) 


The "MS" key transfers the number being displayed in 


KEYS 


DISPLAY 


COMMENTS 


the entry register to the memory register. The arithmetic 


+ 


3. 


Sets add mode 


status of the calculator is not changed. 


2 


2 






+ 


5. 


Completes addition, 
resets add mode 


Memory Plus Key, "M+" 


- 


5. 


Sets subtraction 


When the "M+" key is depressed, the number being 


4.355 


4.3 5 5 


mode 


displayed is added to the contents of the memory and 




0.6 4 5 


Completes subtrac- 


the results, providing there is no overflow, are placed in 






tion. Sets terminate 


the memory. The calculator wilt be out of the data 






mode. 

Sets add mode 


entry mode. 


+ 


0.6 4 5 


If an overflow occurs, the contents of the memory are 


3.25 


3.2 5 


Starts Digit Entry 


not altered. The display shows the eight most significant 


CS 


3.2 5 


Changes Sign 


digits and sign of the results with all nine decimal points. 


4 


-3.2 5 4 


Continues Digit Entry 




+ 


-2.6 9 


Completes signed 
addition, sets add 


Memory Minus Key, "M" 






mode 


This key operates like the "M+" key only the displayed 


1 


1 




number is subtracted from memory. 




1.609 


Completes signed 
addition, sets termin- 
ate mode 


Plus, Minus, Multiply and Divide Keys, "+," "-," "x," "->" 








These keys terminate a number entry, complete the 








operation designated by the mode register and update 


2. Constant addition or subtract 


on (second factor 


the mode register for the next operation. A more detailed 


constantl 






explanation of these keys is found in the description 








of modes. 


KEYS 

3 


DISPLAY 

3 
3. 


COMMENTS 




Sets subtract mode 


Equal Key, "=" 


2 


2 






+ 


1. 


Completes subtrac- 


This key terminates a number entry, complete the 






tion, sets add mode 


operation designated by the mode register and sets the 


6 


6 




terminate flag. 


= 


7. 


Completes addition, 
saves (6) as constant, 


Percent Key, "%" 


.5 


.5 


sets terminate mode 


Following a clear-all operation or a number entry 


= 


6.5 


Completes constant 


proceeded by a clear all operation, this key shifts the 






addition constant-6 


decimal point of the number being displayed two places 


7 


7 




to the left, copies it into the accumulating register and 


- 


7. 


Sets subtraction 


establishes the multiply mode. 






mode, resets termin- 
ate mode 


While in multiply or divide mode, this key shifts the 


3 


3 




displayed decimal point two places to the left, completes 


= 


4. 


Completes subtrac- 


the multiplication or division and sets the terminate flag. 






tion, sets terminate 
mode, saves 3 as a 


In add or subtract mode, this key shifts the displayed 






constant 


decimal point two places to the left, multiplies the 


8 


8 




display times the accumulating register, places the pro- 


EX 


3. 


Exchanges entry, and 


duct in the entry register and leaves the accumulator 






constant 


register and mode register undisturbed. This permits 


= 


-5. 


Completes subtrac- 


automatic calculation of net by depression of the "=" 






tion constant = .8 


key. The terminate flag is not altered. 


9 


9 








1. 


Completes subtrac- 
tion constant - 8 


SAMPLE PROBLEMS 








1 . Simple addition or subtraction 


3. Simple mult 


plication 




KEYS DISPLAY COMMENTS 

C/CE 


KEYS 


DISPLAY 


COMMENTS 


3.1 


3.1 


Start multiplication 


3 3 Start addition pro- 






problem 


blem 









8-111 



3. Simple 


multiplication (continued) 


5. Constant multiplication (continued) 




KEYS 




DISPLAY 


COMMENTS 


KEYS 


DISPLAY 




COMMENTS 


X 
6 




3.1 


Sets multiply mode 


„ 


4 3 2. 


Coir 


pietes constant 




6 
1 8.6 


Completes multipli- 
cation, sets terminate 


3 
X 


3 
3. 


multiplication 
constant = 12 
Sets multiply mode, 










mode 






resets termination 
















mot 


e 












4 


3. 


Sets 


add mode. 


4. Chain muftip! 


cation 










Second function key 
only modifies mode 


KEYS 




DISPLAY 




COMMENTS 


X 


3. 
3. 


Sets 
Sets 


subtract mode 
multiply mode 












= 


9. 


Completes multipli- 


3 

+ 
4 






3 
3 

4 


Sets add mode 






cati 
tion 


jn. Sets termina- 
mode 


X 






7. 


Completes addition, 










6 








sets multiply mode 












D 

4 2. 


Completes multipli- 


6. Simple div 


sion 














cation, sets subtract 
mode 


KEYS 


DISPLAY 




COMMENTS 


2 






2 












= 




4 0. 


Completes subtrac- 


4 


4 
4. 
3 
3 
.3333333 














tion, se